src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "glsl/glsl_parser_extras.h"
  31 #include "main/shaderobj.h"
  32 #include "main/uniforms.h"
  33 #include "util/debug.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  88       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  89    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = false;
  90    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
  91       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
  92    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  93       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  94    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  95    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  96
  97    nir_shader_compiler_options *nir_options =
  98       rzalloc(compiler, nir_shader_compiler_options);
  99    nir_options->native_integers = true;
 100    /* In order to help allow for better CSE at the NIR level we tell NIR
 101     * to split all ffma instructions during opt_algebraic and we then
 102     * re-combine them as a later step.
 103     */
 104    nir_options->lower_ffma = true;
 105    nir_options->lower_sub = true;
 106    /* In the vec4 backend, our dpN instruction replicates its result to all
 107     * the components of a vec4.  We would like NIR to give us replicated fdot
 108     * instructions because it can optimize better for us.
 109     *
 110     * For the FS backend, it should be lowered away by the scalarizing pass so
 111     * we should never see fdot anyway.
 112     */
 113    nir_options->fdot_replicates = true;
 114
 115    /* We want the GLSL compiler to emit code that uses condition codes */
 116    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 117       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 118       compiler->glsl_compiler_options[i].MaxIfDepth =
 119          devinfo->gen < 6 ? 16 : UINT_MAX;
 120
 121       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 122       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 123       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 124       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 125       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 126       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 127
 128       bool is_scalar = compiler->scalar_stage[i];
 129
 130       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 131       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 132       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 133
 134       /* !ARB_gpu_shader5 */
 135       if (devinfo->gen < 7)
 136          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 137
 138       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 139
 140       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 141    }
 142
 143    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 144    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 145
 146    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 147       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 148
 149    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 150       .LowerShaderSharedVariables = true;
 151
 152    return compiler;
 153 }
 154
 155 extern "C" struct gl_shader *
 156 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 157 {
 158    struct brw_shader *shader;
 159
 160    shader = rzalloc(NULL, struct brw_shader);
 161    if (shader) {
 162       shader->base.Type = type;
 163       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 164       shader->base.Name = name;
 165       _mesa_init_shader(ctx, &shader->base);
 166    }
 167
 168    return &shader->base;
 169 }
 170
 171 extern "C" void
 172 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 173                       unsigned surf_index)
 174 {
 175    assert(surf_index < BRW_MAX_SURFACES);
 176
 177    prog_data->binding_table.size_bytes =
 178       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 179 }
 180
 181 enum brw_reg_type
 182 brw_type_for_base_type(const struct glsl_type *type)
 183 {
 184    switch (type->base_type) {
 185    case GLSL_TYPE_FLOAT:
 186       return BRW_REGISTER_TYPE_F;
 187    case GLSL_TYPE_INT:
 188    case GLSL_TYPE_BOOL:
 189    case GLSL_TYPE_SUBROUTINE:
 190       return BRW_REGISTER_TYPE_D;
 191    case GLSL_TYPE_UINT:
 192       return BRW_REGISTER_TYPE_UD;
 193    case GLSL_TYPE_ARRAY:
 194       return brw_type_for_base_type(type->fields.array);
 195    case GLSL_TYPE_STRUCT:
 196    case GLSL_TYPE_SAMPLER:
 197    case GLSL_TYPE_ATOMIC_UINT:
 198       /* These should be overridden with the type of the member when
 199        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 200        * way to trip up if we don't.
 201        */
 202       return BRW_REGISTER_TYPE_UD;
 203    case GLSL_TYPE_IMAGE:
 204       return BRW_REGISTER_TYPE_UD;
 205    case GLSL_TYPE_VOID:
 206    case GLSL_TYPE_ERROR:
 207    case GLSL_TYPE_INTERFACE:
 208    case GLSL_TYPE_DOUBLE:
 209       unreachable("not reached");
 210    }
 211
 212    return BRW_REGISTER_TYPE_F;
 213 }
 214
 215 enum brw_conditional_mod
 216 brw_conditional_for_comparison(unsigned int op)
 217 {
 218    switch (op) {
 219    case ir_binop_less:
 220       return BRW_CONDITIONAL_L;
 221    case ir_binop_greater:
 222       return BRW_CONDITIONAL_G;
 223    case ir_binop_lequal:
 224       return BRW_CONDITIONAL_LE;
 225    case ir_binop_gequal:
 226       return BRW_CONDITIONAL_GE;
 227    case ir_binop_equal:
 228    case ir_binop_all_equal: /* same as equal for scalars */
 229       return BRW_CONDITIONAL_Z;
 230    case ir_binop_nequal:
 231    case ir_binop_any_nequal: /* same as nequal for scalars */
 232       return BRW_CONDITIONAL_NZ;
 233    default:
 234       unreachable("not reached: bad operation for comparison");
 235    }
 236 }
 237
 238 uint32_t
 239 brw_math_function(enum opcode op)
 240 {
 241    switch (op) {
 242    case SHADER_OPCODE_RCP:
 243       return BRW_MATH_FUNCTION_INV;
 244    case SHADER_OPCODE_RSQ:
 245       return BRW_MATH_FUNCTION_RSQ;
 246    case SHADER_OPCODE_SQRT:
 247       return BRW_MATH_FUNCTION_SQRT;
 248    case SHADER_OPCODE_EXP2:
 249       return BRW_MATH_FUNCTION_EXP;
 250    case SHADER_OPCODE_LOG2:
 251       return BRW_MATH_FUNCTION_LOG;
 252    case SHADER_OPCODE_POW:
 253       return BRW_MATH_FUNCTION_POW;
 254    case SHADER_OPCODE_SIN:
 255       return BRW_MATH_FUNCTION_SIN;
 256    case SHADER_OPCODE_COS:
 257       return BRW_MATH_FUNCTION_COS;
 258    case SHADER_OPCODE_INT_QUOTIENT:
 259       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 260    case SHADER_OPCODE_INT_REMAINDER:
 261       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 262    default:
 263       unreachable("not reached: unknown math function");
 264    }
 265 }
 266
 267 uint32_t
 268 brw_texture_offset(int *offsets, unsigned num_components)
 269 {
 270    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 271
 272    /* Combine all three offsets into a single unsigned dword:
 273     *
 274     *    bits 11:8 - U Offset (X component)
 275     *    bits  7:4 - V Offset (Y component)
 276     *    bits  3:0 - R Offset (Z component)
 277     */
 278    unsigned offset_bits = 0;
 279    for (unsigned i = 0; i < num_components; i++) {
 280       const unsigned shift = 4 * (2 - i);
 281       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 282    }
 283    return offset_bits;
 284 }
 285
 286 const char *
 287 brw_instruction_name(enum opcode op)
 288 {
 289    switch (op) {
 290    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 291       assert(opcode_descs[op].name);
 292       return opcode_descs[op].name;
 293    case FS_OPCODE_FB_WRITE:
 294       return "fb_write";
 295    case FS_OPCODE_FB_WRITE_LOGICAL:
 296       return "fb_write_logical";
 297    case FS_OPCODE_PACK_STENCIL_REF:
 298       return "pack_stencil_ref";
 299    case FS_OPCODE_BLORP_FB_WRITE:
 300       return "blorp_fb_write";
 301    case FS_OPCODE_REP_FB_WRITE:
 302       return "rep_fb_write";
 303
 304    case SHADER_OPCODE_RCP:
 305       return "rcp";
 306    case SHADER_OPCODE_RSQ:
 307       return "rsq";
 308    case SHADER_OPCODE_SQRT:
 309       return "sqrt";
 310    case SHADER_OPCODE_EXP2:
 311       return "exp2";
 312    case SHADER_OPCODE_LOG2:
 313       return "log2";
 314    case SHADER_OPCODE_POW:
 315       return "pow";
 316    case SHADER_OPCODE_INT_QUOTIENT:
 317       return "int_quot";
 318    case SHADER_OPCODE_INT_REMAINDER:
 319       return "int_rem";
 320    case SHADER_OPCODE_SIN:
 321       return "sin";
 322    case SHADER_OPCODE_COS:
 323       return "cos";
 324
 325    case SHADER_OPCODE_TEX:
 326       return "tex";
 327    case SHADER_OPCODE_TEX_LOGICAL:
 328       return "tex_logical";
 329    case SHADER_OPCODE_TXD:
 330       return "txd";
 331    case SHADER_OPCODE_TXD_LOGICAL:
 332       return "txd_logical";
 333    case SHADER_OPCODE_TXF:
 334       return "txf";
 335    case SHADER_OPCODE_TXF_LOGICAL:
 336       return "txf_logical";
 337    case SHADER_OPCODE_TXL:
 338       return "txl";
 339    case SHADER_OPCODE_TXL_LOGICAL:
 340       return "txl_logical";
 341    case SHADER_OPCODE_TXS:
 342       return "txs";
 343    case SHADER_OPCODE_TXS_LOGICAL:
 344       return "txs_logical";
 345    case FS_OPCODE_TXB:
 346       return "txb";
 347    case FS_OPCODE_TXB_LOGICAL:
 348       return "txb_logical";
 349    case SHADER_OPCODE_TXF_CMS:
 350       return "txf_cms";
 351    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 352       return "txf_cms_logical";
 353    case SHADER_OPCODE_TXF_CMS_W:
 354       return "txf_cms_w";
 355    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 356       return "txf_cms_w_logical";
 357    case SHADER_OPCODE_TXF_UMS:
 358       return "txf_ums";
 359    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 360       return "txf_ums_logical";
 361    case SHADER_OPCODE_TXF_MCS:
 362       return "txf_mcs";
 363    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 364       return "txf_mcs_logical";
 365    case SHADER_OPCODE_LOD:
 366       return "lod";
 367    case SHADER_OPCODE_LOD_LOGICAL:
 368       return "lod_logical";
 369    case SHADER_OPCODE_TG4:
 370       return "tg4";
 371    case SHADER_OPCODE_TG4_LOGICAL:
 372       return "tg4_logical";
 373    case SHADER_OPCODE_TG4_OFFSET:
 374       return "tg4_offset";
 375    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 376       return "tg4_offset_logical";
 377    case SHADER_OPCODE_SAMPLEINFO:
 378       return "sampleinfo";
 379
 380    case SHADER_OPCODE_SHADER_TIME_ADD:
 381       return "shader_time_add";
 382
 383    case SHADER_OPCODE_UNTYPED_ATOMIC:
 384       return "untyped_atomic";
 385    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 386       return "untyped_atomic_logical";
 387    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 388       return "untyped_surface_read";
 389    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 390       return "untyped_surface_read_logical";
 391    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 392       return "untyped_surface_write";
 393    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 394       return "untyped_surface_write_logical";
 395    case SHADER_OPCODE_TYPED_ATOMIC:
 396       return "typed_atomic";
 397    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 398       return "typed_atomic_logical";
 399    case SHADER_OPCODE_TYPED_SURFACE_READ:
 400       return "typed_surface_read";
 401    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 402       return "typed_surface_read_logical";
 403    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 404       return "typed_surface_write";
 405    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 406       return "typed_surface_write_logical";
 407    case SHADER_OPCODE_MEMORY_FENCE:
 408       return "memory_fence";
 409
 410    case SHADER_OPCODE_LOAD_PAYLOAD:
 411       return "load_payload";
 412
 413    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 414       return "gen4_scratch_read";
 415    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 416       return "gen4_scratch_write";
 417    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 418       return "gen7_scratch_read";
 419    case SHADER_OPCODE_URB_WRITE_SIMD8:
 420       return "gen8_urb_write_simd8";
 421    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 422       return "gen8_urb_write_simd8_per_slot";
 423    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 424       return "gen8_urb_write_simd8_masked";
 425    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 426       return "gen8_urb_write_simd8_masked_per_slot";
 427    case SHADER_OPCODE_URB_READ_SIMD8:
 428       return "urb_read_simd8";
 429    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 430       return "urb_read_simd8_per_slot";
 431
 432    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 433       return "find_live_channel";
 434    case SHADER_OPCODE_BROADCAST:
 435       return "broadcast";
 436
 437    case VEC4_OPCODE_MOV_BYTES:
 438       return "mov_bytes";
 439    case VEC4_OPCODE_PACK_BYTES:
 440       return "pack_bytes";
 441    case VEC4_OPCODE_UNPACK_UNIFORM:
 442       return "unpack_uniform";
 443
 444    case FS_OPCODE_DDX_COARSE:
 445       return "ddx_coarse";
 446    case FS_OPCODE_DDX_FINE:
 447       return "ddx_fine";
 448    case FS_OPCODE_DDY_COARSE:
 449       return "ddy_coarse";
 450    case FS_OPCODE_DDY_FINE:
 451       return "ddy_fine";
 452
 453    case FS_OPCODE_CINTERP:
 454       return "cinterp";
 455    case FS_OPCODE_LINTERP:
 456       return "linterp";
 457
 458    case FS_OPCODE_PIXEL_X:
 459       return "pixel_x";
 460    case FS_OPCODE_PIXEL_Y:
 461       return "pixel_y";
 462
 463    case FS_OPCODE_GET_BUFFER_SIZE:
 464       return "fs_get_buffer_size";
 465
 466    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 467       return "uniform_pull_const";
 468    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 469       return "uniform_pull_const_gen7";
 470    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 471       return "varying_pull_const";
 472    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 473       return "varying_pull_const_gen7";
 474
 475    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 476       return "mov_dispatch_to_flags";
 477    case FS_OPCODE_DISCARD_JUMP:
 478       return "discard_jump";
 479
 480    case FS_OPCODE_SET_SAMPLE_ID:
 481       return "set_sample_id";
 482    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 483       return "set_simd4x2_offset";
 484
 485    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 486       return "pack_half_2x16_split";
 487    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 488       return "unpack_half_2x16_split_x";
 489    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 490       return "unpack_half_2x16_split_y";
 491
 492    case FS_OPCODE_PLACEHOLDER_HALT:
 493       return "placeholder_halt";
 494
 495    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 496       return "interp_centroid";
 497    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 498       return "interp_sample";
 499    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 500       return "interp_shared_offset";
 501    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 502       return "interp_per_slot_offset";
 503
 504    case VS_OPCODE_URB_WRITE:
 505       return "vs_urb_write";
 506    case VS_OPCODE_PULL_CONSTANT_LOAD:
 507       return "pull_constant_load";
 508    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 509       return "pull_constant_load_gen7";
 510
 511    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 512       return "set_simd4x2_header_gen9";
 513
 514    case VS_OPCODE_GET_BUFFER_SIZE:
 515       return "vs_get_buffer_size";
 516
 517    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 518       return "unpack_flags_simd4x2";
 519
 520    case GS_OPCODE_URB_WRITE:
 521       return "gs_urb_write";
 522    case GS_OPCODE_URB_WRITE_ALLOCATE:
 523       return "gs_urb_write_allocate";
 524    case GS_OPCODE_THREAD_END:
 525       return "gs_thread_end";
 526    case GS_OPCODE_SET_WRITE_OFFSET:
 527       return "set_write_offset";
 528    case GS_OPCODE_SET_VERTEX_COUNT:
 529       return "set_vertex_count";
 530    case GS_OPCODE_SET_DWORD_2:
 531       return "set_dword_2";
 532    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 533       return "prepare_channel_masks";
 534    case GS_OPCODE_SET_CHANNEL_MASKS:
 535       return "set_channel_masks";
 536    case GS_OPCODE_GET_INSTANCE_ID:
 537       return "get_instance_id";
 538    case GS_OPCODE_FF_SYNC:
 539       return "ff_sync";
 540    case GS_OPCODE_SET_PRIMITIVE_ID:
 541       return "set_primitive_id";
 542    case GS_OPCODE_SVB_WRITE:
 543       return "gs_svb_write";
 544    case GS_OPCODE_SVB_SET_DST_INDEX:
 545       return "gs_svb_set_dst_index";
 546    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 547       return "gs_ff_sync_set_primitives";
 548    case CS_OPCODE_CS_TERMINATE:
 549       return "cs_terminate";
 550    case SHADER_OPCODE_BARRIER:
 551       return "barrier";
 552    case SHADER_OPCODE_MULH:
 553       return "mulh";
 554    case SHADER_OPCODE_MOV_INDIRECT:
 555       return "mov_indirect";
 556
 557    case VEC4_OPCODE_URB_READ:
 558       return "urb_read";
 559    case TCS_OPCODE_GET_INSTANCE_ID:
 560       return "tcs_get_instance_id";
 561    case TCS_OPCODE_URB_WRITE:
 562       return "tcs_urb_write";
 563    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 564       return "tcs_set_input_urb_offsets";
 565    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 566       return "tcs_set_output_urb_offsets";
 567    case TCS_OPCODE_GET_PRIMITIVE_ID:
 568       return "tcs_get_primitive_id";
 569    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 570       return "tcs_create_barrier_header";
 571    case TCS_OPCODE_SRC0_010_IS_ZERO:
 572       return "tcs_src0<0,1,0>_is_zero";
 573    case TCS_OPCODE_RELEASE_INPUT:
 574       return "tcs_release_input";
 575    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 576       return "tes_create_input_read_header";
 577    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 578       return "tes_add_indirect_urb_offset";
 579    case TES_OPCODE_GET_PRIMITIVE_ID:
 580       return "tes_get_primitive_id";
 581    }
 582
 583    unreachable("not reached");
 584 }
 585
 586 bool
 587 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 588 {
 589    union {
 590       unsigned ud;
 591       int d;
 592       float f;
 593    } imm = { reg->ud }, sat_imm = { 0 };
 594
 595    switch (type) {
 596    case BRW_REGISTER_TYPE_UD:
 597    case BRW_REGISTER_TYPE_D:
 598    case BRW_REGISTER_TYPE_UW:
 599    case BRW_REGISTER_TYPE_W:
 600    case BRW_REGISTER_TYPE_UQ:
 601    case BRW_REGISTER_TYPE_Q:
 602       /* Nothing to do. */
 603       return false;
 604    case BRW_REGISTER_TYPE_F:
 605       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 606       break;
 607    case BRW_REGISTER_TYPE_UB:
 608    case BRW_REGISTER_TYPE_B:
 609       unreachable("no UB/B immediates");
 610    case BRW_REGISTER_TYPE_V:
 611    case BRW_REGISTER_TYPE_UV:
 612    case BRW_REGISTER_TYPE_VF:
 613       unreachable("unimplemented: saturate vector immediate");
 614    case BRW_REGISTER_TYPE_DF:
 615    case BRW_REGISTER_TYPE_HF:
 616       unreachable("unimplemented: saturate DF/HF immediate");
 617    }
 618
 619    if (imm.ud != sat_imm.ud) {
 620       reg->ud = sat_imm.ud;
 621       return true;
 622    }
 623    return false;
 624 }
 625
 626 bool
 627 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 628 {
 629    switch (type) {
 630    case BRW_REGISTER_TYPE_D:
 631    case BRW_REGISTER_TYPE_UD:
 632       reg->d = -reg->d;
 633       return true;
 634    case BRW_REGISTER_TYPE_W:
 635    case BRW_REGISTER_TYPE_UW:
 636       reg->d = -(int16_t)reg->ud;
 637       return true;
 638    case BRW_REGISTER_TYPE_F:
 639       reg->f = -reg->f;
 640       return true;
 641    case BRW_REGISTER_TYPE_VF:
 642       reg->ud ^= 0x80808080;
 643       return true;
 644    case BRW_REGISTER_TYPE_UB:
 645    case BRW_REGISTER_TYPE_B:
 646       unreachable("no UB/B immediates");
 647    case BRW_REGISTER_TYPE_UV:
 648    case BRW_REGISTER_TYPE_V:
 649       assert(!"unimplemented: negate UV/V immediate");
 650    case BRW_REGISTER_TYPE_UQ:
 651    case BRW_REGISTER_TYPE_Q:
 652       assert(!"unimplemented: negate UQ/Q immediate");
 653    case BRW_REGISTER_TYPE_DF:
 654    case BRW_REGISTER_TYPE_HF:
 655       assert(!"unimplemented: negate DF/HF immediate");
 656    }
 657
 658    return false;
 659 }
 660
 661 bool
 662 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 663 {
 664    switch (type) {
 665    case BRW_REGISTER_TYPE_D:
 666       reg->d = abs(reg->d);
 667       return true;
 668    case BRW_REGISTER_TYPE_W:
 669       reg->d = abs((int16_t)reg->ud);
 670       return true;
 671    case BRW_REGISTER_TYPE_F:
 672       reg->f = fabsf(reg->f);
 673       return true;
 674    case BRW_REGISTER_TYPE_VF:
 675       reg->ud &= ~0x80808080;
 676       return true;
 677    case BRW_REGISTER_TYPE_UB:
 678    case BRW_REGISTER_TYPE_B:
 679       unreachable("no UB/B immediates");
 680    case BRW_REGISTER_TYPE_UQ:
 681    case BRW_REGISTER_TYPE_UD:
 682    case BRW_REGISTER_TYPE_UW:
 683    case BRW_REGISTER_TYPE_UV:
 684       /* Presumably the absolute value modifier on an unsigned source is a
 685        * nop, but it would be nice to confirm.
 686        */
 687       assert(!"unimplemented: abs unsigned immediate");
 688    case BRW_REGISTER_TYPE_V:
 689       assert(!"unimplemented: abs V immediate");
 690    case BRW_REGISTER_TYPE_Q:
 691       assert(!"unimplemented: abs Q immediate");
 692    case BRW_REGISTER_TYPE_DF:
 693    case BRW_REGISTER_TYPE_HF:
 694       assert(!"unimplemented: abs DF/HF immediate");
 695    }
 696
 697    return false;
 698 }
 699
 700 backend_shader::backend_shader(const struct brw_compiler *compiler,
 701                                void *log_data,
 702                                void *mem_ctx,
 703                                const nir_shader *shader,
 704                                struct brw_stage_prog_data *stage_prog_data)
 705    : compiler(compiler),
 706      log_data(log_data),
 707      devinfo(compiler->devinfo),
 708      nir(shader),
 709      stage_prog_data(stage_prog_data),
 710      mem_ctx(mem_ctx),
 711      cfg(NULL),
 712      stage(shader->stage)
 713 {
 714    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 715    stage_name = _mesa_shader_stage_to_string(stage);
 716    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 717 }
 718
 719 bool
 720 backend_reg::equals(const backend_reg &r) const
 721 {
 722    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 723           reg_offset == r.reg_offset;
 724 }
 725
 726 bool
 727 backend_reg::is_zero() const
 728 {
 729    if (file != IMM)
 730       return false;
 731
 732    return d == 0;
 733 }
 734
 735 bool
 736 backend_reg::is_one() const
 737 {
 738    if (file != IMM)
 739       return false;
 740
 741    return type == BRW_REGISTER_TYPE_F
 742           ? f == 1.0
 743           : d == 1;
 744 }
 745
 746 bool
 747 backend_reg::is_negative_one() const
 748 {
 749    if (file != IMM)
 750       return false;
 751
 752    switch (type) {
 753    case BRW_REGISTER_TYPE_F:
 754       return f == -1.0;
 755    case BRW_REGISTER_TYPE_D:
 756       return d == -1;
 757    default:
 758       return false;
 759    }
 760 }
 761
 762 bool
 763 backend_reg::is_null() const
 764 {
 765    return file == ARF && nr == BRW_ARF_NULL;
 766 }
 767
 768
 769 bool
 770 backend_reg::is_accumulator() const
 771 {
 772    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 773 }
 774
 775 bool
 776 backend_reg::in_range(const backend_reg &r, unsigned n) const
 777 {
 778    return (file == r.file &&
 779            nr == r.nr &&
 780            reg_offset >= r.reg_offset &&
 781            reg_offset < r.reg_offset + n);
 782 }
 783
 784 bool
 785 backend_instruction::is_commutative() const
 786 {
 787    switch (opcode) {
 788    case BRW_OPCODE_AND:
 789    case BRW_OPCODE_OR:
 790    case BRW_OPCODE_XOR:
 791    case BRW_OPCODE_ADD:
 792    case BRW_OPCODE_MUL:
 793    case SHADER_OPCODE_MULH:
 794       return true;
 795    case BRW_OPCODE_SEL:
 796       /* MIN and MAX are commutative. */
 797       if (conditional_mod == BRW_CONDITIONAL_GE ||
 798           conditional_mod == BRW_CONDITIONAL_L) {
 799          return true;
 800       }
 801       /* fallthrough */
 802    default:
 803       return false;
 804    }
 805 }
 806
 807 bool
 808 backend_instruction::is_3src() const
 809 {
 810    return ::is_3src(opcode);
 811 }
 812
 813 bool
 814 backend_instruction::is_tex() const
 815 {
 816    return (opcode == SHADER_OPCODE_TEX ||
 817            opcode == FS_OPCODE_TXB ||
 818            opcode == SHADER_OPCODE_TXD ||
 819            opcode == SHADER_OPCODE_TXF ||
 820            opcode == SHADER_OPCODE_TXF_CMS ||
 821            opcode == SHADER_OPCODE_TXF_CMS_W ||
 822            opcode == SHADER_OPCODE_TXF_UMS ||
 823            opcode == SHADER_OPCODE_TXF_MCS ||
 824            opcode == SHADER_OPCODE_TXL ||
 825            opcode == SHADER_OPCODE_TXS ||
 826            opcode == SHADER_OPCODE_LOD ||
 827            opcode == SHADER_OPCODE_TG4 ||
 828            opcode == SHADER_OPCODE_TG4_OFFSET);
 829 }
 830
 831 bool
 832 backend_instruction::is_math() const
 833 {
 834    return (opcode == SHADER_OPCODE_RCP ||
 835            opcode == SHADER_OPCODE_RSQ ||
 836            opcode == SHADER_OPCODE_SQRT ||
 837            opcode == SHADER_OPCODE_EXP2 ||
 838            opcode == SHADER_OPCODE_LOG2 ||
 839            opcode == SHADER_OPCODE_SIN ||
 840            opcode == SHADER_OPCODE_COS ||
 841            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 842            opcode == SHADER_OPCODE_INT_REMAINDER ||
 843            opcode == SHADER_OPCODE_POW);
 844 }
 845
 846 bool
 847 backend_instruction::is_control_flow() const
 848 {
 849    switch (opcode) {
 850    case BRW_OPCODE_DO:
 851    case BRW_OPCODE_WHILE:
 852    case BRW_OPCODE_IF:
 853    case BRW_OPCODE_ELSE:
 854    case BRW_OPCODE_ENDIF:
 855    case BRW_OPCODE_BREAK:
 856    case BRW_OPCODE_CONTINUE:
 857       return true;
 858    default:
 859       return false;
 860    }
 861 }
 862
 863 bool
 864 backend_instruction::can_do_source_mods() const
 865 {
 866    switch (opcode) {
 867    case BRW_OPCODE_ADDC:
 868    case BRW_OPCODE_BFE:
 869    case BRW_OPCODE_BFI1:
 870    case BRW_OPCODE_BFI2:
 871    case BRW_OPCODE_BFREV:
 872    case BRW_OPCODE_CBIT:
 873    case BRW_OPCODE_FBH:
 874    case BRW_OPCODE_FBL:
 875    case BRW_OPCODE_SUBB:
 876       return false;
 877    default:
 878       return true;
 879    }
 880 }
 881
 882 bool
 883 backend_instruction::can_do_saturate() const
 884 {
 885    switch (opcode) {
 886    case BRW_OPCODE_ADD:
 887    case BRW_OPCODE_ASR:
 888    case BRW_OPCODE_AVG:
 889    case BRW_OPCODE_DP2:
 890    case BRW_OPCODE_DP3:
 891    case BRW_OPCODE_DP4:
 892    case BRW_OPCODE_DPH:
 893    case BRW_OPCODE_F16TO32:
 894    case BRW_OPCODE_F32TO16:
 895    case BRW_OPCODE_LINE:
 896    case BRW_OPCODE_LRP:
 897    case BRW_OPCODE_MAC:
 898    case BRW_OPCODE_MAD:
 899    case BRW_OPCODE_MATH:
 900    case BRW_OPCODE_MOV:
 901    case BRW_OPCODE_MUL:
 902    case SHADER_OPCODE_MULH:
 903    case BRW_OPCODE_PLN:
 904    case BRW_OPCODE_RNDD:
 905    case BRW_OPCODE_RNDE:
 906    case BRW_OPCODE_RNDU:
 907    case BRW_OPCODE_RNDZ:
 908    case BRW_OPCODE_SEL:
 909    case BRW_OPCODE_SHL:
 910    case BRW_OPCODE_SHR:
 911    case FS_OPCODE_LINTERP:
 912    case SHADER_OPCODE_COS:
 913    case SHADER_OPCODE_EXP2:
 914    case SHADER_OPCODE_LOG2:
 915    case SHADER_OPCODE_POW:
 916    case SHADER_OPCODE_RCP:
 917    case SHADER_OPCODE_RSQ:
 918    case SHADER_OPCODE_SIN:
 919    case SHADER_OPCODE_SQRT:
 920       return true;
 921    default:
 922       return false;
 923    }
 924 }
 925
 926 bool
 927 backend_instruction::can_do_cmod() const
 928 {
 929    switch (opcode) {
 930    case BRW_OPCODE_ADD:
 931    case BRW_OPCODE_ADDC:
 932    case BRW_OPCODE_AND:
 933    case BRW_OPCODE_ASR:
 934    case BRW_OPCODE_AVG:
 935    case BRW_OPCODE_CMP:
 936    case BRW_OPCODE_CMPN:
 937    case BRW_OPCODE_DP2:
 938    case BRW_OPCODE_DP3:
 939    case BRW_OPCODE_DP4:
 940    case BRW_OPCODE_DPH:
 941    case BRW_OPCODE_F16TO32:
 942    case BRW_OPCODE_F32TO16:
 943    case BRW_OPCODE_FRC:
 944    case BRW_OPCODE_LINE:
 945    case BRW_OPCODE_LRP:
 946    case BRW_OPCODE_LZD:
 947    case BRW_OPCODE_MAC:
 948    case BRW_OPCODE_MACH:
 949    case BRW_OPCODE_MAD:
 950    case BRW_OPCODE_MOV:
 951    case BRW_OPCODE_MUL:
 952    case BRW_OPCODE_NOT:
 953    case BRW_OPCODE_OR:
 954    case BRW_OPCODE_PLN:
 955    case BRW_OPCODE_RNDD:
 956    case BRW_OPCODE_RNDE:
 957    case BRW_OPCODE_RNDU:
 958    case BRW_OPCODE_RNDZ:
 959    case BRW_OPCODE_SAD2:
 960    case BRW_OPCODE_SADA2:
 961    case BRW_OPCODE_SHL:
 962    case BRW_OPCODE_SHR:
 963    case BRW_OPCODE_SUBB:
 964    case BRW_OPCODE_XOR:
 965    case FS_OPCODE_CINTERP:
 966    case FS_OPCODE_LINTERP:
 967       return true;
 968    default:
 969       return false;
 970    }
 971 }
 972
 973 bool
 974 backend_instruction::reads_accumulator_implicitly() const
 975 {
 976    switch (opcode) {
 977    case BRW_OPCODE_MAC:
 978    case BRW_OPCODE_MACH:
 979    case BRW_OPCODE_SADA2:
 980       return true;
 981    default:
 982       return false;
 983    }
 984 }
 985
 986 bool
 987 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 988 {
 989    return writes_accumulator ||
 990           (devinfo->gen < 6 &&
 991            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 992             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 993              opcode != FS_OPCODE_CINTERP)));
 994 }
 995
 996 bool
 997 backend_instruction::has_side_effects() const
 998 {
 999    switch (opcode) {
1000    case SHADER_OPCODE_UNTYPED_ATOMIC:
1001    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1002    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1003    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1004    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1005    case SHADER_OPCODE_TYPED_ATOMIC:
1006    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1007    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1008    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1009    case SHADER_OPCODE_MEMORY_FENCE:
1010    case SHADER_OPCODE_URB_WRITE_SIMD8:
1011    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1012    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1013    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1014    case FS_OPCODE_FB_WRITE:
1015    case SHADER_OPCODE_BARRIER:
1016    case TCS_OPCODE_RELEASE_INPUT:
1017       return true;
1018    default:
1019       return false;
1020    }
1021 }
1022
1023 bool
1024 backend_instruction::is_volatile() const
1025 {
1026    switch (opcode) {
1027    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1028    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1029    case SHADER_OPCODE_TYPED_SURFACE_READ:
1030    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1031       return true;
1032    default:
1033       return false;
1034    }
1035 }
1036
1037 #ifndef NDEBUG
1038 static bool
1039 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1040 {
1041    bool found = false;
1042    foreach_inst_in_block (backend_instruction, i, block) {
1043       if (inst == i) {
1044          found = true;
1045       }
1046    }
1047    return found;
1048 }
1049 #endif
1050
1051 static void
1052 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1053 {
1054    for (bblock_t *block_iter = start_block->next();
1055         !block_iter->link.is_tail_sentinel();
1056         block_iter = block_iter->next()) {
1057       block_iter->start_ip += ip_adjustment;
1058       block_iter->end_ip += ip_adjustment;
1059    }
1060 }
1061
1062 void
1063 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1064 {
1065    if (!this->is_head_sentinel())
1066       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1067
1068    block->end_ip++;
1069
1070    adjust_later_block_ips(block, 1);
1071
1072    exec_node::insert_after(inst);
1073 }
1074
1075 void
1076 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1077 {
1078    if (!this->is_tail_sentinel())
1079       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1080
1081    block->end_ip++;
1082
1083    adjust_later_block_ips(block, 1);
1084
1085    exec_node::insert_before(inst);
1086 }
1087
1088 void
1089 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1090 {
1091    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1092
1093    unsigned num_inst = list->length();
1094
1095    block->end_ip += num_inst;
1096
1097    adjust_later_block_ips(block, num_inst);
1098
1099    exec_node::insert_before(list);
1100 }
1101
1102 void
1103 backend_instruction::remove(bblock_t *block)
1104 {
1105    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1106
1107    adjust_later_block_ips(block, -1);
1108
1109    if (block->start_ip == block->end_ip) {
1110       block->cfg->remove_block(block);
1111    } else {
1112       block->end_ip--;
1113    }
1114
1115    exec_node::remove();
1116 }
1117
1118 void
1119 backend_shader::dump_instructions()
1120 {
1121    dump_instructions(NULL);
1122 }
1123
1124 void
1125 backend_shader::dump_instructions(const char *name)
1126 {
1127    FILE *file = stderr;
1128    if (name && geteuid() != 0) {
1129       file = fopen(name, "w");
1130       if (!file)
1131          file = stderr;
1132    }
1133
1134    if (cfg) {
1135       int ip = 0;
1136       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1137          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1138             fprintf(file, "%4d: ", ip++);
1139          dump_instruction(inst, file);
1140       }
1141    } else {
1142       int ip = 0;
1143       foreach_in_list(backend_instruction, inst, &instructions) {
1144          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1145             fprintf(file, "%4d: ", ip++);
1146          dump_instruction(inst, file);
1147       }
1148    }
1149
1150    if (file != stderr) {
1151       fclose(file);
1152    }
1153 }
1154
1155 void
1156 backend_shader::calculate_cfg()
1157 {
1158    if (this->cfg)
1159       return;
1160    cfg = new(mem_ctx) cfg_t(&this->instructions);
1161 }
1162
1163 void
1164 backend_shader::invalidate_cfg()
1165 {
1166    ralloc_free(this->cfg);
1167    this->cfg = NULL;
1168 }
1169
1170 /**
1171  * Sets up the starting offsets for the groups of binding table entries
1172  * commong to all pipeline stages.
1173  *
1174  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1175  * unused but also make sure that addition of small offsets to them will
1176  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1177  */
1178 void
1179 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1180                                         const struct brw_device_info *devinfo,
1181                                         const struct gl_shader_program *shader_prog,
1182                                         const struct gl_program *prog,
1183                                         struct brw_stage_prog_data *stage_prog_data,
1184                                         uint32_t next_binding_table_offset)
1185 {
1186    const struct gl_shader *shader = NULL;
1187    int num_textures = _mesa_fls(prog->SamplersUsed);
1188
1189    if (shader_prog)
1190       shader = shader_prog->_LinkedShaders[stage];
1191
1192    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1193    next_binding_table_offset += num_textures;
1194
1195    if (shader) {
1196       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1197       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1198       next_binding_table_offset += shader->NumUniformBlocks;
1199
1200       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1201       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1202       next_binding_table_offset += shader->NumShaderStorageBlocks;
1203    } else {
1204       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1205       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1206    }
1207
1208    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1209       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1210       next_binding_table_offset++;
1211    } else {
1212       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1213    }
1214
1215    if (prog->UsesGather) {
1216       if (devinfo->gen >= 8) {
1217          stage_prog_data->binding_table.gather_texture_start =
1218             stage_prog_data->binding_table.texture_start;
1219       } else {
1220          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1221          next_binding_table_offset += num_textures;
1222       }
1223    } else {
1224       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1225    }
1226
1227    if (shader && shader->NumAtomicBuffers) {
1228       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1229       next_binding_table_offset += shader->NumAtomicBuffers;
1230    } else {
1231       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1232    }
1233
1234    if (shader && shader->NumImages) {
1235       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1236       next_binding_table_offset += shader->NumImages;
1237    } else {
1238       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1239    }
1240
1241    /* This may or may not be used depending on how the compile goes. */
1242    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1243    next_binding_table_offset++;
1244
1245    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1246
1247    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1248 }
1249
1250 static void
1251 setup_vec4_uniform_value(const gl_constant_value **params,
1252                          const gl_constant_value *values,
1253                          unsigned n)
1254 {
1255    static const gl_constant_value zero = { 0 };
1256
1257    for (unsigned i = 0; i < n; ++i)
1258       params[i] = &values[i];
1259
1260    for (unsigned i = n; i < 4; ++i)
1261       params[i] = &zero;
1262 }
1263
1264 void
1265 brw_setup_image_uniform_values(gl_shader_stage stage,
1266                                struct brw_stage_prog_data *stage_prog_data,
1267                                unsigned param_start_index,
1268                                const gl_uniform_storage *storage)
1269 {
1270    const gl_constant_value **param =
1271       &stage_prog_data->param[param_start_index];
1272
1273    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1274       const unsigned image_idx = storage->opaque[stage].index + i;
1275       const brw_image_param *image_param =
1276          &stage_prog_data->image_param[image_idx];
1277
1278       /* Upload the brw_image_param structure.  The order is expected to match
1279        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1280        */
1281       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1282          (const gl_constant_value *)&image_param->surface_idx, 1);
1283       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1284          (const gl_constant_value *)image_param->offset, 2);
1285       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1286          (const gl_constant_value *)image_param->size, 3);
1287       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1288          (const gl_constant_value *)image_param->stride, 4);
1289       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1290          (const gl_constant_value *)image_param->tiling, 3);
1291       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1292          (const gl_constant_value *)image_param->swizzling, 2);
1293       param += BRW_IMAGE_PARAM_SIZE;
1294
1295       brw_mark_surface_used(
1296          stage_prog_data,
1297          stage_prog_data->binding_table.image_start + image_idx);
1298    }
1299 }
1300
1301 /**
1302  * Decide which set of clip planes should be used when clipping via
1303  * gl_Position or gl_ClipVertex.
1304  */
1305 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1306 {
1307    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1308       /* There is currently a GLSL vertex shader, so clip according to GLSL
1309        * rules, which means compare gl_ClipVertex (or gl_Position, if
1310        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1311        * that were stored in EyeUserPlane at the time the clip planes were
1312        * specified.
1313        */
1314       return ctx->Transform.EyeUserPlane;
1315    } else {
1316       /* Either we are using fixed function or an ARB vertex program.  In
1317        * either case the clip planes are going to be compared against
1318        * gl_Position (which is in clip coordinates) so we have to clip using
1319        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1320        * core.
1321        */
1322       return ctx->Transform._ClipUserPlane;
1323    }
1324 }
1325
1326 extern "C" const unsigned *
1327 brw_compile_tes(const struct brw_compiler *compiler,
1328                 void *log_data,
1329                 void *mem_ctx,
1330                 const struct brw_tes_prog_key *key,
1331                 struct brw_tes_prog_data *prog_data,
1332                 const nir_shader *src_shader,
1333                 struct gl_shader_program *shader_prog,
1334                 int shader_time_index,
1335                 unsigned *final_assembly_size,
1336                 char **error_str)
1337 {
1338    const struct brw_device_info *devinfo = compiler->devinfo;
1339    struct gl_shader *shader =
1340       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1341    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1342
1343    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1344    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1345    nir->info.inputs_read = key->inputs_read;
1346    nir->info.patch_inputs_read = key->patch_inputs_read;
1347    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
1348    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1349
1350    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1351                        nir->info.outputs_written,
1352                        nir->info.separate_shader);
1353
1354    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1355
1356    assert(output_size_bytes >= 1);
1357    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1358       if (error_str)
1359          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1360       return NULL;
1361    }
1362
1363    /* URB entry sizes are stored as a multiple of 64 bytes. */
1364    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1365
1366    struct brw_vue_map input_vue_map;
1367    brw_compute_tess_vue_map(&input_vue_map,
1368                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1369                             nir->info.patch_inputs_read);
1370
1371    bool need_patch_header = nir->info.system_values_read &
1372       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1373        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1374
1375    /* The TES will pull most inputs using URB read messages.
1376     *
1377     * However, we push the patch header for TessLevel factors when required,
1378     * as it's a tiny amount of extra data.
1379     */
1380    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1381
1382    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1383       fprintf(stderr, "TES Input ");
1384       brw_print_vue_map(stderr, &input_vue_map);
1385       fprintf(stderr, "TES Output ");
1386       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1387    }
1388
1389    if (is_scalar) {
1390       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1391                    &prog_data->base.base, shader->Program, nir, 8,
1392                    shader_time_index, &input_vue_map);
1393       if (!v.run_tes()) {
1394          if (error_str)
1395             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1396          return NULL;
1397       }
1398
1399       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1400
1401       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1402                      &prog_data->base.base, v.promoted_constants, false,
1403                      "TES");
1404       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1405          g.enable_debug(ralloc_asprintf(mem_ctx,
1406                                         "%s tessellation evaluation shader %s",
1407                                         nir->info.label ? nir->info.label
1408                                                         : "unnamed",
1409                                         nir->info.name));
1410       }
1411
1412       g.generate_code(v.cfg, 8);
1413
1414       return g.get_assembly(final_assembly_size);
1415    } else {
1416       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1417                               nir, mem_ctx, shader_time_index);
1418       if (!v.run()) {
1419          if (error_str)
1420             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1421          return NULL;
1422       }
1423
1424       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1425          v.dump_instructions();
1426
1427       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1428                                         &prog_data->base, v.cfg,
1429                                         final_assembly_size);
1430    }
1431 }