2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
29 #include "brw_vec4_tes.h"
30 #include "main/shaderobj.h"
31 #include "main/uniforms.h"
33 extern "C" struct gl_shader
*
34 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
36 struct brw_shader
*shader
;
38 shader
= rzalloc(NULL
, struct brw_shader
);
40 shader
->base
.Type
= type
;
41 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
42 shader
->base
.Name
= name
;
43 _mesa_init_shader(ctx
, &shader
->base
);
50 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
53 assert(surf_index
< BRW_MAX_SURFACES
);
55 prog_data
->binding_table
.size_bytes
=
56 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
60 brw_type_for_base_type(const struct glsl_type
*type
)
62 switch (type
->base_type
) {
64 return BRW_REGISTER_TYPE_F
;
67 case GLSL_TYPE_SUBROUTINE
:
68 return BRW_REGISTER_TYPE_D
;
70 return BRW_REGISTER_TYPE_UD
;
72 return brw_type_for_base_type(type
->fields
.array
);
73 case GLSL_TYPE_STRUCT
:
74 case GLSL_TYPE_SAMPLER
:
75 case GLSL_TYPE_ATOMIC_UINT
:
76 /* These should be overridden with the type of the member when
77 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
78 * way to trip up if we don't.
80 return BRW_REGISTER_TYPE_UD
;
82 return BRW_REGISTER_TYPE_UD
;
83 case GLSL_TYPE_DOUBLE
:
84 return BRW_REGISTER_TYPE_DF
;
87 case GLSL_TYPE_INTERFACE
:
88 case GLSL_TYPE_FUNCTION
:
89 unreachable("not reached");
92 return BRW_REGISTER_TYPE_F
;
95 enum brw_conditional_mod
96 brw_conditional_for_comparison(unsigned int op
)
100 return BRW_CONDITIONAL_L
;
101 case ir_binop_greater
:
102 return BRW_CONDITIONAL_G
;
103 case ir_binop_lequal
:
104 return BRW_CONDITIONAL_LE
;
105 case ir_binop_gequal
:
106 return BRW_CONDITIONAL_GE
;
108 case ir_binop_all_equal
: /* same as equal for scalars */
109 return BRW_CONDITIONAL_Z
;
110 case ir_binop_nequal
:
111 case ir_binop_any_nequal
: /* same as nequal for scalars */
112 return BRW_CONDITIONAL_NZ
;
114 unreachable("not reached: bad operation for comparison");
119 brw_math_function(enum opcode op
)
122 case SHADER_OPCODE_RCP
:
123 return BRW_MATH_FUNCTION_INV
;
124 case SHADER_OPCODE_RSQ
:
125 return BRW_MATH_FUNCTION_RSQ
;
126 case SHADER_OPCODE_SQRT
:
127 return BRW_MATH_FUNCTION_SQRT
;
128 case SHADER_OPCODE_EXP2
:
129 return BRW_MATH_FUNCTION_EXP
;
130 case SHADER_OPCODE_LOG2
:
131 return BRW_MATH_FUNCTION_LOG
;
132 case SHADER_OPCODE_POW
:
133 return BRW_MATH_FUNCTION_POW
;
134 case SHADER_OPCODE_SIN
:
135 return BRW_MATH_FUNCTION_SIN
;
136 case SHADER_OPCODE_COS
:
137 return BRW_MATH_FUNCTION_COS
;
138 case SHADER_OPCODE_INT_QUOTIENT
:
139 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
140 case SHADER_OPCODE_INT_REMAINDER
:
141 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
143 unreachable("not reached: unknown math function");
148 brw_texture_offset(int *offsets
, unsigned num_components
)
150 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
152 /* Combine all three offsets into a single unsigned dword:
154 * bits 11:8 - U Offset (X component)
155 * bits 7:4 - V Offset (Y component)
156 * bits 3:0 - R Offset (Z component)
158 unsigned offset_bits
= 0;
159 for (unsigned i
= 0; i
< num_components
; i
++) {
160 const unsigned shift
= 4 * (2 - i
);
161 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
167 brw_instruction_name(const struct brw_device_info
*devinfo
, enum opcode op
)
170 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
171 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
172 * start of a loop in the IR.
174 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
177 assert(brw_opcode_desc(devinfo
, op
)->name
);
178 return brw_opcode_desc(devinfo
, op
)->name
;
179 case FS_OPCODE_FB_WRITE
:
181 case FS_OPCODE_FB_WRITE_LOGICAL
:
182 return "fb_write_logical";
183 case FS_OPCODE_PACK_STENCIL_REF
:
184 return "pack_stencil_ref";
185 case FS_OPCODE_REP_FB_WRITE
:
186 return "rep_fb_write";
188 case SHADER_OPCODE_RCP
:
190 case SHADER_OPCODE_RSQ
:
192 case SHADER_OPCODE_SQRT
:
194 case SHADER_OPCODE_EXP2
:
196 case SHADER_OPCODE_LOG2
:
198 case SHADER_OPCODE_POW
:
200 case SHADER_OPCODE_INT_QUOTIENT
:
202 case SHADER_OPCODE_INT_REMAINDER
:
204 case SHADER_OPCODE_SIN
:
206 case SHADER_OPCODE_COS
:
209 case SHADER_OPCODE_TEX
:
211 case SHADER_OPCODE_TEX_LOGICAL
:
212 return "tex_logical";
213 case SHADER_OPCODE_TXD
:
215 case SHADER_OPCODE_TXD_LOGICAL
:
216 return "txd_logical";
217 case SHADER_OPCODE_TXF
:
219 case SHADER_OPCODE_TXF_LOGICAL
:
220 return "txf_logical";
221 case SHADER_OPCODE_TXF_LZ
:
223 case SHADER_OPCODE_TXL
:
225 case SHADER_OPCODE_TXL_LOGICAL
:
226 return "txl_logical";
227 case SHADER_OPCODE_TXL_LZ
:
229 case SHADER_OPCODE_TXS
:
231 case SHADER_OPCODE_TXS_LOGICAL
:
232 return "txs_logical";
235 case FS_OPCODE_TXB_LOGICAL
:
236 return "txb_logical";
237 case SHADER_OPCODE_TXF_CMS
:
239 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
240 return "txf_cms_logical";
241 case SHADER_OPCODE_TXF_CMS_W
:
243 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
244 return "txf_cms_w_logical";
245 case SHADER_OPCODE_TXF_UMS
:
247 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
248 return "txf_ums_logical";
249 case SHADER_OPCODE_TXF_MCS
:
251 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
252 return "txf_mcs_logical";
253 case SHADER_OPCODE_LOD
:
255 case SHADER_OPCODE_LOD_LOGICAL
:
256 return "lod_logical";
257 case SHADER_OPCODE_TG4
:
259 case SHADER_OPCODE_TG4_LOGICAL
:
260 return "tg4_logical";
261 case SHADER_OPCODE_TG4_OFFSET
:
263 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
264 return "tg4_offset_logical";
265 case SHADER_OPCODE_SAMPLEINFO
:
268 case SHADER_OPCODE_SHADER_TIME_ADD
:
269 return "shader_time_add";
271 case SHADER_OPCODE_UNTYPED_ATOMIC
:
272 return "untyped_atomic";
273 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
274 return "untyped_atomic_logical";
275 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
276 return "untyped_surface_read";
277 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
278 return "untyped_surface_read_logical";
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 return "untyped_surface_write";
281 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
282 return "untyped_surface_write_logical";
283 case SHADER_OPCODE_TYPED_ATOMIC
:
284 return "typed_atomic";
285 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
286 return "typed_atomic_logical";
287 case SHADER_OPCODE_TYPED_SURFACE_READ
:
288 return "typed_surface_read";
289 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
290 return "typed_surface_read_logical";
291 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
292 return "typed_surface_write";
293 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
294 return "typed_surface_write_logical";
295 case SHADER_OPCODE_MEMORY_FENCE
:
296 return "memory_fence";
298 case SHADER_OPCODE_LOAD_PAYLOAD
:
299 return "load_payload";
303 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
304 return "gen4_scratch_read";
305 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
306 return "gen4_scratch_write";
307 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
308 return "gen7_scratch_read";
309 case SHADER_OPCODE_URB_WRITE_SIMD8
:
310 return "gen8_urb_write_simd8";
311 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
312 return "gen8_urb_write_simd8_per_slot";
313 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
314 return "gen8_urb_write_simd8_masked";
315 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
316 return "gen8_urb_write_simd8_masked_per_slot";
317 case SHADER_OPCODE_URB_READ_SIMD8
:
318 return "urb_read_simd8";
319 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
320 return "urb_read_simd8_per_slot";
322 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
323 return "find_live_channel";
324 case SHADER_OPCODE_BROADCAST
:
327 case SHADER_OPCODE_EXTRACT_BYTE
:
328 return "extract_byte";
329 case SHADER_OPCODE_EXTRACT_WORD
:
330 return "extract_word";
331 case VEC4_OPCODE_MOV_BYTES
:
333 case VEC4_OPCODE_PACK_BYTES
:
335 case VEC4_OPCODE_UNPACK_UNIFORM
:
336 return "unpack_uniform";
338 case FS_OPCODE_DDX_COARSE
:
340 case FS_OPCODE_DDX_FINE
:
342 case FS_OPCODE_DDY_COARSE
:
344 case FS_OPCODE_DDY_FINE
:
347 case FS_OPCODE_CINTERP
:
349 case FS_OPCODE_LINTERP
:
352 case FS_OPCODE_PIXEL_X
:
354 case FS_OPCODE_PIXEL_Y
:
357 case FS_OPCODE_GET_BUFFER_SIZE
:
358 return "fs_get_buffer_size";
360 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
361 return "uniform_pull_const";
362 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
363 return "uniform_pull_const_gen7";
364 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
365 return "varying_pull_const";
366 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
367 return "varying_pull_const_gen7";
369 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
370 return "mov_dispatch_to_flags";
371 case FS_OPCODE_DISCARD_JUMP
:
372 return "discard_jump";
374 case FS_OPCODE_SET_SAMPLE_ID
:
375 return "set_sample_id";
376 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
377 return "set_simd4x2_offset";
379 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
380 return "pack_half_2x16_split";
381 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
382 return "unpack_half_2x16_split_x";
383 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
384 return "unpack_half_2x16_split_y";
386 case FS_OPCODE_PLACEHOLDER_HALT
:
387 return "placeholder_halt";
389 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
390 return "interp_centroid";
391 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
392 return "interp_sample";
393 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
394 return "interp_shared_offset";
395 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
396 return "interp_per_slot_offset";
398 case VS_OPCODE_URB_WRITE
:
399 return "vs_urb_write";
400 case VS_OPCODE_PULL_CONSTANT_LOAD
:
401 return "pull_constant_load";
402 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
403 return "pull_constant_load_gen7";
405 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
406 return "set_simd4x2_header_gen9";
408 case VS_OPCODE_GET_BUFFER_SIZE
:
409 return "vs_get_buffer_size";
411 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
412 return "unpack_flags_simd4x2";
414 case GS_OPCODE_URB_WRITE
:
415 return "gs_urb_write";
416 case GS_OPCODE_URB_WRITE_ALLOCATE
:
417 return "gs_urb_write_allocate";
418 case GS_OPCODE_THREAD_END
:
419 return "gs_thread_end";
420 case GS_OPCODE_SET_WRITE_OFFSET
:
421 return "set_write_offset";
422 case GS_OPCODE_SET_VERTEX_COUNT
:
423 return "set_vertex_count";
424 case GS_OPCODE_SET_DWORD_2
:
425 return "set_dword_2";
426 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
427 return "prepare_channel_masks";
428 case GS_OPCODE_SET_CHANNEL_MASKS
:
429 return "set_channel_masks";
430 case GS_OPCODE_GET_INSTANCE_ID
:
431 return "get_instance_id";
432 case GS_OPCODE_FF_SYNC
:
434 case GS_OPCODE_SET_PRIMITIVE_ID
:
435 return "set_primitive_id";
436 case GS_OPCODE_SVB_WRITE
:
437 return "gs_svb_write";
438 case GS_OPCODE_SVB_SET_DST_INDEX
:
439 return "gs_svb_set_dst_index";
440 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
441 return "gs_ff_sync_set_primitives";
442 case CS_OPCODE_CS_TERMINATE
:
443 return "cs_terminate";
444 case SHADER_OPCODE_BARRIER
:
446 case SHADER_OPCODE_MULH
:
448 case SHADER_OPCODE_MOV_INDIRECT
:
449 return "mov_indirect";
451 case VEC4_OPCODE_URB_READ
:
453 case TCS_OPCODE_GET_INSTANCE_ID
:
454 return "tcs_get_instance_id";
455 case TCS_OPCODE_URB_WRITE
:
456 return "tcs_urb_write";
457 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
458 return "tcs_set_input_urb_offsets";
459 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
460 return "tcs_set_output_urb_offsets";
461 case TCS_OPCODE_GET_PRIMITIVE_ID
:
462 return "tcs_get_primitive_id";
463 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
464 return "tcs_create_barrier_header";
465 case TCS_OPCODE_SRC0_010_IS_ZERO
:
466 return "tcs_src0<0,1,0>_is_zero";
467 case TCS_OPCODE_RELEASE_INPUT
:
468 return "tcs_release_input";
469 case TCS_OPCODE_THREAD_END
:
470 return "tcs_thread_end";
471 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
472 return "tes_create_input_read_header";
473 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
474 return "tes_add_indirect_urb_offset";
475 case TES_OPCODE_GET_PRIMITIVE_ID
:
476 return "tes_get_primitive_id";
479 unreachable("not reached");
483 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
490 } imm
, sat_imm
= { 0 };
492 const unsigned size
= type_sz(type
);
494 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
495 * irrelevant, so just check the size of the type and copy from/to an
496 * appropriately sized field.
504 case BRW_REGISTER_TYPE_UD
:
505 case BRW_REGISTER_TYPE_D
:
506 case BRW_REGISTER_TYPE_UW
:
507 case BRW_REGISTER_TYPE_W
:
508 case BRW_REGISTER_TYPE_UQ
:
509 case BRW_REGISTER_TYPE_Q
:
512 case BRW_REGISTER_TYPE_F
:
513 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
515 case BRW_REGISTER_TYPE_DF
:
516 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
518 case BRW_REGISTER_TYPE_UB
:
519 case BRW_REGISTER_TYPE_B
:
520 unreachable("no UB/B immediates");
521 case BRW_REGISTER_TYPE_V
:
522 case BRW_REGISTER_TYPE_UV
:
523 case BRW_REGISTER_TYPE_VF
:
524 unreachable("unimplemented: saturate vector immediate");
525 case BRW_REGISTER_TYPE_HF
:
526 unreachable("unimplemented: saturate HF immediate");
530 if (imm
.ud
!= sat_imm
.ud
) {
531 reg
->ud
= sat_imm
.ud
;
535 if (imm
.df
!= sat_imm
.df
) {
536 reg
->df
= sat_imm
.df
;
544 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
547 case BRW_REGISTER_TYPE_D
:
548 case BRW_REGISTER_TYPE_UD
:
551 case BRW_REGISTER_TYPE_W
:
552 case BRW_REGISTER_TYPE_UW
:
553 reg
->d
= -(int16_t)reg
->ud
;
555 case BRW_REGISTER_TYPE_F
:
558 case BRW_REGISTER_TYPE_VF
:
559 reg
->ud
^= 0x80808080;
561 case BRW_REGISTER_TYPE_DF
:
564 case BRW_REGISTER_TYPE_UB
:
565 case BRW_REGISTER_TYPE_B
:
566 unreachable("no UB/B immediates");
567 case BRW_REGISTER_TYPE_UV
:
568 case BRW_REGISTER_TYPE_V
:
569 assert(!"unimplemented: negate UV/V immediate");
570 case BRW_REGISTER_TYPE_UQ
:
571 case BRW_REGISTER_TYPE_Q
:
572 assert(!"unimplemented: negate UQ/Q immediate");
573 case BRW_REGISTER_TYPE_HF
:
574 assert(!"unimplemented: negate HF immediate");
581 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
584 case BRW_REGISTER_TYPE_D
:
585 reg
->d
= abs(reg
->d
);
587 case BRW_REGISTER_TYPE_W
:
588 reg
->d
= abs((int16_t)reg
->ud
);
590 case BRW_REGISTER_TYPE_F
:
591 reg
->f
= fabsf(reg
->f
);
593 case BRW_REGISTER_TYPE_DF
:
594 reg
->df
= fabs(reg
->df
);
596 case BRW_REGISTER_TYPE_VF
:
597 reg
->ud
&= ~0x80808080;
599 case BRW_REGISTER_TYPE_UB
:
600 case BRW_REGISTER_TYPE_B
:
601 unreachable("no UB/B immediates");
602 case BRW_REGISTER_TYPE_UQ
:
603 case BRW_REGISTER_TYPE_UD
:
604 case BRW_REGISTER_TYPE_UW
:
605 case BRW_REGISTER_TYPE_UV
:
606 /* Presumably the absolute value modifier on an unsigned source is a
607 * nop, but it would be nice to confirm.
609 assert(!"unimplemented: abs unsigned immediate");
610 case BRW_REGISTER_TYPE_V
:
611 assert(!"unimplemented: abs V immediate");
612 case BRW_REGISTER_TYPE_Q
:
613 assert(!"unimplemented: abs Q immediate");
614 case BRW_REGISTER_TYPE_HF
:
615 assert(!"unimplemented: abs HF immediate");
622 tesslevel_outer_components(GLenum tes_primitive_mode
)
624 switch (tes_primitive_mode
) {
632 unreachable("Bogus tessellation domain");
638 tesslevel_inner_components(GLenum tes_primitive_mode
)
640 switch (tes_primitive_mode
) {
648 unreachable("Bogus tessellation domain");
654 * Given a normal .xyzw writemask, convert it to a writemask for a vector
655 * that's stored backwards, i.e. .wzyx.
658 writemask_for_backwards_vector(unsigned mask
)
660 unsigned new_mask
= 0;
662 for (int i
= 0; i
< 4; i
++)
663 new_mask
|= ((mask
>> i
) & 1) << (3 - i
);
668 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
671 const nir_shader
*shader
,
672 struct brw_stage_prog_data
*stage_prog_data
)
673 : compiler(compiler
),
675 devinfo(compiler
->devinfo
),
677 stage_prog_data(stage_prog_data
),
682 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
683 stage_name
= _mesa_shader_stage_to_string(stage
);
684 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
685 is_passthrough_shader
=
686 nir
->info
.name
&& strcmp(nir
->info
.name
, "passthrough") == 0;
690 backend_reg::equals(const backend_reg
&r
) const
692 return brw_regs_equal(this, &r
) && reg_offset
== r
.reg_offset
;
696 backend_reg::is_zero() const
702 case BRW_REGISTER_TYPE_F
:
704 case BRW_REGISTER_TYPE_DF
:
706 case BRW_REGISTER_TYPE_D
:
707 case BRW_REGISTER_TYPE_UD
:
715 backend_reg::is_one() const
721 case BRW_REGISTER_TYPE_F
:
723 case BRW_REGISTER_TYPE_DF
:
725 case BRW_REGISTER_TYPE_D
:
726 case BRW_REGISTER_TYPE_UD
:
734 backend_reg::is_negative_one() const
740 case BRW_REGISTER_TYPE_F
:
742 case BRW_REGISTER_TYPE_DF
:
744 case BRW_REGISTER_TYPE_D
:
752 backend_reg::is_null() const
754 return file
== ARF
&& nr
== BRW_ARF_NULL
;
759 backend_reg::is_accumulator() const
761 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
765 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
767 return (file
== r
.file
&&
769 reg_offset
>= r
.reg_offset
&&
770 reg_offset
< r
.reg_offset
+ n
);
774 backend_instruction::is_commutative() const
782 case SHADER_OPCODE_MULH
:
785 /* MIN and MAX are commutative. */
786 if (conditional_mod
== BRW_CONDITIONAL_GE
||
787 conditional_mod
== BRW_CONDITIONAL_L
) {
797 backend_instruction::is_3src(const struct brw_device_info
*devinfo
) const
799 return ::is_3src(devinfo
, opcode
);
803 backend_instruction::is_tex() const
805 return (opcode
== SHADER_OPCODE_TEX
||
806 opcode
== FS_OPCODE_TXB
||
807 opcode
== SHADER_OPCODE_TXD
||
808 opcode
== SHADER_OPCODE_TXF
||
809 opcode
== SHADER_OPCODE_TXF_LZ
||
810 opcode
== SHADER_OPCODE_TXF_CMS
||
811 opcode
== SHADER_OPCODE_TXF_CMS_W
||
812 opcode
== SHADER_OPCODE_TXF_UMS
||
813 opcode
== SHADER_OPCODE_TXF_MCS
||
814 opcode
== SHADER_OPCODE_TXL
||
815 opcode
== SHADER_OPCODE_TXL_LZ
||
816 opcode
== SHADER_OPCODE_TXS
||
817 opcode
== SHADER_OPCODE_LOD
||
818 opcode
== SHADER_OPCODE_TG4
||
819 opcode
== SHADER_OPCODE_TG4_OFFSET
||
820 opcode
== SHADER_OPCODE_SAMPLEINFO
);
824 backend_instruction::is_math() const
826 return (opcode
== SHADER_OPCODE_RCP
||
827 opcode
== SHADER_OPCODE_RSQ
||
828 opcode
== SHADER_OPCODE_SQRT
||
829 opcode
== SHADER_OPCODE_EXP2
||
830 opcode
== SHADER_OPCODE_LOG2
||
831 opcode
== SHADER_OPCODE_SIN
||
832 opcode
== SHADER_OPCODE_COS
||
833 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
834 opcode
== SHADER_OPCODE_INT_REMAINDER
||
835 opcode
== SHADER_OPCODE_POW
);
839 backend_instruction::is_control_flow() const
843 case BRW_OPCODE_WHILE
:
845 case BRW_OPCODE_ELSE
:
846 case BRW_OPCODE_ENDIF
:
847 case BRW_OPCODE_BREAK
:
848 case BRW_OPCODE_CONTINUE
:
856 backend_instruction::can_do_source_mods() const
859 case BRW_OPCODE_ADDC
:
861 case BRW_OPCODE_BFI1
:
862 case BRW_OPCODE_BFI2
:
863 case BRW_OPCODE_BFREV
:
864 case BRW_OPCODE_CBIT
:
867 case BRW_OPCODE_SUBB
:
875 backend_instruction::can_do_saturate() const
885 case BRW_OPCODE_F16TO32
:
886 case BRW_OPCODE_F32TO16
:
887 case BRW_OPCODE_LINE
:
891 case BRW_OPCODE_MATH
:
894 case SHADER_OPCODE_MULH
:
896 case BRW_OPCODE_RNDD
:
897 case BRW_OPCODE_RNDE
:
898 case BRW_OPCODE_RNDU
:
899 case BRW_OPCODE_RNDZ
:
903 case FS_OPCODE_LINTERP
:
904 case SHADER_OPCODE_COS
:
905 case SHADER_OPCODE_EXP2
:
906 case SHADER_OPCODE_LOG2
:
907 case SHADER_OPCODE_POW
:
908 case SHADER_OPCODE_RCP
:
909 case SHADER_OPCODE_RSQ
:
910 case SHADER_OPCODE_SIN
:
911 case SHADER_OPCODE_SQRT
:
919 backend_instruction::can_do_cmod() const
923 case BRW_OPCODE_ADDC
:
928 case BRW_OPCODE_CMPN
:
933 case BRW_OPCODE_F16TO32
:
934 case BRW_OPCODE_F32TO16
:
936 case BRW_OPCODE_LINE
:
940 case BRW_OPCODE_MACH
:
947 case BRW_OPCODE_RNDD
:
948 case BRW_OPCODE_RNDE
:
949 case BRW_OPCODE_RNDU
:
950 case BRW_OPCODE_RNDZ
:
951 case BRW_OPCODE_SAD2
:
952 case BRW_OPCODE_SADA2
:
955 case BRW_OPCODE_SUBB
:
957 case FS_OPCODE_CINTERP
:
958 case FS_OPCODE_LINTERP
:
966 backend_instruction::reads_accumulator_implicitly() const
970 case BRW_OPCODE_MACH
:
971 case BRW_OPCODE_SADA2
:
979 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
981 return writes_accumulator
||
983 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
984 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
985 opcode
!= FS_OPCODE_CINTERP
)));
989 backend_instruction::has_side_effects() const
992 case SHADER_OPCODE_UNTYPED_ATOMIC
:
993 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
994 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
995 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
996 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
997 case SHADER_OPCODE_TYPED_ATOMIC
:
998 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
999 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1000 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1001 case SHADER_OPCODE_MEMORY_FENCE
:
1002 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1003 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1004 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1005 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1006 case FS_OPCODE_FB_WRITE
:
1007 case SHADER_OPCODE_BARRIER
:
1008 case TCS_OPCODE_URB_WRITE
:
1009 case TCS_OPCODE_RELEASE_INPUT
:
1017 backend_instruction::is_volatile() const
1020 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1021 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1022 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1023 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1024 case SHADER_OPCODE_URB_READ_SIMD8
:
1025 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1026 case VEC4_OPCODE_URB_READ
:
1035 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1038 foreach_inst_in_block (backend_instruction
, i
, block
) {
1048 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1050 for (bblock_t
*block_iter
= start_block
->next();
1052 block_iter
= block_iter
->next()) {
1053 block_iter
->start_ip
+= ip_adjustment
;
1054 block_iter
->end_ip
+= ip_adjustment
;
1059 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1061 assert(this != inst
);
1063 if (!this->is_head_sentinel())
1064 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1068 adjust_later_block_ips(block
, 1);
1070 exec_node::insert_after(inst
);
1074 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1076 assert(this != inst
);
1078 if (!this->is_tail_sentinel())
1079 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1083 adjust_later_block_ips(block
, 1);
1085 exec_node::insert_before(inst
);
1089 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1091 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1093 unsigned num_inst
= list
->length();
1095 block
->end_ip
+= num_inst
;
1097 adjust_later_block_ips(block
, num_inst
);
1099 exec_node::insert_before(list
);
1103 backend_instruction::remove(bblock_t
*block
)
1105 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1107 adjust_later_block_ips(block
, -1);
1109 if (block
->start_ip
== block
->end_ip
) {
1110 block
->cfg
->remove_block(block
);
1115 exec_node::remove();
1119 backend_shader::dump_instructions()
1121 dump_instructions(NULL
);
1125 backend_shader::dump_instructions(const char *name
)
1127 FILE *file
= stderr
;
1128 if (name
&& geteuid() != 0) {
1129 file
= fopen(name
, "w");
1136 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1137 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1138 fprintf(file
, "%4d: ", ip
++);
1139 dump_instruction(inst
, file
);
1143 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1144 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1145 fprintf(file
, "%4d: ", ip
++);
1146 dump_instruction(inst
, file
);
1150 if (file
!= stderr
) {
1156 backend_shader::calculate_cfg()
1160 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1164 * Sets up the starting offsets for the groups of binding table entries
1165 * commong to all pipeline stages.
1167 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1168 * unused but also make sure that addition of small offsets to them will
1169 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1172 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1173 const struct brw_device_info
*devinfo
,
1174 const struct gl_shader_program
*shader_prog
,
1175 const struct gl_program
*prog
,
1176 struct brw_stage_prog_data
*stage_prog_data
,
1177 uint32_t next_binding_table_offset
)
1179 const struct gl_shader
*shader
= NULL
;
1180 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1183 shader
= shader_prog
->_LinkedShaders
[stage
];
1185 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1186 next_binding_table_offset
+= num_textures
;
1189 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1190 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1191 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1193 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1194 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1195 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1197 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1198 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1201 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1202 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1203 next_binding_table_offset
++;
1205 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1208 if (prog
->UsesGather
) {
1209 if (devinfo
->gen
>= 8) {
1210 stage_prog_data
->binding_table
.gather_texture_start
=
1211 stage_prog_data
->binding_table
.texture_start
;
1213 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1214 next_binding_table_offset
+= num_textures
;
1217 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1220 if (shader
&& shader
->NumAtomicBuffers
) {
1221 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1222 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1224 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1227 if (shader
&& shader
->NumImages
) {
1228 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1229 next_binding_table_offset
+= shader
->NumImages
;
1231 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1234 /* This may or may not be used depending on how the compile goes. */
1235 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1236 next_binding_table_offset
++;
1238 /* Plane 0 is just the regular texture section */
1239 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
1241 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
1242 next_binding_table_offset
+= num_textures
;
1244 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
1245 next_binding_table_offset
+= num_textures
;
1247 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1249 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1253 setup_vec4_uniform_value(const gl_constant_value
**params
,
1254 const gl_constant_value
*values
,
1257 static const gl_constant_value zero
= { 0 };
1259 for (unsigned i
= 0; i
< n
; ++i
)
1260 params
[i
] = &values
[i
];
1262 for (unsigned i
= n
; i
< 4; ++i
)
1267 brw_setup_image_uniform_values(gl_shader_stage stage
,
1268 struct brw_stage_prog_data
*stage_prog_data
,
1269 unsigned param_start_index
,
1270 const gl_uniform_storage
*storage
)
1272 const gl_constant_value
**param
=
1273 &stage_prog_data
->param
[param_start_index
];
1275 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1276 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1277 const brw_image_param
*image_param
=
1278 &stage_prog_data
->image_param
[image_idx
];
1280 /* Upload the brw_image_param structure. The order is expected to match
1281 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1283 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1284 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1285 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1286 (const gl_constant_value
*)image_param
->offset
, 2);
1287 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1288 (const gl_constant_value
*)image_param
->size
, 3);
1289 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1290 (const gl_constant_value
*)image_param
->stride
, 4);
1291 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1292 (const gl_constant_value
*)image_param
->tiling
, 3);
1293 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1294 (const gl_constant_value
*)image_param
->swizzling
, 2);
1295 param
+= BRW_IMAGE_PARAM_SIZE
;
1297 brw_mark_surface_used(
1299 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1304 * Decide which set of clip planes should be used when clipping via
1305 * gl_Position or gl_ClipVertex.
1307 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1309 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1310 /* There is currently a GLSL vertex shader, so clip according to GLSL
1311 * rules, which means compare gl_ClipVertex (or gl_Position, if
1312 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1313 * that were stored in EyeUserPlane at the time the clip planes were
1316 return ctx
->Transform
.EyeUserPlane
;
1318 /* Either we are using fixed function or an ARB vertex program. In
1319 * either case the clip planes are going to be compared against
1320 * gl_Position (which is in clip coordinates) so we have to clip using
1321 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1324 return ctx
->Transform
._ClipUserPlane
;
1328 extern "C" const unsigned *
1329 brw_compile_tes(const struct brw_compiler
*compiler
,
1332 const struct brw_tes_prog_key
*key
,
1333 struct brw_tes_prog_data
*prog_data
,
1334 const nir_shader
*src_shader
,
1335 struct gl_shader_program
*shader_prog
,
1336 int shader_time_index
,
1337 unsigned *final_assembly_size
,
1340 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
1341 struct gl_shader
*shader
=
1342 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
];
1343 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1345 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1346 nir
->info
.inputs_read
= key
->inputs_read
;
1347 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1349 struct brw_vue_map input_vue_map
;
1350 brw_compute_tess_vue_map(&input_vue_map
,
1351 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
1352 nir
->info
.patch_inputs_read
);
1354 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
1355 brw_nir_lower_tes_inputs(nir
, &input_vue_map
);
1356 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1357 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
1359 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1360 nir
->info
.outputs_written
,
1361 nir
->info
.separate_shader
);
1363 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1365 assert(output_size_bytes
>= 1);
1366 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1368 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1372 /* URB entry sizes are stored as a multiple of 64 bytes. */
1373 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1375 bool need_patch_header
= nir
->info
.system_values_read
&
1376 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER
) |
1377 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER
));
1379 /* The TES will pull most inputs using URB read messages.
1381 * However, we push the patch header for TessLevel factors when required,
1382 * as it's a tiny amount of extra data.
1384 prog_data
->base
.urb_read_length
= need_patch_header
? 1 : 0;
1386 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1387 fprintf(stderr
, "TES Input ");
1388 brw_print_vue_map(stderr
, &input_vue_map
);
1389 fprintf(stderr
, "TES Output ");
1390 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1394 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1395 &prog_data
->base
.base
, shader
->Program
, nir
, 8,
1396 shader_time_index
, &input_vue_map
);
1399 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1403 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1404 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1406 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1407 &prog_data
->base
.base
, v
.promoted_constants
, false,
1408 MESA_SHADER_TESS_EVAL
);
1409 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1410 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1411 "%s tessellation evaluation shader %s",
1412 nir
->info
.label
? nir
->info
.label
1417 g
.generate_code(v
.cfg
, 8);
1419 return g
.get_assembly(final_assembly_size
);
1421 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1422 nir
, mem_ctx
, shader_time_index
);
1425 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1429 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1430 v
.dump_instructions();
1432 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1433 &prog_data
->base
, v
.cfg
,
1434 final_assembly_size
);