src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/uniforms.h"
  31
  32 extern "C" void
  33 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  34                       unsigned surf_index)
  35 {
  36    assert(surf_index < BRW_MAX_SURFACES);
  37
  38    prog_data->binding_table.size_bytes =
  39       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  40 }
  41
  42 enum brw_reg_type
  43 brw_type_for_base_type(const struct glsl_type *type)
  44 {
  45    switch (type->base_type) {
  46    case GLSL_TYPE_FLOAT:
  47       return BRW_REGISTER_TYPE_F;
  48    case GLSL_TYPE_INT:
  49    case GLSL_TYPE_BOOL:
  50    case GLSL_TYPE_SUBROUTINE:
  51       return BRW_REGISTER_TYPE_D;
  52    case GLSL_TYPE_UINT:
  53       return BRW_REGISTER_TYPE_UD;
  54    case GLSL_TYPE_ARRAY:
  55       return brw_type_for_base_type(type->fields.array);
  56    case GLSL_TYPE_STRUCT:
  57    case GLSL_TYPE_SAMPLER:
  58    case GLSL_TYPE_ATOMIC_UINT:
  59       /* These should be overridden with the type of the member when
  60        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  61        * way to trip up if we don't.
  62        */
  63       return BRW_REGISTER_TYPE_UD;
  64    case GLSL_TYPE_IMAGE:
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_DOUBLE:
  67       return BRW_REGISTER_TYPE_DF;
  68    case GLSL_TYPE_VOID:
  69    case GLSL_TYPE_ERROR:
  70    case GLSL_TYPE_INTERFACE:
  71    case GLSL_TYPE_FUNCTION:
  72       unreachable("not reached");
  73    }
  74
  75    return BRW_REGISTER_TYPE_F;
  76 }
  77
  78 enum brw_conditional_mod
  79 brw_conditional_for_comparison(unsigned int op)
  80 {
  81    switch (op) {
  82    case ir_binop_less:
  83       return BRW_CONDITIONAL_L;
  84    case ir_binop_greater:
  85       return BRW_CONDITIONAL_G;
  86    case ir_binop_lequal:
  87       return BRW_CONDITIONAL_LE;
  88    case ir_binop_gequal:
  89       return BRW_CONDITIONAL_GE;
  90    case ir_binop_equal:
  91    case ir_binop_all_equal: /* same as equal for scalars */
  92       return BRW_CONDITIONAL_Z;
  93    case ir_binop_nequal:
  94    case ir_binop_any_nequal: /* same as nequal for scalars */
  95       return BRW_CONDITIONAL_NZ;
  96    default:
  97       unreachable("not reached: bad operation for comparison");
  98    }
  99 }
 100
 101 uint32_t
 102 brw_math_function(enum opcode op)
 103 {
 104    switch (op) {
 105    case SHADER_OPCODE_RCP:
 106       return BRW_MATH_FUNCTION_INV;
 107    case SHADER_OPCODE_RSQ:
 108       return BRW_MATH_FUNCTION_RSQ;
 109    case SHADER_OPCODE_SQRT:
 110       return BRW_MATH_FUNCTION_SQRT;
 111    case SHADER_OPCODE_EXP2:
 112       return BRW_MATH_FUNCTION_EXP;
 113    case SHADER_OPCODE_LOG2:
 114       return BRW_MATH_FUNCTION_LOG;
 115    case SHADER_OPCODE_POW:
 116       return BRW_MATH_FUNCTION_POW;
 117    case SHADER_OPCODE_SIN:
 118       return BRW_MATH_FUNCTION_SIN;
 119    case SHADER_OPCODE_COS:
 120       return BRW_MATH_FUNCTION_COS;
 121    case SHADER_OPCODE_INT_QUOTIENT:
 122       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 123    case SHADER_OPCODE_INT_REMAINDER:
 124       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 125    default:
 126       unreachable("not reached: unknown math function");
 127    }
 128 }
 129
 130 uint32_t
 131 brw_texture_offset(int *offsets, unsigned num_components)
 132 {
 133    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 134
 135    /* Combine all three offsets into a single unsigned dword:
 136     *
 137     *    bits 11:8 - U Offset (X component)
 138     *    bits  7:4 - V Offset (Y component)
 139     *    bits  3:0 - R Offset (Z component)
 140     */
 141    unsigned offset_bits = 0;
 142    for (unsigned i = 0; i < num_components; i++) {
 143       const unsigned shift = 4 * (2 - i);
 144       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 145    }
 146    return offset_bits;
 147 }
 148
 149 const char *
 150 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
 151 {
 152    switch (op) {
 153    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 154       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 155        * start of a loop in the IR.
 156        */
 157       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 158          return "do";
 159
 160       assert(brw_opcode_desc(devinfo, op)->name);
 161       return brw_opcode_desc(devinfo, op)->name;
 162    case FS_OPCODE_FB_WRITE:
 163       return "fb_write";
 164    case FS_OPCODE_FB_WRITE_LOGICAL:
 165       return "fb_write_logical";
 166    case FS_OPCODE_REP_FB_WRITE:
 167       return "rep_fb_write";
 168
 169    case SHADER_OPCODE_RCP:
 170       return "rcp";
 171    case SHADER_OPCODE_RSQ:
 172       return "rsq";
 173    case SHADER_OPCODE_SQRT:
 174       return "sqrt";
 175    case SHADER_OPCODE_EXP2:
 176       return "exp2";
 177    case SHADER_OPCODE_LOG2:
 178       return "log2";
 179    case SHADER_OPCODE_POW:
 180       return "pow";
 181    case SHADER_OPCODE_INT_QUOTIENT:
 182       return "int_quot";
 183    case SHADER_OPCODE_INT_REMAINDER:
 184       return "int_rem";
 185    case SHADER_OPCODE_SIN:
 186       return "sin";
 187    case SHADER_OPCODE_COS:
 188       return "cos";
 189
 190    case SHADER_OPCODE_TEX:
 191       return "tex";
 192    case SHADER_OPCODE_TEX_LOGICAL:
 193       return "tex_logical";
 194    case SHADER_OPCODE_TXD:
 195       return "txd";
 196    case SHADER_OPCODE_TXD_LOGICAL:
 197       return "txd_logical";
 198    case SHADER_OPCODE_TXF:
 199       return "txf";
 200    case SHADER_OPCODE_TXF_LOGICAL:
 201       return "txf_logical";
 202    case SHADER_OPCODE_TXF_LZ:
 203       return "txf_lz";
 204    case SHADER_OPCODE_TXL:
 205       return "txl";
 206    case SHADER_OPCODE_TXL_LOGICAL:
 207       return "txl_logical";
 208    case SHADER_OPCODE_TXL_LZ:
 209       return "txl_lz";
 210    case SHADER_OPCODE_TXS:
 211       return "txs";
 212    case SHADER_OPCODE_TXS_LOGICAL:
 213       return "txs_logical";
 214    case FS_OPCODE_TXB:
 215       return "txb";
 216    case FS_OPCODE_TXB_LOGICAL:
 217       return "txb_logical";
 218    case SHADER_OPCODE_TXF_CMS:
 219       return "txf_cms";
 220    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 221       return "txf_cms_logical";
 222    case SHADER_OPCODE_TXF_CMS_W:
 223       return "txf_cms_w";
 224    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 225       return "txf_cms_w_logical";
 226    case SHADER_OPCODE_TXF_UMS:
 227       return "txf_ums";
 228    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 229       return "txf_ums_logical";
 230    case SHADER_OPCODE_TXF_MCS:
 231       return "txf_mcs";
 232    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 233       return "txf_mcs_logical";
 234    case SHADER_OPCODE_LOD:
 235       return "lod";
 236    case SHADER_OPCODE_LOD_LOGICAL:
 237       return "lod_logical";
 238    case SHADER_OPCODE_TG4:
 239       return "tg4";
 240    case SHADER_OPCODE_TG4_LOGICAL:
 241       return "tg4_logical";
 242    case SHADER_OPCODE_TG4_OFFSET:
 243       return "tg4_offset";
 244    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 245       return "tg4_offset_logical";
 246    case SHADER_OPCODE_SAMPLEINFO:
 247       return "sampleinfo";
 248    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 249       return "sampleinfo_logical";
 250
 251    case SHADER_OPCODE_SHADER_TIME_ADD:
 252       return "shader_time_add";
 253
 254    case SHADER_OPCODE_UNTYPED_ATOMIC:
 255       return "untyped_atomic";
 256    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 257       return "untyped_atomic_logical";
 258    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 259       return "untyped_surface_read";
 260    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 261       return "untyped_surface_read_logical";
 262    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 263       return "untyped_surface_write";
 264    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 265       return "untyped_surface_write_logical";
 266    case SHADER_OPCODE_TYPED_ATOMIC:
 267       return "typed_atomic";
 268    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 269       return "typed_atomic_logical";
 270    case SHADER_OPCODE_TYPED_SURFACE_READ:
 271       return "typed_surface_read";
 272    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 273       return "typed_surface_read_logical";
 274    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 275       return "typed_surface_write";
 276    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 277       return "typed_surface_write_logical";
 278    case SHADER_OPCODE_MEMORY_FENCE:
 279       return "memory_fence";
 280
 281    case SHADER_OPCODE_LOAD_PAYLOAD:
 282       return "load_payload";
 283    case FS_OPCODE_PACK:
 284       return "pack";
 285
 286    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 287       return "gen4_scratch_read";
 288    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 289       return "gen4_scratch_write";
 290    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 291       return "gen7_scratch_read";
 292    case SHADER_OPCODE_URB_WRITE_SIMD8:
 293       return "gen8_urb_write_simd8";
 294    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 295       return "gen8_urb_write_simd8_per_slot";
 296    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 297       return "gen8_urb_write_simd8_masked";
 298    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 299       return "gen8_urb_write_simd8_masked_per_slot";
 300    case SHADER_OPCODE_URB_READ_SIMD8:
 301       return "urb_read_simd8";
 302    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 303       return "urb_read_simd8_per_slot";
 304
 305    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 306       return "find_live_channel";
 307    case SHADER_OPCODE_BROADCAST:
 308       return "broadcast";
 309
 310    case VEC4_OPCODE_MOV_BYTES:
 311       return "mov_bytes";
 312    case VEC4_OPCODE_PACK_BYTES:
 313       return "pack_bytes";
 314    case VEC4_OPCODE_UNPACK_UNIFORM:
 315       return "unpack_uniform";
 316
 317    case FS_OPCODE_DDX_COARSE:
 318       return "ddx_coarse";
 319    case FS_OPCODE_DDX_FINE:
 320       return "ddx_fine";
 321    case FS_OPCODE_DDY_COARSE:
 322       return "ddy_coarse";
 323    case FS_OPCODE_DDY_FINE:
 324       return "ddy_fine";
 325
 326    case FS_OPCODE_CINTERP:
 327       return "cinterp";
 328    case FS_OPCODE_LINTERP:
 329       return "linterp";
 330
 331    case FS_OPCODE_PIXEL_X:
 332       return "pixel_x";
 333    case FS_OPCODE_PIXEL_Y:
 334       return "pixel_y";
 335
 336    case FS_OPCODE_GET_BUFFER_SIZE:
 337       return "fs_get_buffer_size";
 338
 339    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 340       return "uniform_pull_const";
 341    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 342       return "uniform_pull_const_gen7";
 343    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 344       return "varying_pull_const_gen4";
 345    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 346       return "varying_pull_const_gen7";
 347    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 348       return "varying_pull_const_logical";
 349
 350    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 351       return "mov_dispatch_to_flags";
 352    case FS_OPCODE_DISCARD_JUMP:
 353       return "discard_jump";
 354
 355    case FS_OPCODE_SET_SAMPLE_ID:
 356       return "set_sample_id";
 357    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 358       return "set_simd4x2_offset";
 359
 360    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 361       return "pack_half_2x16_split";
 362    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 363       return "unpack_half_2x16_split_x";
 364    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 365       return "unpack_half_2x16_split_y";
 366
 367    case FS_OPCODE_PLACEHOLDER_HALT:
 368       return "placeholder_halt";
 369
 370    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 371       return "interp_sample";
 372    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 373       return "interp_shared_offset";
 374    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 375       return "interp_per_slot_offset";
 376
 377    case VS_OPCODE_URB_WRITE:
 378       return "vs_urb_write";
 379    case VS_OPCODE_PULL_CONSTANT_LOAD:
 380       return "pull_constant_load";
 381    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 382       return "pull_constant_load_gen7";
 383
 384    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 385       return "set_simd4x2_header_gen9";
 386
 387    case VS_OPCODE_GET_BUFFER_SIZE:
 388       return "vs_get_buffer_size";
 389
 390    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 391       return "unpack_flags_simd4x2";
 392
 393    case GS_OPCODE_URB_WRITE:
 394       return "gs_urb_write";
 395    case GS_OPCODE_URB_WRITE_ALLOCATE:
 396       return "gs_urb_write_allocate";
 397    case GS_OPCODE_THREAD_END:
 398       return "gs_thread_end";
 399    case GS_OPCODE_SET_WRITE_OFFSET:
 400       return "set_write_offset";
 401    case GS_OPCODE_SET_VERTEX_COUNT:
 402       return "set_vertex_count";
 403    case GS_OPCODE_SET_DWORD_2:
 404       return "set_dword_2";
 405    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 406       return "prepare_channel_masks";
 407    case GS_OPCODE_SET_CHANNEL_MASKS:
 408       return "set_channel_masks";
 409    case GS_OPCODE_GET_INSTANCE_ID:
 410       return "get_instance_id";
 411    case GS_OPCODE_FF_SYNC:
 412       return "ff_sync";
 413    case GS_OPCODE_SET_PRIMITIVE_ID:
 414       return "set_primitive_id";
 415    case GS_OPCODE_SVB_WRITE:
 416       return "gs_svb_write";
 417    case GS_OPCODE_SVB_SET_DST_INDEX:
 418       return "gs_svb_set_dst_index";
 419    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 420       return "gs_ff_sync_set_primitives";
 421    case CS_OPCODE_CS_TERMINATE:
 422       return "cs_terminate";
 423    case SHADER_OPCODE_BARRIER:
 424       return "barrier";
 425    case SHADER_OPCODE_MULH:
 426       return "mulh";
 427    case SHADER_OPCODE_MOV_INDIRECT:
 428       return "mov_indirect";
 429
 430    case VEC4_OPCODE_URB_READ:
 431       return "urb_read";
 432    case TCS_OPCODE_GET_INSTANCE_ID:
 433       return "tcs_get_instance_id";
 434    case TCS_OPCODE_URB_WRITE:
 435       return "tcs_urb_write";
 436    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 437       return "tcs_set_input_urb_offsets";
 438    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 439       return "tcs_set_output_urb_offsets";
 440    case TCS_OPCODE_GET_PRIMITIVE_ID:
 441       return "tcs_get_primitive_id";
 442    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 443       return "tcs_create_barrier_header";
 444    case TCS_OPCODE_SRC0_010_IS_ZERO:
 445       return "tcs_src0<0,1,0>_is_zero";
 446    case TCS_OPCODE_RELEASE_INPUT:
 447       return "tcs_release_input";
 448    case TCS_OPCODE_THREAD_END:
 449       return "tcs_thread_end";
 450    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 451       return "tes_create_input_read_header";
 452    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 453       return "tes_add_indirect_urb_offset";
 454    case TES_OPCODE_GET_PRIMITIVE_ID:
 455       return "tes_get_primitive_id";
 456    }
 457
 458    unreachable("not reached");
 459 }
 460
 461 bool
 462 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 463 {
 464    union {
 465       unsigned ud;
 466       int d;
 467       float f;
 468       double df;
 469    } imm, sat_imm = { 0 };
 470
 471    const unsigned size = type_sz(type);
 472
 473    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 474     * irrelevant, so just check the size of the type and copy from/to an
 475     * appropriately sized field.
 476     */
 477    if (size < 8)
 478       imm.ud = reg->ud;
 479    else
 480       imm.df = reg->df;
 481
 482    switch (type) {
 483    case BRW_REGISTER_TYPE_UD:
 484    case BRW_REGISTER_TYPE_D:
 485    case BRW_REGISTER_TYPE_UW:
 486    case BRW_REGISTER_TYPE_W:
 487    case BRW_REGISTER_TYPE_UQ:
 488    case BRW_REGISTER_TYPE_Q:
 489       /* Nothing to do. */
 490       return false;
 491    case BRW_REGISTER_TYPE_F:
 492       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 493       break;
 494    case BRW_REGISTER_TYPE_DF:
 495       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 496       break;
 497    case BRW_REGISTER_TYPE_UB:
 498    case BRW_REGISTER_TYPE_B:
 499       unreachable("no UB/B immediates");
 500    case BRW_REGISTER_TYPE_V:
 501    case BRW_REGISTER_TYPE_UV:
 502    case BRW_REGISTER_TYPE_VF:
 503       unreachable("unimplemented: saturate vector immediate");
 504    case BRW_REGISTER_TYPE_HF:
 505       unreachable("unimplemented: saturate HF immediate");
 506    }
 507
 508    if (size < 8) {
 509       if (imm.ud != sat_imm.ud) {
 510          reg->ud = sat_imm.ud;
 511          return true;
 512       }
 513    } else {
 514       if (imm.df != sat_imm.df) {
 515          reg->df = sat_imm.df;
 516          return true;
 517       }
 518    }
 519    return false;
 520 }
 521
 522 bool
 523 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 524 {
 525    switch (type) {
 526    case BRW_REGISTER_TYPE_D:
 527    case BRW_REGISTER_TYPE_UD:
 528       reg->d = -reg->d;
 529       return true;
 530    case BRW_REGISTER_TYPE_W:
 531    case BRW_REGISTER_TYPE_UW:
 532       reg->d = -(int16_t)reg->ud;
 533       return true;
 534    case BRW_REGISTER_TYPE_F:
 535       reg->f = -reg->f;
 536       return true;
 537    case BRW_REGISTER_TYPE_VF:
 538       reg->ud ^= 0x80808080;
 539       return true;
 540    case BRW_REGISTER_TYPE_DF:
 541       reg->df = -reg->df;
 542       return true;
 543    case BRW_REGISTER_TYPE_UB:
 544    case BRW_REGISTER_TYPE_B:
 545       unreachable("no UB/B immediates");
 546    case BRW_REGISTER_TYPE_UV:
 547    case BRW_REGISTER_TYPE_V:
 548       assert(!"unimplemented: negate UV/V immediate");
 549    case BRW_REGISTER_TYPE_UQ:
 550    case BRW_REGISTER_TYPE_Q:
 551       assert(!"unimplemented: negate UQ/Q immediate");
 552    case BRW_REGISTER_TYPE_HF:
 553       assert(!"unimplemented: negate HF immediate");
 554    }
 555
 556    return false;
 557 }
 558
 559 bool
 560 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 561 {
 562    switch (type) {
 563    case BRW_REGISTER_TYPE_D:
 564       reg->d = abs(reg->d);
 565       return true;
 566    case BRW_REGISTER_TYPE_W:
 567       reg->d = abs((int16_t)reg->ud);
 568       return true;
 569    case BRW_REGISTER_TYPE_F:
 570       reg->f = fabsf(reg->f);
 571       return true;
 572    case BRW_REGISTER_TYPE_DF:
 573       reg->df = fabs(reg->df);
 574       return true;
 575    case BRW_REGISTER_TYPE_VF:
 576       reg->ud &= ~0x80808080;
 577       return true;
 578    case BRW_REGISTER_TYPE_UB:
 579    case BRW_REGISTER_TYPE_B:
 580       unreachable("no UB/B immediates");
 581    case BRW_REGISTER_TYPE_UQ:
 582    case BRW_REGISTER_TYPE_UD:
 583    case BRW_REGISTER_TYPE_UW:
 584    case BRW_REGISTER_TYPE_UV:
 585       /* Presumably the absolute value modifier on an unsigned source is a
 586        * nop, but it would be nice to confirm.
 587        */
 588       assert(!"unimplemented: abs unsigned immediate");
 589    case BRW_REGISTER_TYPE_V:
 590       assert(!"unimplemented: abs V immediate");
 591    case BRW_REGISTER_TYPE_Q:
 592       assert(!"unimplemented: abs Q immediate");
 593    case BRW_REGISTER_TYPE_HF:
 594       assert(!"unimplemented: abs HF immediate");
 595    }
 596
 597    return false;
 598 }
 599
 600 unsigned
 601 tesslevel_outer_components(GLenum tes_primitive_mode)
 602 {
 603    switch (tes_primitive_mode) {
 604    case GL_QUADS:
 605       return 4;
 606    case GL_TRIANGLES:
 607       return 3;
 608    case GL_ISOLINES:
 609       return 2;
 610    default:
 611       unreachable("Bogus tessellation domain");
 612    }
 613    return 0;
 614 }
 615
 616 unsigned
 617 tesslevel_inner_components(GLenum tes_primitive_mode)
 618 {
 619    switch (tes_primitive_mode) {
 620    case GL_QUADS:
 621       return 2;
 622    case GL_TRIANGLES:
 623       return 1;
 624    case GL_ISOLINES:
 625       return 0;
 626    default:
 627       unreachable("Bogus tessellation domain");
 628    }
 629    return 0;
 630 }
 631
 632 /**
 633  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 634  * that's stored backwards, i.e. .wzyx.
 635  */
 636 unsigned
 637 writemask_for_backwards_vector(unsigned mask)
 638 {
 639    unsigned new_mask = 0;
 640
 641    for (int i = 0; i < 4; i++)
 642       new_mask |= ((mask >> i) & 1) << (3 - i);
 643
 644    return new_mask;
 645 }
 646
 647 backend_shader::backend_shader(const struct brw_compiler *compiler,
 648                                void *log_data,
 649                                void *mem_ctx,
 650                                const nir_shader *shader,
 651                                struct brw_stage_prog_data *stage_prog_data)
 652    : compiler(compiler),
 653      log_data(log_data),
 654      devinfo(compiler->devinfo),
 655      nir(shader),
 656      stage_prog_data(stage_prog_data),
 657      mem_ctx(mem_ctx),
 658      cfg(NULL),
 659      stage(shader->stage)
 660 {
 661    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 662    stage_name = _mesa_shader_stage_to_string(stage);
 663    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 664    is_passthrough_shader =
 665       nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
 666 }
 667
 668 bool
 669 backend_reg::equals(const backend_reg &r) const
 670 {
 671    return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
 672 }
 673
 674 bool
 675 backend_reg::is_zero() const
 676 {
 677    if (file != IMM)
 678       return false;
 679
 680    switch (type) {
 681    case BRW_REGISTER_TYPE_F:
 682       return f == 0;
 683    case BRW_REGISTER_TYPE_DF:
 684       return df == 0;
 685    case BRW_REGISTER_TYPE_D:
 686    case BRW_REGISTER_TYPE_UD:
 687       return d == 0;
 688    default:
 689       return false;
 690    }
 691 }
 692
 693 bool
 694 backend_reg::is_one() const
 695 {
 696    if (file != IMM)
 697       return false;
 698
 699    switch (type) {
 700    case BRW_REGISTER_TYPE_F:
 701       return f == 1.0f;
 702    case BRW_REGISTER_TYPE_DF:
 703       return df == 1.0;
 704    case BRW_REGISTER_TYPE_D:
 705    case BRW_REGISTER_TYPE_UD:
 706       return d == 1;
 707    default:
 708       return false;
 709    }
 710 }
 711
 712 bool
 713 backend_reg::is_negative_one() const
 714 {
 715    if (file != IMM)
 716       return false;
 717
 718    switch (type) {
 719    case BRW_REGISTER_TYPE_F:
 720       return f == -1.0;
 721    case BRW_REGISTER_TYPE_DF:
 722       return df == -1.0;
 723    case BRW_REGISTER_TYPE_D:
 724       return d == -1;
 725    default:
 726       return false;
 727    }
 728 }
 729
 730 bool
 731 backend_reg::is_null() const
 732 {
 733    return file == ARF && nr == BRW_ARF_NULL;
 734 }
 735
 736
 737 bool
 738 backend_reg::is_accumulator() const
 739 {
 740    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 741 }
 742
 743 bool
 744 backend_reg::in_range(const backend_reg &r, unsigned n) const
 745 {
 746    return (file == r.file &&
 747            nr == r.nr &&
 748            reg_offset >= r.reg_offset &&
 749            reg_offset < r.reg_offset + n);
 750 }
 751
 752 bool
 753 backend_instruction::is_commutative() const
 754 {
 755    switch (opcode) {
 756    case BRW_OPCODE_AND:
 757    case BRW_OPCODE_OR:
 758    case BRW_OPCODE_XOR:
 759    case BRW_OPCODE_ADD:
 760    case BRW_OPCODE_MUL:
 761    case SHADER_OPCODE_MULH:
 762       return true;
 763    case BRW_OPCODE_SEL:
 764       /* MIN and MAX are commutative. */
 765       if (conditional_mod == BRW_CONDITIONAL_GE ||
 766           conditional_mod == BRW_CONDITIONAL_L) {
 767          return true;
 768       }
 769       /* fallthrough */
 770    default:
 771       return false;
 772    }
 773 }
 774
 775 bool
 776 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
 777 {
 778    return ::is_3src(devinfo, opcode);
 779 }
 780
 781 bool
 782 backend_instruction::is_tex() const
 783 {
 784    return (opcode == SHADER_OPCODE_TEX ||
 785            opcode == FS_OPCODE_TXB ||
 786            opcode == SHADER_OPCODE_TXD ||
 787            opcode == SHADER_OPCODE_TXF ||
 788            opcode == SHADER_OPCODE_TXF_LZ ||
 789            opcode == SHADER_OPCODE_TXF_CMS ||
 790            opcode == SHADER_OPCODE_TXF_CMS_W ||
 791            opcode == SHADER_OPCODE_TXF_UMS ||
 792            opcode == SHADER_OPCODE_TXF_MCS ||
 793            opcode == SHADER_OPCODE_TXL ||
 794            opcode == SHADER_OPCODE_TXL_LZ ||
 795            opcode == SHADER_OPCODE_TXS ||
 796            opcode == SHADER_OPCODE_LOD ||
 797            opcode == SHADER_OPCODE_TG4 ||
 798            opcode == SHADER_OPCODE_TG4_OFFSET ||
 799            opcode == SHADER_OPCODE_SAMPLEINFO);
 800 }
 801
 802 bool
 803 backend_instruction::is_math() const
 804 {
 805    return (opcode == SHADER_OPCODE_RCP ||
 806            opcode == SHADER_OPCODE_RSQ ||
 807            opcode == SHADER_OPCODE_SQRT ||
 808            opcode == SHADER_OPCODE_EXP2 ||
 809            opcode == SHADER_OPCODE_LOG2 ||
 810            opcode == SHADER_OPCODE_SIN ||
 811            opcode == SHADER_OPCODE_COS ||
 812            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 813            opcode == SHADER_OPCODE_INT_REMAINDER ||
 814            opcode == SHADER_OPCODE_POW);
 815 }
 816
 817 bool
 818 backend_instruction::is_control_flow() const
 819 {
 820    switch (opcode) {
 821    case BRW_OPCODE_DO:
 822    case BRW_OPCODE_WHILE:
 823    case BRW_OPCODE_IF:
 824    case BRW_OPCODE_ELSE:
 825    case BRW_OPCODE_ENDIF:
 826    case BRW_OPCODE_BREAK:
 827    case BRW_OPCODE_CONTINUE:
 828       return true;
 829    default:
 830       return false;
 831    }
 832 }
 833
 834 bool
 835 backend_instruction::can_do_source_mods() const
 836 {
 837    switch (opcode) {
 838    case BRW_OPCODE_ADDC:
 839    case BRW_OPCODE_BFE:
 840    case BRW_OPCODE_BFI1:
 841    case BRW_OPCODE_BFI2:
 842    case BRW_OPCODE_BFREV:
 843    case BRW_OPCODE_CBIT:
 844    case BRW_OPCODE_FBH:
 845    case BRW_OPCODE_FBL:
 846    case BRW_OPCODE_SUBB:
 847       return false;
 848    default:
 849       return true;
 850    }
 851 }
 852
 853 bool
 854 backend_instruction::can_do_saturate() const
 855 {
 856    switch (opcode) {
 857    case BRW_OPCODE_ADD:
 858    case BRW_OPCODE_ASR:
 859    case BRW_OPCODE_AVG:
 860    case BRW_OPCODE_DP2:
 861    case BRW_OPCODE_DP3:
 862    case BRW_OPCODE_DP4:
 863    case BRW_OPCODE_DPH:
 864    case BRW_OPCODE_F16TO32:
 865    case BRW_OPCODE_F32TO16:
 866    case BRW_OPCODE_LINE:
 867    case BRW_OPCODE_LRP:
 868    case BRW_OPCODE_MAC:
 869    case BRW_OPCODE_MAD:
 870    case BRW_OPCODE_MATH:
 871    case BRW_OPCODE_MOV:
 872    case BRW_OPCODE_MUL:
 873    case SHADER_OPCODE_MULH:
 874    case BRW_OPCODE_PLN:
 875    case BRW_OPCODE_RNDD:
 876    case BRW_OPCODE_RNDE:
 877    case BRW_OPCODE_RNDU:
 878    case BRW_OPCODE_RNDZ:
 879    case BRW_OPCODE_SEL:
 880    case BRW_OPCODE_SHL:
 881    case BRW_OPCODE_SHR:
 882    case FS_OPCODE_LINTERP:
 883    case SHADER_OPCODE_COS:
 884    case SHADER_OPCODE_EXP2:
 885    case SHADER_OPCODE_LOG2:
 886    case SHADER_OPCODE_POW:
 887    case SHADER_OPCODE_RCP:
 888    case SHADER_OPCODE_RSQ:
 889    case SHADER_OPCODE_SIN:
 890    case SHADER_OPCODE_SQRT:
 891       return true;
 892    default:
 893       return false;
 894    }
 895 }
 896
 897 bool
 898 backend_instruction::can_do_cmod() const
 899 {
 900    switch (opcode) {
 901    case BRW_OPCODE_ADD:
 902    case BRW_OPCODE_ADDC:
 903    case BRW_OPCODE_AND:
 904    case BRW_OPCODE_ASR:
 905    case BRW_OPCODE_AVG:
 906    case BRW_OPCODE_CMP:
 907    case BRW_OPCODE_CMPN:
 908    case BRW_OPCODE_DP2:
 909    case BRW_OPCODE_DP3:
 910    case BRW_OPCODE_DP4:
 911    case BRW_OPCODE_DPH:
 912    case BRW_OPCODE_F16TO32:
 913    case BRW_OPCODE_F32TO16:
 914    case BRW_OPCODE_FRC:
 915    case BRW_OPCODE_LINE:
 916    case BRW_OPCODE_LRP:
 917    case BRW_OPCODE_LZD:
 918    case BRW_OPCODE_MAC:
 919    case BRW_OPCODE_MACH:
 920    case BRW_OPCODE_MAD:
 921    case BRW_OPCODE_MOV:
 922    case BRW_OPCODE_MUL:
 923    case BRW_OPCODE_NOT:
 924    case BRW_OPCODE_OR:
 925    case BRW_OPCODE_PLN:
 926    case BRW_OPCODE_RNDD:
 927    case BRW_OPCODE_RNDE:
 928    case BRW_OPCODE_RNDU:
 929    case BRW_OPCODE_RNDZ:
 930    case BRW_OPCODE_SAD2:
 931    case BRW_OPCODE_SADA2:
 932    case BRW_OPCODE_SHL:
 933    case BRW_OPCODE_SHR:
 934    case BRW_OPCODE_SUBB:
 935    case BRW_OPCODE_XOR:
 936    case FS_OPCODE_CINTERP:
 937    case FS_OPCODE_LINTERP:
 938       return true;
 939    default:
 940       return false;
 941    }
 942 }
 943
 944 bool
 945 backend_instruction::reads_accumulator_implicitly() const
 946 {
 947    switch (opcode) {
 948    case BRW_OPCODE_MAC:
 949    case BRW_OPCODE_MACH:
 950    case BRW_OPCODE_SADA2:
 951       return true;
 952    default:
 953       return false;
 954    }
 955 }
 956
 957 bool
 958 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 959 {
 960    return writes_accumulator ||
 961           (devinfo->gen < 6 &&
 962            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 963             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 964              opcode != FS_OPCODE_CINTERP)));
 965 }
 966
 967 bool
 968 backend_instruction::has_side_effects() const
 969 {
 970    switch (opcode) {
 971    case SHADER_OPCODE_UNTYPED_ATOMIC:
 972    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 973    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 974    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 975    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 976    case SHADER_OPCODE_TYPED_ATOMIC:
 977    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 978    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 979    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 980    case SHADER_OPCODE_MEMORY_FENCE:
 981    case SHADER_OPCODE_URB_WRITE_SIMD8:
 982    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 983    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 984    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 985    case FS_OPCODE_FB_WRITE:
 986    case FS_OPCODE_FB_WRITE_LOGICAL:
 987    case SHADER_OPCODE_BARRIER:
 988    case TCS_OPCODE_URB_WRITE:
 989    case TCS_OPCODE_RELEASE_INPUT:
 990       return true;
 991    default:
 992       return false;
 993    }
 994 }
 995
 996 bool
 997 backend_instruction::is_volatile() const
 998 {
 999    switch (opcode) {
1000    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1001    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1002    case SHADER_OPCODE_TYPED_SURFACE_READ:
1003    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1004    case SHADER_OPCODE_URB_READ_SIMD8:
1005    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1006    case VEC4_OPCODE_URB_READ:
1007       return true;
1008    default:
1009       return false;
1010    }
1011 }
1012
1013 #ifndef NDEBUG
1014 static bool
1015 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1016 {
1017    bool found = false;
1018    foreach_inst_in_block (backend_instruction, i, block) {
1019       if (inst == i) {
1020          found = true;
1021       }
1022    }
1023    return found;
1024 }
1025 #endif
1026
1027 static void
1028 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1029 {
1030    for (bblock_t *block_iter = start_block->next();
1031         block_iter;
1032         block_iter = block_iter->next()) {
1033       block_iter->start_ip += ip_adjustment;
1034       block_iter->end_ip += ip_adjustment;
1035    }
1036 }
1037
1038 void
1039 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1040 {
1041    assert(this != inst);
1042
1043    if (!this->is_head_sentinel())
1044       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1045
1046    block->end_ip++;
1047
1048    adjust_later_block_ips(block, 1);
1049
1050    exec_node::insert_after(inst);
1051 }
1052
1053 void
1054 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1055 {
1056    assert(this != inst);
1057
1058    if (!this->is_tail_sentinel())
1059       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1060
1061    block->end_ip++;
1062
1063    adjust_later_block_ips(block, 1);
1064
1065    exec_node::insert_before(inst);
1066 }
1067
1068 void
1069 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1070 {
1071    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1072
1073    unsigned num_inst = list->length();
1074
1075    block->end_ip += num_inst;
1076
1077    adjust_later_block_ips(block, num_inst);
1078
1079    exec_node::insert_before(list);
1080 }
1081
1082 void
1083 backend_instruction::remove(bblock_t *block)
1084 {
1085    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1086
1087    adjust_later_block_ips(block, -1);
1088
1089    if (block->start_ip == block->end_ip) {
1090       block->cfg->remove_block(block);
1091    } else {
1092       block->end_ip--;
1093    }
1094
1095    exec_node::remove();
1096 }
1097
1098 void
1099 backend_shader::dump_instructions()
1100 {
1101    dump_instructions(NULL);
1102 }
1103
1104 void
1105 backend_shader::dump_instructions(const char *name)
1106 {
1107    FILE *file = stderr;
1108    if (name && geteuid() != 0) {
1109       file = fopen(name, "w");
1110       if (!file)
1111          file = stderr;
1112    }
1113
1114    if (cfg) {
1115       int ip = 0;
1116       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1117          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1118             fprintf(file, "%4d: ", ip++);
1119          dump_instruction(inst, file);
1120       }
1121    } else {
1122       int ip = 0;
1123       foreach_in_list(backend_instruction, inst, &instructions) {
1124          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1125             fprintf(file, "%4d: ", ip++);
1126          dump_instruction(inst, file);
1127       }
1128    }
1129
1130    if (file != stderr) {
1131       fclose(file);
1132    }
1133 }
1134
1135 void
1136 backend_shader::calculate_cfg()
1137 {
1138    if (this->cfg)
1139       return;
1140    cfg = new(mem_ctx) cfg_t(&this->instructions);
1141 }
1142
1143 /**
1144  * Sets up the starting offsets for the groups of binding table entries
1145  * commong to all pipeline stages.
1146  *
1147  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1148  * unused but also make sure that addition of small offsets to them will
1149  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1150  */
1151 uint32_t
1152 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1153                                         const struct brw_device_info *devinfo,
1154                                         const struct gl_shader_program *shader_prog,
1155                                         const struct gl_program *prog,
1156                                         struct brw_stage_prog_data *stage_prog_data,
1157                                         uint32_t next_binding_table_offset)
1158 {
1159    const struct gl_linked_shader *shader = NULL;
1160    int num_textures = util_last_bit(prog->SamplersUsed);
1161
1162    if (shader_prog)
1163       shader = shader_prog->_LinkedShaders[stage];
1164
1165    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1166    next_binding_table_offset += num_textures;
1167
1168    if (shader) {
1169       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1170       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1171       next_binding_table_offset += shader->NumUniformBlocks;
1172
1173       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1174       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1175       next_binding_table_offset += shader->NumShaderStorageBlocks;
1176    } else {
1177       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1178       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1179    }
1180
1181    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1182       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1183       next_binding_table_offset++;
1184    } else {
1185       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1186    }
1187
1188    if (prog->UsesGather) {
1189       if (devinfo->gen >= 8) {
1190          stage_prog_data->binding_table.gather_texture_start =
1191             stage_prog_data->binding_table.texture_start;
1192       } else {
1193          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1194          next_binding_table_offset += num_textures;
1195       }
1196    } else {
1197       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1198    }
1199
1200    if (shader && shader->NumAtomicBuffers) {
1201       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1202       next_binding_table_offset += shader->NumAtomicBuffers;
1203    } else {
1204       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1205    }
1206
1207    if (shader && shader->NumImages) {
1208       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1209       next_binding_table_offset += shader->NumImages;
1210    } else {
1211       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1212    }
1213
1214    /* This may or may not be used depending on how the compile goes. */
1215    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1216    next_binding_table_offset++;
1217
1218    /* Plane 0 is just the regular texture section */
1219    stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
1220
1221    stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
1222    next_binding_table_offset += num_textures;
1223
1224    stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
1225    next_binding_table_offset += num_textures;
1226
1227    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1228
1229    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1230    return next_binding_table_offset;
1231 }
1232
1233 static void
1234 setup_vec4_uniform_value(const gl_constant_value **params,
1235                          const gl_constant_value *values,
1236                          unsigned n)
1237 {
1238    static const gl_constant_value zero = { 0 };
1239
1240    for (unsigned i = 0; i < n; ++i)
1241       params[i] = &values[i];
1242
1243    for (unsigned i = n; i < 4; ++i)
1244       params[i] = &zero;
1245 }
1246
1247 void
1248 brw_setup_image_uniform_values(gl_shader_stage stage,
1249                                struct brw_stage_prog_data *stage_prog_data,
1250                                unsigned param_start_index,
1251                                const gl_uniform_storage *storage)
1252 {
1253    const gl_constant_value **param =
1254       &stage_prog_data->param[param_start_index];
1255
1256    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1257       const unsigned image_idx = storage->opaque[stage].index + i;
1258       const brw_image_param *image_param =
1259          &stage_prog_data->image_param[image_idx];
1260
1261       /* Upload the brw_image_param structure.  The order is expected to match
1262        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1263        */
1264       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1265          (const gl_constant_value *)&image_param->surface_idx, 1);
1266       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1267          (const gl_constant_value *)image_param->offset, 2);
1268       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1269          (const gl_constant_value *)image_param->size, 3);
1270       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1271          (const gl_constant_value *)image_param->stride, 4);
1272       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1273          (const gl_constant_value *)image_param->tiling, 3);
1274       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1275          (const gl_constant_value *)image_param->swizzling, 2);
1276       param += BRW_IMAGE_PARAM_SIZE;
1277
1278       brw_mark_surface_used(
1279          stage_prog_data,
1280          stage_prog_data->binding_table.image_start + image_idx);
1281    }
1282 }
1283
1284 /**
1285  * Decide which set of clip planes should be used when clipping via
1286  * gl_Position or gl_ClipVertex.
1287  */
1288 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1289 {
1290    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1291       /* There is currently a GLSL vertex shader, so clip according to GLSL
1292        * rules, which means compare gl_ClipVertex (or gl_Position, if
1293        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1294        * that were stored in EyeUserPlane at the time the clip planes were
1295        * specified.
1296        */
1297       return ctx->Transform.EyeUserPlane;
1298    } else {
1299       /* Either we are using fixed function or an ARB vertex program.  In
1300        * either case the clip planes are going to be compared against
1301        * gl_Position (which is in clip coordinates) so we have to clip using
1302        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1303        * core.
1304        */
1305       return ctx->Transform._ClipUserPlane;
1306    }
1307 }
1308
1309 extern "C" const unsigned *
1310 brw_compile_tes(const struct brw_compiler *compiler,
1311                 void *log_data,
1312                 void *mem_ctx,
1313                 const struct brw_tes_prog_key *key,
1314                 struct brw_tes_prog_data *prog_data,
1315                 const nir_shader *src_shader,
1316                 struct gl_shader_program *shader_prog,
1317                 int shader_time_index,
1318                 unsigned *final_assembly_size,
1319                 char **error_str)
1320 {
1321    const struct brw_device_info *devinfo = compiler->devinfo;
1322    struct gl_linked_shader *shader =
1323       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1324    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1325
1326    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1327    nir->info.inputs_read = key->inputs_read;
1328    nir->info.patch_inputs_read = key->patch_inputs_read;
1329
1330    struct brw_vue_map input_vue_map;
1331    brw_compute_tess_vue_map(&input_vue_map,
1332                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1333                             nir->info.patch_inputs_read);
1334
1335    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1336    brw_nir_lower_tes_inputs(nir, &input_vue_map);
1337    brw_nir_lower_vue_outputs(nir, is_scalar);
1338    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1339
1340    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1341                        nir->info.outputs_written,
1342                        nir->info.separate_shader);
1343
1344    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1345
1346    assert(output_size_bytes >= 1);
1347    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1348       if (error_str)
1349          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1350       return NULL;
1351    }
1352
1353    /* URB entry sizes are stored as a multiple of 64 bytes. */
1354    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1355
1356    bool need_patch_header = nir->info.system_values_read &
1357       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1358        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1359
1360    /* The TES will pull most inputs using URB read messages.
1361     *
1362     * However, we push the patch header for TessLevel factors when required,
1363     * as it's a tiny amount of extra data.
1364     */
1365    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1366
1367    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1368       fprintf(stderr, "TES Input ");
1369       brw_print_vue_map(stderr, &input_vue_map);
1370       fprintf(stderr, "TES Output ");
1371       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1372    }
1373
1374    if (is_scalar) {
1375       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1376                    &prog_data->base.base, shader->Program, nir, 8,
1377                    shader_time_index, &input_vue_map);
1378       if (!v.run_tes()) {
1379          if (error_str)
1380             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1381          return NULL;
1382       }
1383
1384       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1385       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1386
1387       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1388                      &prog_data->base.base, v.promoted_constants, false,
1389                      MESA_SHADER_TESS_EVAL);
1390       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1391          g.enable_debug(ralloc_asprintf(mem_ctx,
1392                                         "%s tessellation evaluation shader %s",
1393                                         nir->info.label ? nir->info.label
1394                                                         : "unnamed",
1395                                         nir->info.name));
1396       }
1397
1398       g.generate_code(v.cfg, 8);
1399
1400       return g.get_assembly(final_assembly_size);
1401    } else {
1402       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1403                               nir, mem_ctx, shader_time_index);
1404       if (!v.run()) {
1405          if (error_str)
1406             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1407          return NULL;
1408       }
1409
1410       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1411          v.dump_instructions();
1412
1413       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1414                                         &prog_data->base, v.cfg,
1415                                         final_assembly_size);
1416    }
1417 }