2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/macros.h"
25 #include "brw_context.h"
31 #include "glsl/ir_optimization.h"
32 #include "glsl/glsl_parser_extras.h"
33 #include "main/shaderapi.h"
36 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
38 struct brw_context
*brw
= (struct brw_context
*)data
;
43 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
44 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
45 MESA_DEBUG_TYPE_OTHER
,
46 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
51 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
53 struct brw_context
*brw
= (struct brw_context
*)data
;
58 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
60 va_copy(args_copy
, args
);
61 vfprintf(stderr
, fmt
, args_copy
);
65 if (brw
->perf_debug
) {
67 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
68 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
69 MESA_DEBUG_TYPE_PERFORMANCE
,
70 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
76 is_scalar_shader_stage(const struct brw_compiler
*compiler
, int stage
)
79 case MESA_SHADER_FRAGMENT
:
80 case MESA_SHADER_COMPUTE
:
82 case MESA_SHADER_GEOMETRY
:
83 return compiler
->scalar_gs
;
84 case MESA_SHADER_VERTEX
:
85 return compiler
->scalar_vs
;
92 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
94 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
96 compiler
->devinfo
= devinfo
;
97 compiler
->shader_debug_log
= shader_debug_log_mesa
;
98 compiler
->shader_perf_log
= shader_perf_log_mesa
;
100 brw_fs_alloc_reg_sets(compiler
);
101 brw_vec4_alloc_reg_set(compiler
);
103 if (devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
))
104 compiler
->scalar_vs
= true;
106 if (devinfo
->gen
>= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false))
107 compiler
->scalar_gs
= true;
109 nir_shader_compiler_options
*nir_options
=
110 rzalloc(compiler
, nir_shader_compiler_options
);
111 nir_options
->native_integers
= true;
112 /* In order to help allow for better CSE at the NIR level we tell NIR
113 * to split all ffma instructions during opt_algebraic and we then
114 * re-combine them as a later step.
116 nir_options
->lower_ffma
= true;
117 nir_options
->lower_sub
= true;
118 /* In the vec4 backend, our dpN instruction replicates its result to all
119 * the components of a vec4. We would like NIR to give us replicated fdot
120 * instructions because it can optimize better for us.
122 * For the FS backend, it should be lowered away by the scalarizing pass so
123 * we should never see fdot anyway.
125 nir_options
->fdot_replicates
= true;
127 /* We want the GLSL compiler to emit code that uses condition codes */
128 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
129 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
130 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
131 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
133 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
134 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
135 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
136 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
137 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
138 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
140 bool is_scalar
= is_scalar_shader_stage(compiler
, i
);
142 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
143 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
144 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
146 /* !ARB_gpu_shader5 */
147 if (devinfo
->gen
< 7)
148 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
150 compiler
->glsl_compiler_options
[i
].NirOptions
= nir_options
;
152 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
159 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
161 struct brw_shader
*shader
;
163 shader
= rzalloc(NULL
, struct brw_shader
);
165 shader
->base
.Type
= type
;
166 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
167 shader
->base
.Name
= name
;
168 _mesa_init_shader(ctx
, &shader
->base
);
171 return &shader
->base
;
175 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
178 assert(surf_index
< BRW_MAX_SURFACES
);
180 prog_data
->binding_table
.size_bytes
=
181 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
185 brw_type_for_base_type(const struct glsl_type
*type
)
187 switch (type
->base_type
) {
188 case GLSL_TYPE_FLOAT
:
189 return BRW_REGISTER_TYPE_F
;
192 case GLSL_TYPE_SUBROUTINE
:
193 return BRW_REGISTER_TYPE_D
;
195 return BRW_REGISTER_TYPE_UD
;
196 case GLSL_TYPE_ARRAY
:
197 return brw_type_for_base_type(type
->fields
.array
);
198 case GLSL_TYPE_STRUCT
:
199 case GLSL_TYPE_SAMPLER
:
200 case GLSL_TYPE_ATOMIC_UINT
:
201 /* These should be overridden with the type of the member when
202 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
203 * way to trip up if we don't.
205 return BRW_REGISTER_TYPE_UD
;
206 case GLSL_TYPE_IMAGE
:
207 return BRW_REGISTER_TYPE_UD
;
209 case GLSL_TYPE_ERROR
:
210 case GLSL_TYPE_INTERFACE
:
211 case GLSL_TYPE_DOUBLE
:
212 unreachable("not reached");
215 return BRW_REGISTER_TYPE_F
;
218 enum brw_conditional_mod
219 brw_conditional_for_comparison(unsigned int op
)
223 return BRW_CONDITIONAL_L
;
224 case ir_binop_greater
:
225 return BRW_CONDITIONAL_G
;
226 case ir_binop_lequal
:
227 return BRW_CONDITIONAL_LE
;
228 case ir_binop_gequal
:
229 return BRW_CONDITIONAL_GE
;
231 case ir_binop_all_equal
: /* same as equal for scalars */
232 return BRW_CONDITIONAL_Z
;
233 case ir_binop_nequal
:
234 case ir_binop_any_nequal
: /* same as nequal for scalars */
235 return BRW_CONDITIONAL_NZ
;
237 unreachable("not reached: bad operation for comparison");
242 brw_math_function(enum opcode op
)
245 case SHADER_OPCODE_RCP
:
246 return BRW_MATH_FUNCTION_INV
;
247 case SHADER_OPCODE_RSQ
:
248 return BRW_MATH_FUNCTION_RSQ
;
249 case SHADER_OPCODE_SQRT
:
250 return BRW_MATH_FUNCTION_SQRT
;
251 case SHADER_OPCODE_EXP2
:
252 return BRW_MATH_FUNCTION_EXP
;
253 case SHADER_OPCODE_LOG2
:
254 return BRW_MATH_FUNCTION_LOG
;
255 case SHADER_OPCODE_POW
:
256 return BRW_MATH_FUNCTION_POW
;
257 case SHADER_OPCODE_SIN
:
258 return BRW_MATH_FUNCTION_SIN
;
259 case SHADER_OPCODE_COS
:
260 return BRW_MATH_FUNCTION_COS
;
261 case SHADER_OPCODE_INT_QUOTIENT
:
262 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
263 case SHADER_OPCODE_INT_REMAINDER
:
264 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
266 unreachable("not reached: unknown math function");
271 brw_texture_offset(int *offsets
, unsigned num_components
)
273 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
275 /* Combine all three offsets into a single unsigned dword:
277 * bits 11:8 - U Offset (X component)
278 * bits 7:4 - V Offset (Y component)
279 * bits 3:0 - R Offset (Z component)
281 unsigned offset_bits
= 0;
282 for (unsigned i
= 0; i
< num_components
; i
++) {
283 const unsigned shift
= 4 * (2 - i
);
284 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
290 brw_instruction_name(enum opcode op
)
293 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
294 assert(opcode_descs
[op
].name
);
295 return opcode_descs
[op
].name
;
296 case FS_OPCODE_FB_WRITE
:
298 case FS_OPCODE_FB_WRITE_LOGICAL
:
299 return "fb_write_logical";
300 case FS_OPCODE_PACK_STENCIL_REF
:
301 return "pack_stencil_ref";
302 case FS_OPCODE_BLORP_FB_WRITE
:
303 return "blorp_fb_write";
304 case FS_OPCODE_REP_FB_WRITE
:
305 return "rep_fb_write";
307 case SHADER_OPCODE_RCP
:
309 case SHADER_OPCODE_RSQ
:
311 case SHADER_OPCODE_SQRT
:
313 case SHADER_OPCODE_EXP2
:
315 case SHADER_OPCODE_LOG2
:
317 case SHADER_OPCODE_POW
:
319 case SHADER_OPCODE_INT_QUOTIENT
:
321 case SHADER_OPCODE_INT_REMAINDER
:
323 case SHADER_OPCODE_SIN
:
325 case SHADER_OPCODE_COS
:
328 case SHADER_OPCODE_TEX
:
330 case SHADER_OPCODE_TEX_LOGICAL
:
331 return "tex_logical";
332 case SHADER_OPCODE_TXD
:
334 case SHADER_OPCODE_TXD_LOGICAL
:
335 return "txd_logical";
336 case SHADER_OPCODE_TXF
:
338 case SHADER_OPCODE_TXF_LOGICAL
:
339 return "txf_logical";
340 case SHADER_OPCODE_TXL
:
342 case SHADER_OPCODE_TXL_LOGICAL
:
343 return "txl_logical";
344 case SHADER_OPCODE_TXS
:
346 case SHADER_OPCODE_TXS_LOGICAL
:
347 return "txs_logical";
350 case FS_OPCODE_TXB_LOGICAL
:
351 return "txb_logical";
352 case SHADER_OPCODE_TXF_CMS
:
354 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
355 return "txf_cms_logical";
356 case SHADER_OPCODE_TXF_CMS_W
:
358 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
359 return "txf_cms_w_logical";
360 case SHADER_OPCODE_TXF_UMS
:
362 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
363 return "txf_ums_logical";
364 case SHADER_OPCODE_TXF_MCS
:
366 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
367 return "txf_mcs_logical";
368 case SHADER_OPCODE_LOD
:
370 case SHADER_OPCODE_LOD_LOGICAL
:
371 return "lod_logical";
372 case SHADER_OPCODE_TG4
:
374 case SHADER_OPCODE_TG4_LOGICAL
:
375 return "tg4_logical";
376 case SHADER_OPCODE_TG4_OFFSET
:
378 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
379 return "tg4_offset_logical";
380 case SHADER_OPCODE_SAMPLEINFO
:
383 case SHADER_OPCODE_SHADER_TIME_ADD
:
384 return "shader_time_add";
386 case SHADER_OPCODE_UNTYPED_ATOMIC
:
387 return "untyped_atomic";
388 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
389 return "untyped_atomic_logical";
390 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
391 return "untyped_surface_read";
392 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
393 return "untyped_surface_read_logical";
394 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
395 return "untyped_surface_write";
396 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
397 return "untyped_surface_write_logical";
398 case SHADER_OPCODE_TYPED_ATOMIC
:
399 return "typed_atomic";
400 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
401 return "typed_atomic_logical";
402 case SHADER_OPCODE_TYPED_SURFACE_READ
:
403 return "typed_surface_read";
404 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
405 return "typed_surface_read_logical";
406 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
407 return "typed_surface_write";
408 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
409 return "typed_surface_write_logical";
410 case SHADER_OPCODE_MEMORY_FENCE
:
411 return "memory_fence";
413 case SHADER_OPCODE_LOAD_PAYLOAD
:
414 return "load_payload";
416 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
417 return "gen4_scratch_read";
418 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
419 return "gen4_scratch_write";
420 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
421 return "gen7_scratch_read";
422 case SHADER_OPCODE_URB_WRITE_SIMD8
:
423 return "gen8_urb_write_simd8";
424 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
425 return "gen8_urb_write_simd8_per_slot";
426 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
427 return "gen8_urb_write_simd8_masked";
428 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
429 return "gen8_urb_write_simd8_masked_per_slot";
430 case SHADER_OPCODE_URB_READ_SIMD8
:
431 return "urb_read_simd8";
433 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
434 return "find_live_channel";
435 case SHADER_OPCODE_BROADCAST
:
438 case VEC4_OPCODE_MOV_BYTES
:
440 case VEC4_OPCODE_PACK_BYTES
:
442 case VEC4_OPCODE_UNPACK_UNIFORM
:
443 return "unpack_uniform";
445 case FS_OPCODE_DDX_COARSE
:
447 case FS_OPCODE_DDX_FINE
:
449 case FS_OPCODE_DDY_COARSE
:
451 case FS_OPCODE_DDY_FINE
:
454 case FS_OPCODE_CINTERP
:
456 case FS_OPCODE_LINTERP
:
459 case FS_OPCODE_PIXEL_X
:
461 case FS_OPCODE_PIXEL_Y
:
464 case FS_OPCODE_GET_BUFFER_SIZE
:
465 return "fs_get_buffer_size";
467 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
468 return "uniform_pull_const";
469 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
470 return "uniform_pull_const_gen7";
471 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
472 return "varying_pull_const";
473 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
474 return "varying_pull_const_gen7";
476 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
477 return "mov_dispatch_to_flags";
478 case FS_OPCODE_DISCARD_JUMP
:
479 return "discard_jump";
481 case FS_OPCODE_SET_SAMPLE_ID
:
482 return "set_sample_id";
483 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
484 return "set_simd4x2_offset";
486 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
487 return "pack_half_2x16_split";
488 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
489 return "unpack_half_2x16_split_x";
490 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
491 return "unpack_half_2x16_split_y";
493 case FS_OPCODE_PLACEHOLDER_HALT
:
494 return "placeholder_halt";
496 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
497 return "interp_centroid";
498 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
499 return "interp_sample";
500 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
501 return "interp_shared_offset";
502 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
503 return "interp_per_slot_offset";
505 case VS_OPCODE_URB_WRITE
:
506 return "vs_urb_write";
507 case VS_OPCODE_PULL_CONSTANT_LOAD
:
508 return "pull_constant_load";
509 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
510 return "pull_constant_load_gen7";
512 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
513 return "set_simd4x2_header_gen9";
515 case VS_OPCODE_GET_BUFFER_SIZE
:
516 return "vs_get_buffer_size";
518 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
519 return "unpack_flags_simd4x2";
521 case GS_OPCODE_URB_WRITE
:
522 return "gs_urb_write";
523 case GS_OPCODE_URB_WRITE_ALLOCATE
:
524 return "gs_urb_write_allocate";
525 case GS_OPCODE_THREAD_END
:
526 return "gs_thread_end";
527 case GS_OPCODE_SET_WRITE_OFFSET
:
528 return "set_write_offset";
529 case GS_OPCODE_SET_VERTEX_COUNT
:
530 return "set_vertex_count";
531 case GS_OPCODE_SET_DWORD_2
:
532 return "set_dword_2";
533 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
534 return "prepare_channel_masks";
535 case GS_OPCODE_SET_CHANNEL_MASKS
:
536 return "set_channel_masks";
537 case GS_OPCODE_GET_INSTANCE_ID
:
538 return "get_instance_id";
539 case GS_OPCODE_FF_SYNC
:
541 case GS_OPCODE_SET_PRIMITIVE_ID
:
542 return "set_primitive_id";
543 case GS_OPCODE_SVB_WRITE
:
544 return "gs_svb_write";
545 case GS_OPCODE_SVB_SET_DST_INDEX
:
546 return "gs_svb_set_dst_index";
547 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
548 return "gs_ff_sync_set_primitives";
549 case CS_OPCODE_CS_TERMINATE
:
550 return "cs_terminate";
551 case SHADER_OPCODE_BARRIER
:
553 case SHADER_OPCODE_MULH
:
557 unreachable("not reached");
561 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
567 } imm
= { reg
->ud
}, sat_imm
= { 0 };
570 case BRW_REGISTER_TYPE_UD
:
571 case BRW_REGISTER_TYPE_D
:
572 case BRW_REGISTER_TYPE_UQ
:
573 case BRW_REGISTER_TYPE_Q
:
576 case BRW_REGISTER_TYPE_UW
:
577 sat_imm
.ud
= CLAMP(imm
.ud
, 0, USHRT_MAX
);
579 case BRW_REGISTER_TYPE_W
:
580 sat_imm
.d
= CLAMP(imm
.d
, SHRT_MIN
, SHRT_MAX
);
582 case BRW_REGISTER_TYPE_F
:
583 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
585 case BRW_REGISTER_TYPE_UB
:
586 case BRW_REGISTER_TYPE_B
:
587 unreachable("no UB/B immediates");
588 case BRW_REGISTER_TYPE_V
:
589 case BRW_REGISTER_TYPE_UV
:
590 case BRW_REGISTER_TYPE_VF
:
591 unreachable("unimplemented: saturate vector immediate");
592 case BRW_REGISTER_TYPE_DF
:
593 case BRW_REGISTER_TYPE_HF
:
594 unreachable("unimplemented: saturate DF/HF immediate");
597 if (imm
.ud
!= sat_imm
.ud
) {
598 reg
->ud
= sat_imm
.ud
;
605 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
608 case BRW_REGISTER_TYPE_D
:
609 case BRW_REGISTER_TYPE_UD
:
612 case BRW_REGISTER_TYPE_W
:
613 case BRW_REGISTER_TYPE_UW
:
614 reg
->d
= -(int16_t)reg
->ud
;
616 case BRW_REGISTER_TYPE_F
:
619 case BRW_REGISTER_TYPE_VF
:
620 reg
->ud
^= 0x80808080;
622 case BRW_REGISTER_TYPE_UB
:
623 case BRW_REGISTER_TYPE_B
:
624 unreachable("no UB/B immediates");
625 case BRW_REGISTER_TYPE_UV
:
626 case BRW_REGISTER_TYPE_V
:
627 assert(!"unimplemented: negate UV/V immediate");
628 case BRW_REGISTER_TYPE_UQ
:
629 case BRW_REGISTER_TYPE_Q
:
630 assert(!"unimplemented: negate UQ/Q immediate");
631 case BRW_REGISTER_TYPE_DF
:
632 case BRW_REGISTER_TYPE_HF
:
633 assert(!"unimplemented: negate DF/HF immediate");
640 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
643 case BRW_REGISTER_TYPE_D
:
644 reg
->d
= abs(reg
->d
);
646 case BRW_REGISTER_TYPE_W
:
647 reg
->d
= abs((int16_t)reg
->ud
);
649 case BRW_REGISTER_TYPE_F
:
650 reg
->f
= fabsf(reg
->f
);
652 case BRW_REGISTER_TYPE_VF
:
653 reg
->ud
&= ~0x80808080;
655 case BRW_REGISTER_TYPE_UB
:
656 case BRW_REGISTER_TYPE_B
:
657 unreachable("no UB/B immediates");
658 case BRW_REGISTER_TYPE_UQ
:
659 case BRW_REGISTER_TYPE_UD
:
660 case BRW_REGISTER_TYPE_UW
:
661 case BRW_REGISTER_TYPE_UV
:
662 /* Presumably the absolute value modifier on an unsigned source is a
663 * nop, but it would be nice to confirm.
665 assert(!"unimplemented: abs unsigned immediate");
666 case BRW_REGISTER_TYPE_V
:
667 assert(!"unimplemented: abs V immediate");
668 case BRW_REGISTER_TYPE_Q
:
669 assert(!"unimplemented: abs Q immediate");
670 case BRW_REGISTER_TYPE_DF
:
671 case BRW_REGISTER_TYPE_HF
:
672 assert(!"unimplemented: abs DF/HF immediate");
678 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
681 const nir_shader
*shader
,
682 struct brw_stage_prog_data
*stage_prog_data
)
683 : compiler(compiler
),
685 devinfo(compiler
->devinfo
),
687 stage_prog_data(stage_prog_data
),
692 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
693 stage_name
= _mesa_shader_stage_to_string(stage
);
694 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
698 backend_reg::is_zero() const
707 backend_reg::is_one() const
712 return type
== BRW_REGISTER_TYPE_F
718 backend_reg::is_negative_one() const
724 case BRW_REGISTER_TYPE_F
:
726 case BRW_REGISTER_TYPE_D
:
734 backend_reg::is_null() const
736 return file
== HW_REG
&&
737 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
738 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
743 backend_reg::is_accumulator() const
745 return file
== HW_REG
&&
746 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
747 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
751 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
753 return (file
== r
.file
&&
755 reg_offset
>= r
.reg_offset
&&
756 reg_offset
< r
.reg_offset
+ n
);
760 backend_instruction::is_commutative() const
768 case SHADER_OPCODE_MULH
:
771 /* MIN and MAX are commutative. */
772 if (conditional_mod
== BRW_CONDITIONAL_GE
||
773 conditional_mod
== BRW_CONDITIONAL_L
) {
783 backend_instruction::is_3src() const
785 return ::is_3src(opcode
);
789 backend_instruction::is_tex() const
791 return (opcode
== SHADER_OPCODE_TEX
||
792 opcode
== FS_OPCODE_TXB
||
793 opcode
== SHADER_OPCODE_TXD
||
794 opcode
== SHADER_OPCODE_TXF
||
795 opcode
== SHADER_OPCODE_TXF_CMS
||
796 opcode
== SHADER_OPCODE_TXF_CMS_W
||
797 opcode
== SHADER_OPCODE_TXF_UMS
||
798 opcode
== SHADER_OPCODE_TXF_MCS
||
799 opcode
== SHADER_OPCODE_TXL
||
800 opcode
== SHADER_OPCODE_TXS
||
801 opcode
== SHADER_OPCODE_LOD
||
802 opcode
== SHADER_OPCODE_TG4
||
803 opcode
== SHADER_OPCODE_TG4_OFFSET
);
807 backend_instruction::is_math() const
809 return (opcode
== SHADER_OPCODE_RCP
||
810 opcode
== SHADER_OPCODE_RSQ
||
811 opcode
== SHADER_OPCODE_SQRT
||
812 opcode
== SHADER_OPCODE_EXP2
||
813 opcode
== SHADER_OPCODE_LOG2
||
814 opcode
== SHADER_OPCODE_SIN
||
815 opcode
== SHADER_OPCODE_COS
||
816 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
817 opcode
== SHADER_OPCODE_INT_REMAINDER
||
818 opcode
== SHADER_OPCODE_POW
);
822 backend_instruction::is_control_flow() const
826 case BRW_OPCODE_WHILE
:
828 case BRW_OPCODE_ELSE
:
829 case BRW_OPCODE_ENDIF
:
830 case BRW_OPCODE_BREAK
:
831 case BRW_OPCODE_CONTINUE
:
839 backend_instruction::can_do_source_mods() const
842 case BRW_OPCODE_ADDC
:
844 case BRW_OPCODE_BFI1
:
845 case BRW_OPCODE_BFI2
:
846 case BRW_OPCODE_BFREV
:
847 case BRW_OPCODE_CBIT
:
850 case BRW_OPCODE_SUBB
:
858 backend_instruction::can_do_saturate() const
868 case BRW_OPCODE_F16TO32
:
869 case BRW_OPCODE_F32TO16
:
870 case BRW_OPCODE_LINE
:
874 case BRW_OPCODE_MATH
:
877 case SHADER_OPCODE_MULH
:
879 case BRW_OPCODE_RNDD
:
880 case BRW_OPCODE_RNDE
:
881 case BRW_OPCODE_RNDU
:
882 case BRW_OPCODE_RNDZ
:
886 case FS_OPCODE_LINTERP
:
887 case SHADER_OPCODE_COS
:
888 case SHADER_OPCODE_EXP2
:
889 case SHADER_OPCODE_LOG2
:
890 case SHADER_OPCODE_POW
:
891 case SHADER_OPCODE_RCP
:
892 case SHADER_OPCODE_RSQ
:
893 case SHADER_OPCODE_SIN
:
894 case SHADER_OPCODE_SQRT
:
902 backend_instruction::can_do_cmod() const
906 case BRW_OPCODE_ADDC
:
911 case BRW_OPCODE_CMPN
:
916 case BRW_OPCODE_F16TO32
:
917 case BRW_OPCODE_F32TO16
:
919 case BRW_OPCODE_LINE
:
923 case BRW_OPCODE_MACH
:
930 case BRW_OPCODE_RNDD
:
931 case BRW_OPCODE_RNDE
:
932 case BRW_OPCODE_RNDU
:
933 case BRW_OPCODE_RNDZ
:
934 case BRW_OPCODE_SAD2
:
935 case BRW_OPCODE_SADA2
:
938 case BRW_OPCODE_SUBB
:
940 case FS_OPCODE_CINTERP
:
941 case FS_OPCODE_LINTERP
:
949 backend_instruction::reads_accumulator_implicitly() const
953 case BRW_OPCODE_MACH
:
954 case BRW_OPCODE_SADA2
:
962 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
964 return writes_accumulator
||
966 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
967 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
968 opcode
!= FS_OPCODE_CINTERP
)));
972 backend_instruction::has_side_effects() const
975 case SHADER_OPCODE_UNTYPED_ATOMIC
:
976 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
977 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
978 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
979 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
980 case SHADER_OPCODE_TYPED_ATOMIC
:
981 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
982 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
983 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
984 case SHADER_OPCODE_MEMORY_FENCE
:
985 case SHADER_OPCODE_URB_WRITE_SIMD8
:
986 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
987 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
988 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
989 case FS_OPCODE_FB_WRITE
:
990 case SHADER_OPCODE_BARRIER
:
998 backend_instruction::is_volatile() const
1001 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1002 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1003 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1004 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1013 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1016 foreach_inst_in_block (backend_instruction
, i
, block
) {
1026 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1028 for (bblock_t
*block_iter
= start_block
->next();
1029 !block_iter
->link
.is_tail_sentinel();
1030 block_iter
= block_iter
->next()) {
1031 block_iter
->start_ip
+= ip_adjustment
;
1032 block_iter
->end_ip
+= ip_adjustment
;
1037 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1039 if (!this->is_head_sentinel())
1040 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1044 adjust_later_block_ips(block
, 1);
1046 exec_node::insert_after(inst
);
1050 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1052 if (!this->is_tail_sentinel())
1053 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1057 adjust_later_block_ips(block
, 1);
1059 exec_node::insert_before(inst
);
1063 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1065 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1067 unsigned num_inst
= list
->length();
1069 block
->end_ip
+= num_inst
;
1071 adjust_later_block_ips(block
, num_inst
);
1073 exec_node::insert_before(list
);
1077 backend_instruction::remove(bblock_t
*block
)
1079 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1081 adjust_later_block_ips(block
, -1);
1083 if (block
->start_ip
== block
->end_ip
) {
1084 block
->cfg
->remove_block(block
);
1089 exec_node::remove();
1093 backend_shader::dump_instructions()
1095 dump_instructions(NULL
);
1099 backend_shader::dump_instructions(const char *name
)
1101 FILE *file
= stderr
;
1102 if (name
&& geteuid() != 0) {
1103 file
= fopen(name
, "w");
1110 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1111 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1112 fprintf(file
, "%4d: ", ip
++);
1113 dump_instruction(inst
, file
);
1117 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1118 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1119 fprintf(file
, "%4d: ", ip
++);
1120 dump_instruction(inst
, file
);
1124 if (file
!= stderr
) {
1130 backend_shader::calculate_cfg()
1134 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1138 backend_shader::invalidate_cfg()
1140 ralloc_free(this->cfg
);
1145 * Sets up the starting offsets for the groups of binding table entries
1146 * commong to all pipeline stages.
1148 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1149 * unused but also make sure that addition of small offsets to them will
1150 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1153 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1154 const struct brw_device_info
*devinfo
,
1155 const struct gl_shader_program
*shader_prog
,
1156 const struct gl_program
*prog
,
1157 struct brw_stage_prog_data
*stage_prog_data
,
1158 uint32_t next_binding_table_offset
)
1160 const struct gl_shader
*shader
= NULL
;
1161 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1164 shader
= shader_prog
->_LinkedShaders
[stage
];
1166 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1167 next_binding_table_offset
+= num_textures
;
1170 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1171 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1172 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1174 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1175 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1176 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1178 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1179 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1182 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1183 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1184 next_binding_table_offset
++;
1186 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1189 if (prog
->UsesGather
) {
1190 if (devinfo
->gen
>= 8) {
1191 stage_prog_data
->binding_table
.gather_texture_start
=
1192 stage_prog_data
->binding_table
.texture_start
;
1194 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1195 next_binding_table_offset
+= num_textures
;
1198 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1201 if (shader
&& shader
->NumAtomicBuffers
) {
1202 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1203 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1205 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1208 if (shader
&& shader
->NumImages
) {
1209 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1210 next_binding_table_offset
+= shader
->NumImages
;
1212 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1215 /* This may or may not be used depending on how the compile goes. */
1216 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1217 next_binding_table_offset
++;
1219 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1221 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1225 setup_vec4_uniform_value(const gl_constant_value
**params
,
1226 const gl_constant_value
*values
,
1229 static const gl_constant_value zero
= { 0 };
1231 for (unsigned i
= 0; i
< n
; ++i
)
1232 params
[i
] = &values
[i
];
1234 for (unsigned i
= n
; i
< 4; ++i
)
1239 brw_setup_image_uniform_values(gl_shader_stage stage
,
1240 struct brw_stage_prog_data
*stage_prog_data
,
1241 unsigned param_start_index
,
1242 const gl_uniform_storage
*storage
)
1244 const gl_constant_value
**param
=
1245 &stage_prog_data
->param
[param_start_index
];
1247 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1248 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1249 const brw_image_param
*image_param
=
1250 &stage_prog_data
->image_param
[image_idx
];
1252 /* Upload the brw_image_param structure. The order is expected to match
1253 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1255 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1256 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1257 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1258 (const gl_constant_value
*)image_param
->offset
, 2);
1259 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1260 (const gl_constant_value
*)image_param
->size
, 3);
1261 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1262 (const gl_constant_value
*)image_param
->stride
, 4);
1263 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1264 (const gl_constant_value
*)image_param
->tiling
, 3);
1265 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1266 (const gl_constant_value
*)image_param
->swizzling
, 2);
1267 param
+= BRW_IMAGE_PARAM_SIZE
;
1269 brw_mark_surface_used(
1271 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1276 * Decide which set of clip planes should be used when clipping via
1277 * gl_Position or gl_ClipVertex.
1279 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1281 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1282 /* There is currently a GLSL vertex shader, so clip according to GLSL
1283 * rules, which means compare gl_ClipVertex (or gl_Position, if
1284 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1285 * that were stored in EyeUserPlane at the time the clip planes were
1288 return ctx
->Transform
.EyeUserPlane
;
1290 /* Either we are using fixed function or an ARB vertex program. In
1291 * either case the clip planes are going to be compared against
1292 * gl_Position (which is in clip coordinates) so we have to clip using
1293 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1296 return ctx
->Transform
._ClipUserPlane
;