2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
28 #include "glsl/glsl_parser_extras.h"
29 #include "main/shaderobj.h"
30 #include "main/uniforms.h"
31 #include "util/debug.h"
34 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
36 struct brw_context
*brw
= (struct brw_context
*)data
;
41 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
42 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
43 MESA_DEBUG_TYPE_OTHER
,
44 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
49 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
51 struct brw_context
*brw
= (struct brw_context
*)data
;
56 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
58 va_copy(args_copy
, args
);
59 vfprintf(stderr
, fmt
, args_copy
);
63 if (brw
->perf_debug
) {
65 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
66 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
67 MESA_DEBUG_TYPE_PERFORMANCE
,
68 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
74 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
76 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
78 compiler
->devinfo
= devinfo
;
79 compiler
->shader_debug_log
= shader_debug_log_mesa
;
80 compiler
->shader_perf_log
= shader_perf_log_mesa
;
82 brw_fs_alloc_reg_sets(compiler
);
83 brw_vec4_alloc_reg_set(compiler
);
85 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
86 devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
);
87 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
88 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
89 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
90 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
92 nir_shader_compiler_options
*nir_options
=
93 rzalloc(compiler
, nir_shader_compiler_options
);
94 nir_options
->native_integers
= true;
95 /* In order to help allow for better CSE at the NIR level we tell NIR
96 * to split all ffma instructions during opt_algebraic and we then
97 * re-combine them as a later step.
99 nir_options
->lower_ffma
= true;
100 nir_options
->lower_sub
= true;
101 nir_options
->lower_fdiv
= true;
103 /* In the vec4 backend, our dpN instruction replicates its result to all
104 * the components of a vec4. We would like NIR to give us replicated fdot
105 * instructions because it can optimize better for us.
107 * For the FS backend, it should be lowered away by the scalarizing pass so
108 * we should never see fdot anyway.
110 nir_options
->fdot_replicates
= true;
112 /* We want the GLSL compiler to emit code that uses condition codes */
113 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
114 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
115 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
116 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
118 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
119 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
120 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
121 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
122 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
123 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
125 bool is_scalar
= compiler
->scalar_stage
[i
];
127 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
128 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
129 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
131 /* !ARB_gpu_shader5 */
132 if (devinfo
->gen
< 7)
133 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
135 compiler
->glsl_compiler_options
[i
].NirOptions
= nir_options
;
137 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
140 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
141 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;
143 compiler
->glsl_compiler_options
[MESA_SHADER_COMPUTE
]
144 .LowerShaderSharedVariables
= true;
149 extern "C" struct gl_shader
*
150 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
152 struct brw_shader
*shader
;
154 shader
= rzalloc(NULL
, struct brw_shader
);
156 shader
->base
.Type
= type
;
157 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
158 shader
->base
.Name
= name
;
159 _mesa_init_shader(ctx
, &shader
->base
);
162 return &shader
->base
;
166 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
169 assert(surf_index
< BRW_MAX_SURFACES
);
171 prog_data
->binding_table
.size_bytes
=
172 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
176 brw_type_for_base_type(const struct glsl_type
*type
)
178 switch (type
->base_type
) {
179 case GLSL_TYPE_FLOAT
:
180 return BRW_REGISTER_TYPE_F
;
183 case GLSL_TYPE_SUBROUTINE
:
184 return BRW_REGISTER_TYPE_D
;
186 return BRW_REGISTER_TYPE_UD
;
187 case GLSL_TYPE_ARRAY
:
188 return brw_type_for_base_type(type
->fields
.array
);
189 case GLSL_TYPE_STRUCT
:
190 case GLSL_TYPE_SAMPLER
:
191 case GLSL_TYPE_ATOMIC_UINT
:
192 /* These should be overridden with the type of the member when
193 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
194 * way to trip up if we don't.
196 return BRW_REGISTER_TYPE_UD
;
197 case GLSL_TYPE_IMAGE
:
198 return BRW_REGISTER_TYPE_UD
;
200 case GLSL_TYPE_ERROR
:
201 case GLSL_TYPE_INTERFACE
:
202 case GLSL_TYPE_DOUBLE
:
203 case GLSL_TYPE_FUNCTION
:
204 unreachable("not reached");
207 return BRW_REGISTER_TYPE_F
;
210 enum brw_conditional_mod
211 brw_conditional_for_comparison(unsigned int op
)
215 return BRW_CONDITIONAL_L
;
216 case ir_binop_greater
:
217 return BRW_CONDITIONAL_G
;
218 case ir_binop_lequal
:
219 return BRW_CONDITIONAL_LE
;
220 case ir_binop_gequal
:
221 return BRW_CONDITIONAL_GE
;
223 case ir_binop_all_equal
: /* same as equal for scalars */
224 return BRW_CONDITIONAL_Z
;
225 case ir_binop_nequal
:
226 case ir_binop_any_nequal
: /* same as nequal for scalars */
227 return BRW_CONDITIONAL_NZ
;
229 unreachable("not reached: bad operation for comparison");
234 brw_math_function(enum opcode op
)
237 case SHADER_OPCODE_RCP
:
238 return BRW_MATH_FUNCTION_INV
;
239 case SHADER_OPCODE_RSQ
:
240 return BRW_MATH_FUNCTION_RSQ
;
241 case SHADER_OPCODE_SQRT
:
242 return BRW_MATH_FUNCTION_SQRT
;
243 case SHADER_OPCODE_EXP2
:
244 return BRW_MATH_FUNCTION_EXP
;
245 case SHADER_OPCODE_LOG2
:
246 return BRW_MATH_FUNCTION_LOG
;
247 case SHADER_OPCODE_POW
:
248 return BRW_MATH_FUNCTION_POW
;
249 case SHADER_OPCODE_SIN
:
250 return BRW_MATH_FUNCTION_SIN
;
251 case SHADER_OPCODE_COS
:
252 return BRW_MATH_FUNCTION_COS
;
253 case SHADER_OPCODE_INT_QUOTIENT
:
254 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
255 case SHADER_OPCODE_INT_REMAINDER
:
256 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
258 unreachable("not reached: unknown math function");
263 brw_texture_offset(int *offsets
, unsigned num_components
)
265 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
267 /* Combine all three offsets into a single unsigned dword:
269 * bits 11:8 - U Offset (X component)
270 * bits 7:4 - V Offset (Y component)
271 * bits 3:0 - R Offset (Z component)
273 unsigned offset_bits
= 0;
274 for (unsigned i
= 0; i
< num_components
; i
++) {
275 const unsigned shift
= 4 * (2 - i
);
276 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
282 brw_instruction_name(enum opcode op
)
285 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
286 assert(opcode_descs
[op
].name
);
287 return opcode_descs
[op
].name
;
288 case FS_OPCODE_FB_WRITE
:
290 case FS_OPCODE_FB_WRITE_LOGICAL
:
291 return "fb_write_logical";
292 case FS_OPCODE_PACK_STENCIL_REF
:
293 return "pack_stencil_ref";
294 case FS_OPCODE_BLORP_FB_WRITE
:
295 return "blorp_fb_write";
296 case FS_OPCODE_REP_FB_WRITE
:
297 return "rep_fb_write";
299 case SHADER_OPCODE_RCP
:
301 case SHADER_OPCODE_RSQ
:
303 case SHADER_OPCODE_SQRT
:
305 case SHADER_OPCODE_EXP2
:
307 case SHADER_OPCODE_LOG2
:
309 case SHADER_OPCODE_POW
:
311 case SHADER_OPCODE_INT_QUOTIENT
:
313 case SHADER_OPCODE_INT_REMAINDER
:
315 case SHADER_OPCODE_SIN
:
317 case SHADER_OPCODE_COS
:
320 case SHADER_OPCODE_TEX
:
322 case SHADER_OPCODE_TEX_LOGICAL
:
323 return "tex_logical";
324 case SHADER_OPCODE_TXD
:
326 case SHADER_OPCODE_TXD_LOGICAL
:
327 return "txd_logical";
328 case SHADER_OPCODE_TXF
:
330 case SHADER_OPCODE_TXF_LOGICAL
:
331 return "txf_logical";
332 case SHADER_OPCODE_TXL
:
334 case SHADER_OPCODE_TXL_LOGICAL
:
335 return "txl_logical";
336 case SHADER_OPCODE_TXS
:
338 case SHADER_OPCODE_TXS_LOGICAL
:
339 return "txs_logical";
342 case FS_OPCODE_TXB_LOGICAL
:
343 return "txb_logical";
344 case SHADER_OPCODE_TXF_CMS
:
346 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
347 return "txf_cms_logical";
348 case SHADER_OPCODE_TXF_CMS_W
:
350 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
351 return "txf_cms_w_logical";
352 case SHADER_OPCODE_TXF_UMS
:
354 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
355 return "txf_ums_logical";
356 case SHADER_OPCODE_TXF_MCS
:
358 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
359 return "txf_mcs_logical";
360 case SHADER_OPCODE_LOD
:
362 case SHADER_OPCODE_LOD_LOGICAL
:
363 return "lod_logical";
364 case SHADER_OPCODE_TG4
:
366 case SHADER_OPCODE_TG4_LOGICAL
:
367 return "tg4_logical";
368 case SHADER_OPCODE_TG4_OFFSET
:
370 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
371 return "tg4_offset_logical";
372 case SHADER_OPCODE_SAMPLEINFO
:
375 case SHADER_OPCODE_SHADER_TIME_ADD
:
376 return "shader_time_add";
378 case SHADER_OPCODE_UNTYPED_ATOMIC
:
379 return "untyped_atomic";
380 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
381 return "untyped_atomic_logical";
382 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
383 return "untyped_surface_read";
384 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
385 return "untyped_surface_read_logical";
386 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
387 return "untyped_surface_write";
388 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
389 return "untyped_surface_write_logical";
390 case SHADER_OPCODE_TYPED_ATOMIC
:
391 return "typed_atomic";
392 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
393 return "typed_atomic_logical";
394 case SHADER_OPCODE_TYPED_SURFACE_READ
:
395 return "typed_surface_read";
396 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
397 return "typed_surface_read_logical";
398 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
399 return "typed_surface_write";
400 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
401 return "typed_surface_write_logical";
402 case SHADER_OPCODE_MEMORY_FENCE
:
403 return "memory_fence";
405 case SHADER_OPCODE_LOAD_PAYLOAD
:
406 return "load_payload";
408 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
409 return "gen4_scratch_read";
410 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
411 return "gen4_scratch_write";
412 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
413 return "gen7_scratch_read";
414 case SHADER_OPCODE_URB_WRITE_SIMD8
:
415 return "gen8_urb_write_simd8";
416 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
417 return "gen8_urb_write_simd8_per_slot";
418 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
419 return "gen8_urb_write_simd8_masked";
420 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
421 return "gen8_urb_write_simd8_masked_per_slot";
422 case SHADER_OPCODE_URB_READ_SIMD8
:
423 return "urb_read_simd8";
424 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
425 return "urb_read_simd8_per_slot";
427 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
428 return "find_live_channel";
429 case SHADER_OPCODE_BROADCAST
:
432 case VEC4_OPCODE_MOV_BYTES
:
434 case VEC4_OPCODE_PACK_BYTES
:
436 case VEC4_OPCODE_UNPACK_UNIFORM
:
437 return "unpack_uniform";
439 case FS_OPCODE_DDX_COARSE
:
441 case FS_OPCODE_DDX_FINE
:
443 case FS_OPCODE_DDY_COARSE
:
445 case FS_OPCODE_DDY_FINE
:
448 case FS_OPCODE_CINTERP
:
450 case FS_OPCODE_LINTERP
:
453 case FS_OPCODE_PIXEL_X
:
455 case FS_OPCODE_PIXEL_Y
:
458 case FS_OPCODE_GET_BUFFER_SIZE
:
459 return "fs_get_buffer_size";
461 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
462 return "uniform_pull_const";
463 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
464 return "uniform_pull_const_gen7";
465 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
466 return "varying_pull_const";
467 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
468 return "varying_pull_const_gen7";
470 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
471 return "mov_dispatch_to_flags";
472 case FS_OPCODE_DISCARD_JUMP
:
473 return "discard_jump";
475 case FS_OPCODE_SET_SAMPLE_ID
:
476 return "set_sample_id";
477 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
478 return "set_simd4x2_offset";
480 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
481 return "pack_half_2x16_split";
482 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
483 return "unpack_half_2x16_split_x";
484 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
485 return "unpack_half_2x16_split_y";
487 case FS_OPCODE_PLACEHOLDER_HALT
:
488 return "placeholder_halt";
490 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
491 return "interp_centroid";
492 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
493 return "interp_sample";
494 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
495 return "interp_shared_offset";
496 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
497 return "interp_per_slot_offset";
499 case VS_OPCODE_URB_WRITE
:
500 return "vs_urb_write";
501 case VS_OPCODE_PULL_CONSTANT_LOAD
:
502 return "pull_constant_load";
503 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
504 return "pull_constant_load_gen7";
506 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
507 return "set_simd4x2_header_gen9";
509 case VS_OPCODE_GET_BUFFER_SIZE
:
510 return "vs_get_buffer_size";
512 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
513 return "unpack_flags_simd4x2";
515 case GS_OPCODE_URB_WRITE
:
516 return "gs_urb_write";
517 case GS_OPCODE_URB_WRITE_ALLOCATE
:
518 return "gs_urb_write_allocate";
519 case GS_OPCODE_THREAD_END
:
520 return "gs_thread_end";
521 case GS_OPCODE_SET_WRITE_OFFSET
:
522 return "set_write_offset";
523 case GS_OPCODE_SET_VERTEX_COUNT
:
524 return "set_vertex_count";
525 case GS_OPCODE_SET_DWORD_2
:
526 return "set_dword_2";
527 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
528 return "prepare_channel_masks";
529 case GS_OPCODE_SET_CHANNEL_MASKS
:
530 return "set_channel_masks";
531 case GS_OPCODE_GET_INSTANCE_ID
:
532 return "get_instance_id";
533 case GS_OPCODE_FF_SYNC
:
535 case GS_OPCODE_SET_PRIMITIVE_ID
:
536 return "set_primitive_id";
537 case GS_OPCODE_SVB_WRITE
:
538 return "gs_svb_write";
539 case GS_OPCODE_SVB_SET_DST_INDEX
:
540 return "gs_svb_set_dst_index";
541 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
542 return "gs_ff_sync_set_primitives";
543 case CS_OPCODE_CS_TERMINATE
:
544 return "cs_terminate";
545 case SHADER_OPCODE_BARRIER
:
547 case SHADER_OPCODE_MULH
:
549 case SHADER_OPCODE_MOV_INDIRECT
:
550 return "mov_indirect";
553 unreachable("not reached");
557 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
563 } imm
= { reg
->ud
}, sat_imm
= { 0 };
566 case BRW_REGISTER_TYPE_UD
:
567 case BRW_REGISTER_TYPE_D
:
568 case BRW_REGISTER_TYPE_UW
:
569 case BRW_REGISTER_TYPE_W
:
570 case BRW_REGISTER_TYPE_UQ
:
571 case BRW_REGISTER_TYPE_Q
:
574 case BRW_REGISTER_TYPE_F
:
575 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
577 case BRW_REGISTER_TYPE_UB
:
578 case BRW_REGISTER_TYPE_B
:
579 unreachable("no UB/B immediates");
580 case BRW_REGISTER_TYPE_V
:
581 case BRW_REGISTER_TYPE_UV
:
582 case BRW_REGISTER_TYPE_VF
:
583 unreachable("unimplemented: saturate vector immediate");
584 case BRW_REGISTER_TYPE_DF
:
585 case BRW_REGISTER_TYPE_HF
:
586 unreachable("unimplemented: saturate DF/HF immediate");
589 if (imm
.ud
!= sat_imm
.ud
) {
590 reg
->ud
= sat_imm
.ud
;
597 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
600 case BRW_REGISTER_TYPE_D
:
601 case BRW_REGISTER_TYPE_UD
:
604 case BRW_REGISTER_TYPE_W
:
605 case BRW_REGISTER_TYPE_UW
:
606 reg
->d
= -(int16_t)reg
->ud
;
608 case BRW_REGISTER_TYPE_F
:
611 case BRW_REGISTER_TYPE_VF
:
612 reg
->ud
^= 0x80808080;
614 case BRW_REGISTER_TYPE_UB
:
615 case BRW_REGISTER_TYPE_B
:
616 unreachable("no UB/B immediates");
617 case BRW_REGISTER_TYPE_UV
:
618 case BRW_REGISTER_TYPE_V
:
619 assert(!"unimplemented: negate UV/V immediate");
620 case BRW_REGISTER_TYPE_UQ
:
621 case BRW_REGISTER_TYPE_Q
:
622 assert(!"unimplemented: negate UQ/Q immediate");
623 case BRW_REGISTER_TYPE_DF
:
624 case BRW_REGISTER_TYPE_HF
:
625 assert(!"unimplemented: negate DF/HF immediate");
632 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
635 case BRW_REGISTER_TYPE_D
:
636 reg
->d
= abs(reg
->d
);
638 case BRW_REGISTER_TYPE_W
:
639 reg
->d
= abs((int16_t)reg
->ud
);
641 case BRW_REGISTER_TYPE_F
:
642 reg
->f
= fabsf(reg
->f
);
644 case BRW_REGISTER_TYPE_VF
:
645 reg
->ud
&= ~0x80808080;
647 case BRW_REGISTER_TYPE_UB
:
648 case BRW_REGISTER_TYPE_B
:
649 unreachable("no UB/B immediates");
650 case BRW_REGISTER_TYPE_UQ
:
651 case BRW_REGISTER_TYPE_UD
:
652 case BRW_REGISTER_TYPE_UW
:
653 case BRW_REGISTER_TYPE_UV
:
654 /* Presumably the absolute value modifier on an unsigned source is a
655 * nop, but it would be nice to confirm.
657 assert(!"unimplemented: abs unsigned immediate");
658 case BRW_REGISTER_TYPE_V
:
659 assert(!"unimplemented: abs V immediate");
660 case BRW_REGISTER_TYPE_Q
:
661 assert(!"unimplemented: abs Q immediate");
662 case BRW_REGISTER_TYPE_DF
:
663 case BRW_REGISTER_TYPE_HF
:
664 assert(!"unimplemented: abs DF/HF immediate");
670 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
673 const nir_shader
*shader
,
674 struct brw_stage_prog_data
*stage_prog_data
)
675 : compiler(compiler
),
677 devinfo(compiler
->devinfo
),
679 stage_prog_data(stage_prog_data
),
684 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
685 stage_name
= _mesa_shader_stage_to_string(stage
);
686 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
690 backend_reg::equals(const backend_reg
&r
) const
692 return memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
693 reg_offset
== r
.reg_offset
;
697 backend_reg::is_zero() const
706 backend_reg::is_one() const
711 return type
== BRW_REGISTER_TYPE_F
717 backend_reg::is_negative_one() const
723 case BRW_REGISTER_TYPE_F
:
725 case BRW_REGISTER_TYPE_D
:
733 backend_reg::is_null() const
735 return file
== ARF
&& nr
== BRW_ARF_NULL
;
740 backend_reg::is_accumulator() const
742 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
746 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
748 return (file
== r
.file
&&
750 reg_offset
>= r
.reg_offset
&&
751 reg_offset
< r
.reg_offset
+ n
);
755 backend_instruction::is_commutative() const
763 case SHADER_OPCODE_MULH
:
766 /* MIN and MAX are commutative. */
767 if (conditional_mod
== BRW_CONDITIONAL_GE
||
768 conditional_mod
== BRW_CONDITIONAL_L
) {
778 backend_instruction::is_3src() const
780 return ::is_3src(opcode
);
784 backend_instruction::is_tex() const
786 return (opcode
== SHADER_OPCODE_TEX
||
787 opcode
== FS_OPCODE_TXB
||
788 opcode
== SHADER_OPCODE_TXD
||
789 opcode
== SHADER_OPCODE_TXF
||
790 opcode
== SHADER_OPCODE_TXF_CMS
||
791 opcode
== SHADER_OPCODE_TXF_CMS_W
||
792 opcode
== SHADER_OPCODE_TXF_UMS
||
793 opcode
== SHADER_OPCODE_TXF_MCS
||
794 opcode
== SHADER_OPCODE_TXL
||
795 opcode
== SHADER_OPCODE_TXS
||
796 opcode
== SHADER_OPCODE_LOD
||
797 opcode
== SHADER_OPCODE_TG4
||
798 opcode
== SHADER_OPCODE_TG4_OFFSET
);
802 backend_instruction::is_math() const
804 return (opcode
== SHADER_OPCODE_RCP
||
805 opcode
== SHADER_OPCODE_RSQ
||
806 opcode
== SHADER_OPCODE_SQRT
||
807 opcode
== SHADER_OPCODE_EXP2
||
808 opcode
== SHADER_OPCODE_LOG2
||
809 opcode
== SHADER_OPCODE_SIN
||
810 opcode
== SHADER_OPCODE_COS
||
811 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
812 opcode
== SHADER_OPCODE_INT_REMAINDER
||
813 opcode
== SHADER_OPCODE_POW
);
817 backend_instruction::is_control_flow() const
821 case BRW_OPCODE_WHILE
:
823 case BRW_OPCODE_ELSE
:
824 case BRW_OPCODE_ENDIF
:
825 case BRW_OPCODE_BREAK
:
826 case BRW_OPCODE_CONTINUE
:
834 backend_instruction::can_do_source_mods() const
837 case BRW_OPCODE_ADDC
:
839 case BRW_OPCODE_BFI1
:
840 case BRW_OPCODE_BFI2
:
841 case BRW_OPCODE_BFREV
:
842 case BRW_OPCODE_CBIT
:
845 case BRW_OPCODE_SUBB
:
853 backend_instruction::can_do_saturate() const
863 case BRW_OPCODE_F16TO32
:
864 case BRW_OPCODE_F32TO16
:
865 case BRW_OPCODE_LINE
:
869 case BRW_OPCODE_MATH
:
872 case SHADER_OPCODE_MULH
:
874 case BRW_OPCODE_RNDD
:
875 case BRW_OPCODE_RNDE
:
876 case BRW_OPCODE_RNDU
:
877 case BRW_OPCODE_RNDZ
:
881 case FS_OPCODE_LINTERP
:
882 case SHADER_OPCODE_COS
:
883 case SHADER_OPCODE_EXP2
:
884 case SHADER_OPCODE_LOG2
:
885 case SHADER_OPCODE_POW
:
886 case SHADER_OPCODE_RCP
:
887 case SHADER_OPCODE_RSQ
:
888 case SHADER_OPCODE_SIN
:
889 case SHADER_OPCODE_SQRT
:
897 backend_instruction::can_do_cmod() const
901 case BRW_OPCODE_ADDC
:
906 case BRW_OPCODE_CMPN
:
911 case BRW_OPCODE_F16TO32
:
912 case BRW_OPCODE_F32TO16
:
914 case BRW_OPCODE_LINE
:
918 case BRW_OPCODE_MACH
:
925 case BRW_OPCODE_RNDD
:
926 case BRW_OPCODE_RNDE
:
927 case BRW_OPCODE_RNDU
:
928 case BRW_OPCODE_RNDZ
:
929 case BRW_OPCODE_SAD2
:
930 case BRW_OPCODE_SADA2
:
933 case BRW_OPCODE_SUBB
:
935 case FS_OPCODE_CINTERP
:
936 case FS_OPCODE_LINTERP
:
944 backend_instruction::reads_accumulator_implicitly() const
948 case BRW_OPCODE_MACH
:
949 case BRW_OPCODE_SADA2
:
957 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
959 return writes_accumulator
||
961 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
962 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
963 opcode
!= FS_OPCODE_CINTERP
)));
967 backend_instruction::has_side_effects() const
970 case SHADER_OPCODE_UNTYPED_ATOMIC
:
971 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
972 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
973 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
974 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
975 case SHADER_OPCODE_TYPED_ATOMIC
:
976 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
977 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
978 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
979 case SHADER_OPCODE_MEMORY_FENCE
:
980 case SHADER_OPCODE_URB_WRITE_SIMD8
:
981 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
982 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
983 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
984 case FS_OPCODE_FB_WRITE
:
985 case SHADER_OPCODE_BARRIER
:
993 backend_instruction::is_volatile() const
996 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
997 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
998 case SHADER_OPCODE_TYPED_SURFACE_READ
:
999 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1008 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1011 foreach_inst_in_block (backend_instruction
, i
, block
) {
1021 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1023 for (bblock_t
*block_iter
= start_block
->next();
1024 !block_iter
->link
.is_tail_sentinel();
1025 block_iter
= block_iter
->next()) {
1026 block_iter
->start_ip
+= ip_adjustment
;
1027 block_iter
->end_ip
+= ip_adjustment
;
1032 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1034 if (!this->is_head_sentinel())
1035 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1039 adjust_later_block_ips(block
, 1);
1041 exec_node::insert_after(inst
);
1045 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1047 if (!this->is_tail_sentinel())
1048 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1052 adjust_later_block_ips(block
, 1);
1054 exec_node::insert_before(inst
);
1058 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1060 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1062 unsigned num_inst
= list
->length();
1064 block
->end_ip
+= num_inst
;
1066 adjust_later_block_ips(block
, num_inst
);
1068 exec_node::insert_before(list
);
1072 backend_instruction::remove(bblock_t
*block
)
1074 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1076 adjust_later_block_ips(block
, -1);
1078 if (block
->start_ip
== block
->end_ip
) {
1079 block
->cfg
->remove_block(block
);
1084 exec_node::remove();
1088 backend_shader::dump_instructions()
1090 dump_instructions(NULL
);
1094 backend_shader::dump_instructions(const char *name
)
1096 FILE *file
= stderr
;
1097 if (name
&& geteuid() != 0) {
1098 file
= fopen(name
, "w");
1105 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1106 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1107 fprintf(file
, "%4d: ", ip
++);
1108 dump_instruction(inst
, file
);
1112 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1113 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1114 fprintf(file
, "%4d: ", ip
++);
1115 dump_instruction(inst
, file
);
1119 if (file
!= stderr
) {
1125 backend_shader::calculate_cfg()
1129 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1133 backend_shader::invalidate_cfg()
1135 ralloc_free(this->cfg
);
1140 * Sets up the starting offsets for the groups of binding table entries
1141 * commong to all pipeline stages.
1143 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1144 * unused but also make sure that addition of small offsets to them will
1145 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1148 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1149 const struct brw_device_info
*devinfo
,
1150 const struct gl_shader_program
*shader_prog
,
1151 const struct gl_program
*prog
,
1152 struct brw_stage_prog_data
*stage_prog_data
,
1153 uint32_t next_binding_table_offset
)
1155 const struct gl_shader
*shader
= NULL
;
1156 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1159 shader
= shader_prog
->_LinkedShaders
[stage
];
1161 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1162 next_binding_table_offset
+= num_textures
;
1165 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1166 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1167 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1169 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1170 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1171 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1173 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1174 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1177 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1178 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1179 next_binding_table_offset
++;
1181 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1184 if (prog
->UsesGather
) {
1185 if (devinfo
->gen
>= 8) {
1186 stage_prog_data
->binding_table
.gather_texture_start
=
1187 stage_prog_data
->binding_table
.texture_start
;
1189 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1190 next_binding_table_offset
+= num_textures
;
1193 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1196 if (shader
&& shader
->NumAtomicBuffers
) {
1197 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1198 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1200 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1203 if (shader
&& shader
->NumImages
) {
1204 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1205 next_binding_table_offset
+= shader
->NumImages
;
1207 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1210 /* This may or may not be used depending on how the compile goes. */
1211 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1212 next_binding_table_offset
++;
1214 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1216 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1220 setup_vec4_uniform_value(const gl_constant_value
**params
,
1221 const gl_constant_value
*values
,
1224 static const gl_constant_value zero
= { 0 };
1226 for (unsigned i
= 0; i
< n
; ++i
)
1227 params
[i
] = &values
[i
];
1229 for (unsigned i
= n
; i
< 4; ++i
)
1234 brw_setup_image_uniform_values(gl_shader_stage stage
,
1235 struct brw_stage_prog_data
*stage_prog_data
,
1236 unsigned param_start_index
,
1237 const gl_uniform_storage
*storage
)
1239 const gl_constant_value
**param
=
1240 &stage_prog_data
->param
[param_start_index
];
1242 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1243 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1244 const brw_image_param
*image_param
=
1245 &stage_prog_data
->image_param
[image_idx
];
1247 /* Upload the brw_image_param structure. The order is expected to match
1248 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1250 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1251 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1252 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1253 (const gl_constant_value
*)image_param
->offset
, 2);
1254 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1255 (const gl_constant_value
*)image_param
->size
, 3);
1256 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1257 (const gl_constant_value
*)image_param
->stride
, 4);
1258 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1259 (const gl_constant_value
*)image_param
->tiling
, 3);
1260 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1261 (const gl_constant_value
*)image_param
->swizzling
, 2);
1262 param
+= BRW_IMAGE_PARAM_SIZE
;
1264 brw_mark_surface_used(
1266 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1271 * Decide which set of clip planes should be used when clipping via
1272 * gl_Position or gl_ClipVertex.
1274 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1276 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1277 /* There is currently a GLSL vertex shader, so clip according to GLSL
1278 * rules, which means compare gl_ClipVertex (or gl_Position, if
1279 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1280 * that were stored in EyeUserPlane at the time the clip planes were
1283 return ctx
->Transform
.EyeUserPlane
;
1285 /* Either we are using fixed function or an ARB vertex program. In
1286 * either case the clip planes are going to be compared against
1287 * gl_Position (which is in clip coordinates) so we have to clip using
1288 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1291 return ctx
->Transform
._ClipUserPlane
;