src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32
  33 extern "C" struct gl_shader *
  34 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  35 {
  36    struct brw_shader *shader;
  37
  38    shader = rzalloc(NULL, struct brw_shader);
  39    if (shader) {
  40       shader->base.Type = type;
  41       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  42       shader->base.Name = name;
  43       _mesa_init_shader(ctx, &shader->base);
  44    }
  45
  46    return &shader->base;
  47 }
  48
  49 extern "C" void
  50 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  51                       unsigned surf_index)
  52 {
  53    assert(surf_index < BRW_MAX_SURFACES);
  54
  55    prog_data->binding_table.size_bytes =
  56       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  57 }
  58
  59 enum brw_reg_type
  60 brw_type_for_base_type(const struct glsl_type *type)
  61 {
  62    switch (type->base_type) {
  63    case GLSL_TYPE_FLOAT:
  64       return BRW_REGISTER_TYPE_F;
  65    case GLSL_TYPE_INT:
  66    case GLSL_TYPE_BOOL:
  67    case GLSL_TYPE_SUBROUTINE:
  68       return BRW_REGISTER_TYPE_D;
  69    case GLSL_TYPE_UINT:
  70       return BRW_REGISTER_TYPE_UD;
  71    case GLSL_TYPE_ARRAY:
  72       return brw_type_for_base_type(type->fields.array);
  73    case GLSL_TYPE_STRUCT:
  74    case GLSL_TYPE_SAMPLER:
  75    case GLSL_TYPE_ATOMIC_UINT:
  76       /* These should be overridden with the type of the member when
  77        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  78        * way to trip up if we don't.
  79        */
  80       return BRW_REGISTER_TYPE_UD;
  81    case GLSL_TYPE_IMAGE:
  82       return BRW_REGISTER_TYPE_UD;
  83    case GLSL_TYPE_VOID:
  84    case GLSL_TYPE_ERROR:
  85    case GLSL_TYPE_INTERFACE:
  86    case GLSL_TYPE_DOUBLE:
  87    case GLSL_TYPE_FUNCTION:
  88       unreachable("not reached");
  89    }
  90
  91    return BRW_REGISTER_TYPE_F;
  92 }
  93
  94 enum brw_conditional_mod
  95 brw_conditional_for_comparison(unsigned int op)
  96 {
  97    switch (op) {
  98    case ir_binop_less:
  99       return BRW_CONDITIONAL_L;
 100    case ir_binop_greater:
 101       return BRW_CONDITIONAL_G;
 102    case ir_binop_lequal:
 103       return BRW_CONDITIONAL_LE;
 104    case ir_binop_gequal:
 105       return BRW_CONDITIONAL_GE;
 106    case ir_binop_equal:
 107    case ir_binop_all_equal: /* same as equal for scalars */
 108       return BRW_CONDITIONAL_Z;
 109    case ir_binop_nequal:
 110    case ir_binop_any_nequal: /* same as nequal for scalars */
 111       return BRW_CONDITIONAL_NZ;
 112    default:
 113       unreachable("not reached: bad operation for comparison");
 114    }
 115 }
 116
 117 uint32_t
 118 brw_math_function(enum opcode op)
 119 {
 120    switch (op) {
 121    case SHADER_OPCODE_RCP:
 122       return BRW_MATH_FUNCTION_INV;
 123    case SHADER_OPCODE_RSQ:
 124       return BRW_MATH_FUNCTION_RSQ;
 125    case SHADER_OPCODE_SQRT:
 126       return BRW_MATH_FUNCTION_SQRT;
 127    case SHADER_OPCODE_EXP2:
 128       return BRW_MATH_FUNCTION_EXP;
 129    case SHADER_OPCODE_LOG2:
 130       return BRW_MATH_FUNCTION_LOG;
 131    case SHADER_OPCODE_POW:
 132       return BRW_MATH_FUNCTION_POW;
 133    case SHADER_OPCODE_SIN:
 134       return BRW_MATH_FUNCTION_SIN;
 135    case SHADER_OPCODE_COS:
 136       return BRW_MATH_FUNCTION_COS;
 137    case SHADER_OPCODE_INT_QUOTIENT:
 138       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 139    case SHADER_OPCODE_INT_REMAINDER:
 140       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 141    default:
 142       unreachable("not reached: unknown math function");
 143    }
 144 }
 145
 146 uint32_t
 147 brw_texture_offset(int *offsets, unsigned num_components)
 148 {
 149    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 150
 151    /* Combine all three offsets into a single unsigned dword:
 152     *
 153     *    bits 11:8 - U Offset (X component)
 154     *    bits  7:4 - V Offset (Y component)
 155     *    bits  3:0 - R Offset (Z component)
 156     */
 157    unsigned offset_bits = 0;
 158    for (unsigned i = 0; i < num_components; i++) {
 159       const unsigned shift = 4 * (2 - i);
 160       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 161    }
 162    return offset_bits;
 163 }
 164
 165 const char *
 166 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
 167 {
 168    switch (op) {
 169    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 170       assert(opcode_descs[op].name);
 171       return opcode_descs[op].name;
 172    case FS_OPCODE_FB_WRITE:
 173       return "fb_write";
 174    case FS_OPCODE_FB_WRITE_LOGICAL:
 175       return "fb_write_logical";
 176    case FS_OPCODE_PACK_STENCIL_REF:
 177       return "pack_stencil_ref";
 178    case FS_OPCODE_BLORP_FB_WRITE:
 179       return "blorp_fb_write";
 180    case FS_OPCODE_REP_FB_WRITE:
 181       return "rep_fb_write";
 182
 183    case SHADER_OPCODE_RCP:
 184       return "rcp";
 185    case SHADER_OPCODE_RSQ:
 186       return "rsq";
 187    case SHADER_OPCODE_SQRT:
 188       return "sqrt";
 189    case SHADER_OPCODE_EXP2:
 190       return "exp2";
 191    case SHADER_OPCODE_LOG2:
 192       return "log2";
 193    case SHADER_OPCODE_POW:
 194       return "pow";
 195    case SHADER_OPCODE_INT_QUOTIENT:
 196       return "int_quot";
 197    case SHADER_OPCODE_INT_REMAINDER:
 198       return "int_rem";
 199    case SHADER_OPCODE_SIN:
 200       return "sin";
 201    case SHADER_OPCODE_COS:
 202       return "cos";
 203
 204    case SHADER_OPCODE_TEX:
 205       return "tex";
 206    case SHADER_OPCODE_TEX_LOGICAL:
 207       return "tex_logical";
 208    case SHADER_OPCODE_TXD:
 209       return "txd";
 210    case SHADER_OPCODE_TXD_LOGICAL:
 211       return "txd_logical";
 212    case SHADER_OPCODE_TXF:
 213       return "txf";
 214    case SHADER_OPCODE_TXF_LOGICAL:
 215       return "txf_logical";
 216    case SHADER_OPCODE_TXL:
 217       return "txl";
 218    case SHADER_OPCODE_TXL_LOGICAL:
 219       return "txl_logical";
 220    case SHADER_OPCODE_TXS:
 221       return "txs";
 222    case SHADER_OPCODE_TXS_LOGICAL:
 223       return "txs_logical";
 224    case FS_OPCODE_TXB:
 225       return "txb";
 226    case FS_OPCODE_TXB_LOGICAL:
 227       return "txb_logical";
 228    case SHADER_OPCODE_TXF_CMS:
 229       return "txf_cms";
 230    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 231       return "txf_cms_logical";
 232    case SHADER_OPCODE_TXF_CMS_W:
 233       return "txf_cms_w";
 234    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 235       return "txf_cms_w_logical";
 236    case SHADER_OPCODE_TXF_UMS:
 237       return "txf_ums";
 238    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 239       return "txf_ums_logical";
 240    case SHADER_OPCODE_TXF_MCS:
 241       return "txf_mcs";
 242    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 243       return "txf_mcs_logical";
 244    case SHADER_OPCODE_LOD:
 245       return "lod";
 246    case SHADER_OPCODE_LOD_LOGICAL:
 247       return "lod_logical";
 248    case SHADER_OPCODE_TG4:
 249       return "tg4";
 250    case SHADER_OPCODE_TG4_LOGICAL:
 251       return "tg4_logical";
 252    case SHADER_OPCODE_TG4_OFFSET:
 253       return "tg4_offset";
 254    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 255       return "tg4_offset_logical";
 256    case SHADER_OPCODE_SAMPLEINFO:
 257       return "sampleinfo";
 258
 259    case SHADER_OPCODE_SHADER_TIME_ADD:
 260       return "shader_time_add";
 261
 262    case SHADER_OPCODE_UNTYPED_ATOMIC:
 263       return "untyped_atomic";
 264    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 265       return "untyped_atomic_logical";
 266    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 267       return "untyped_surface_read";
 268    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 269       return "untyped_surface_read_logical";
 270    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 271       return "untyped_surface_write";
 272    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 273       return "untyped_surface_write_logical";
 274    case SHADER_OPCODE_TYPED_ATOMIC:
 275       return "typed_atomic";
 276    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 277       return "typed_atomic_logical";
 278    case SHADER_OPCODE_TYPED_SURFACE_READ:
 279       return "typed_surface_read";
 280    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 281       return "typed_surface_read_logical";
 282    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 283       return "typed_surface_write";
 284    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 285       return "typed_surface_write_logical";
 286    case SHADER_OPCODE_MEMORY_FENCE:
 287       return "memory_fence";
 288
 289    case SHADER_OPCODE_LOAD_PAYLOAD:
 290       return "load_payload";
 291
 292    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 293       return "gen4_scratch_read";
 294    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 295       return "gen4_scratch_write";
 296    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 297       return "gen7_scratch_read";
 298    case SHADER_OPCODE_URB_WRITE_SIMD8:
 299       return "gen8_urb_write_simd8";
 300    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 301       return "gen8_urb_write_simd8_per_slot";
 302    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 303       return "gen8_urb_write_simd8_masked";
 304    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 305       return "gen8_urb_write_simd8_masked_per_slot";
 306    case SHADER_OPCODE_URB_READ_SIMD8:
 307       return "urb_read_simd8";
 308    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 309       return "urb_read_simd8_per_slot";
 310
 311    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 312       return "find_live_channel";
 313    case SHADER_OPCODE_BROADCAST:
 314       return "broadcast";
 315
 316    case SHADER_OPCODE_EXTRACT_BYTE:
 317       return "extract_byte";
 318    case SHADER_OPCODE_EXTRACT_WORD:
 319       return "extract_word";
 320    case VEC4_OPCODE_MOV_BYTES:
 321       return "mov_bytes";
 322    case VEC4_OPCODE_PACK_BYTES:
 323       return "pack_bytes";
 324    case VEC4_OPCODE_UNPACK_UNIFORM:
 325       return "unpack_uniform";
 326
 327    case FS_OPCODE_DDX_COARSE:
 328       return "ddx_coarse";
 329    case FS_OPCODE_DDX_FINE:
 330       return "ddx_fine";
 331    case FS_OPCODE_DDY_COARSE:
 332       return "ddy_coarse";
 333    case FS_OPCODE_DDY_FINE:
 334       return "ddy_fine";
 335
 336    case FS_OPCODE_CINTERP:
 337       return "cinterp";
 338    case FS_OPCODE_LINTERP:
 339       return "linterp";
 340
 341    case FS_OPCODE_PIXEL_X:
 342       return "pixel_x";
 343    case FS_OPCODE_PIXEL_Y:
 344       return "pixel_y";
 345
 346    case FS_OPCODE_GET_BUFFER_SIZE:
 347       return "fs_get_buffer_size";
 348
 349    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 350       return "uniform_pull_const";
 351    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 352       return "uniform_pull_const_gen7";
 353    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 354       return "varying_pull_const";
 355    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 356       return "varying_pull_const_gen7";
 357
 358    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 359       return "mov_dispatch_to_flags";
 360    case FS_OPCODE_DISCARD_JUMP:
 361       return "discard_jump";
 362
 363    case FS_OPCODE_SET_SAMPLE_ID:
 364       return "set_sample_id";
 365    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 366       return "set_simd4x2_offset";
 367
 368    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 369       return "pack_half_2x16_split";
 370    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 371       return "unpack_half_2x16_split_x";
 372    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 373       return "unpack_half_2x16_split_y";
 374
 375    case FS_OPCODE_PLACEHOLDER_HALT:
 376       return "placeholder_halt";
 377
 378    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 379       return "interp_centroid";
 380    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 381       return "interp_sample";
 382    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 383       return "interp_shared_offset";
 384    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 385       return "interp_per_slot_offset";
 386
 387    case VS_OPCODE_URB_WRITE:
 388       return "vs_urb_write";
 389    case VS_OPCODE_PULL_CONSTANT_LOAD:
 390       return "pull_constant_load";
 391    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 392       return "pull_constant_load_gen7";
 393
 394    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 395       return "set_simd4x2_header_gen9";
 396
 397    case VS_OPCODE_GET_BUFFER_SIZE:
 398       return "vs_get_buffer_size";
 399
 400    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 401       return "unpack_flags_simd4x2";
 402
 403    case GS_OPCODE_URB_WRITE:
 404       return "gs_urb_write";
 405    case GS_OPCODE_URB_WRITE_ALLOCATE:
 406       return "gs_urb_write_allocate";
 407    case GS_OPCODE_THREAD_END:
 408       return "gs_thread_end";
 409    case GS_OPCODE_SET_WRITE_OFFSET:
 410       return "set_write_offset";
 411    case GS_OPCODE_SET_VERTEX_COUNT:
 412       return "set_vertex_count";
 413    case GS_OPCODE_SET_DWORD_2:
 414       return "set_dword_2";
 415    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 416       return "prepare_channel_masks";
 417    case GS_OPCODE_SET_CHANNEL_MASKS:
 418       return "set_channel_masks";
 419    case GS_OPCODE_GET_INSTANCE_ID:
 420       return "get_instance_id";
 421    case GS_OPCODE_FF_SYNC:
 422       return "ff_sync";
 423    case GS_OPCODE_SET_PRIMITIVE_ID:
 424       return "set_primitive_id";
 425    case GS_OPCODE_SVB_WRITE:
 426       return "gs_svb_write";
 427    case GS_OPCODE_SVB_SET_DST_INDEX:
 428       return "gs_svb_set_dst_index";
 429    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 430       return "gs_ff_sync_set_primitives";
 431    case CS_OPCODE_CS_TERMINATE:
 432       return "cs_terminate";
 433    case SHADER_OPCODE_BARRIER:
 434       return "barrier";
 435    case SHADER_OPCODE_MULH:
 436       return "mulh";
 437    case SHADER_OPCODE_MOV_INDIRECT:
 438       return "mov_indirect";
 439
 440    case VEC4_OPCODE_URB_READ:
 441       return "urb_read";
 442    case TCS_OPCODE_GET_INSTANCE_ID:
 443       return "tcs_get_instance_id";
 444    case TCS_OPCODE_URB_WRITE:
 445       return "tcs_urb_write";
 446    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 447       return "tcs_set_input_urb_offsets";
 448    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 449       return "tcs_set_output_urb_offsets";
 450    case TCS_OPCODE_GET_PRIMITIVE_ID:
 451       return "tcs_get_primitive_id";
 452    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 453       return "tcs_create_barrier_header";
 454    case TCS_OPCODE_SRC0_010_IS_ZERO:
 455       return "tcs_src0<0,1,0>_is_zero";
 456    case TCS_OPCODE_RELEASE_INPUT:
 457       return "tcs_release_input";
 458    case TCS_OPCODE_THREAD_END:
 459       return "tcs_thread_end";
 460    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 461       return "tes_create_input_read_header";
 462    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 463       return "tes_add_indirect_urb_offset";
 464    case TES_OPCODE_GET_PRIMITIVE_ID:
 465       return "tes_get_primitive_id";
 466    }
 467
 468    unreachable("not reached");
 469 }
 470
 471 bool
 472 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 473 {
 474    union {
 475       unsigned ud;
 476       int d;
 477       float f;
 478    } imm = { reg->ud }, sat_imm = { 0 };
 479
 480    switch (type) {
 481    case BRW_REGISTER_TYPE_UD:
 482    case BRW_REGISTER_TYPE_D:
 483    case BRW_REGISTER_TYPE_UW:
 484    case BRW_REGISTER_TYPE_W:
 485    case BRW_REGISTER_TYPE_UQ:
 486    case BRW_REGISTER_TYPE_Q:
 487       /* Nothing to do. */
 488       return false;
 489    case BRW_REGISTER_TYPE_F:
 490       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 491       break;
 492    case BRW_REGISTER_TYPE_UB:
 493    case BRW_REGISTER_TYPE_B:
 494       unreachable("no UB/B immediates");
 495    case BRW_REGISTER_TYPE_V:
 496    case BRW_REGISTER_TYPE_UV:
 497    case BRW_REGISTER_TYPE_VF:
 498       unreachable("unimplemented: saturate vector immediate");
 499    case BRW_REGISTER_TYPE_DF:
 500    case BRW_REGISTER_TYPE_HF:
 501       unreachable("unimplemented: saturate DF/HF immediate");
 502    }
 503
 504    if (imm.ud != sat_imm.ud) {
 505       reg->ud = sat_imm.ud;
 506       return true;
 507    }
 508    return false;
 509 }
 510
 511 bool
 512 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 513 {
 514    switch (type) {
 515    case BRW_REGISTER_TYPE_D:
 516    case BRW_REGISTER_TYPE_UD:
 517       reg->d = -reg->d;
 518       return true;
 519    case BRW_REGISTER_TYPE_W:
 520    case BRW_REGISTER_TYPE_UW:
 521       reg->d = -(int16_t)reg->ud;
 522       return true;
 523    case BRW_REGISTER_TYPE_F:
 524       reg->f = -reg->f;
 525       return true;
 526    case BRW_REGISTER_TYPE_VF:
 527       reg->ud ^= 0x80808080;
 528       return true;
 529    case BRW_REGISTER_TYPE_UB:
 530    case BRW_REGISTER_TYPE_B:
 531       unreachable("no UB/B immediates");
 532    case BRW_REGISTER_TYPE_UV:
 533    case BRW_REGISTER_TYPE_V:
 534       assert(!"unimplemented: negate UV/V immediate");
 535    case BRW_REGISTER_TYPE_UQ:
 536    case BRW_REGISTER_TYPE_Q:
 537       assert(!"unimplemented: negate UQ/Q immediate");
 538    case BRW_REGISTER_TYPE_DF:
 539    case BRW_REGISTER_TYPE_HF:
 540       assert(!"unimplemented: negate DF/HF immediate");
 541    }
 542
 543    return false;
 544 }
 545
 546 bool
 547 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 548 {
 549    switch (type) {
 550    case BRW_REGISTER_TYPE_D:
 551       reg->d = abs(reg->d);
 552       return true;
 553    case BRW_REGISTER_TYPE_W:
 554       reg->d = abs((int16_t)reg->ud);
 555       return true;
 556    case BRW_REGISTER_TYPE_F:
 557       reg->f = fabsf(reg->f);
 558       return true;
 559    case BRW_REGISTER_TYPE_VF:
 560       reg->ud &= ~0x80808080;
 561       return true;
 562    case BRW_REGISTER_TYPE_UB:
 563    case BRW_REGISTER_TYPE_B:
 564       unreachable("no UB/B immediates");
 565    case BRW_REGISTER_TYPE_UQ:
 566    case BRW_REGISTER_TYPE_UD:
 567    case BRW_REGISTER_TYPE_UW:
 568    case BRW_REGISTER_TYPE_UV:
 569       /* Presumably the absolute value modifier on an unsigned source is a
 570        * nop, but it would be nice to confirm.
 571        */
 572       assert(!"unimplemented: abs unsigned immediate");
 573    case BRW_REGISTER_TYPE_V:
 574       assert(!"unimplemented: abs V immediate");
 575    case BRW_REGISTER_TYPE_Q:
 576       assert(!"unimplemented: abs Q immediate");
 577    case BRW_REGISTER_TYPE_DF:
 578    case BRW_REGISTER_TYPE_HF:
 579       assert(!"unimplemented: abs DF/HF immediate");
 580    }
 581
 582    return false;
 583 }
 584
 585 unsigned
 586 tesslevel_outer_components(GLenum tes_primitive_mode)
 587 {
 588    switch (tes_primitive_mode) {
 589    case GL_QUADS:
 590       return 4;
 591    case GL_TRIANGLES:
 592       return 3;
 593    case GL_ISOLINES:
 594       return 2;
 595    default:
 596       unreachable("Bogus tessellation domain");
 597    }
 598    return 0;
 599 }
 600
 601 unsigned
 602 tesslevel_inner_components(GLenum tes_primitive_mode)
 603 {
 604    switch (tes_primitive_mode) {
 605    case GL_QUADS:
 606       return 2;
 607    case GL_TRIANGLES:
 608       return 1;
 609    case GL_ISOLINES:
 610       return 0;
 611    default:
 612       unreachable("Bogus tessellation domain");
 613    }
 614    return 0;
 615 }
 616
 617 /**
 618  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 619  * that's stored backwards, i.e. .wzyx.
 620  */
 621 unsigned
 622 writemask_for_backwards_vector(unsigned mask)
 623 {
 624    unsigned new_mask = 0;
 625
 626    for (int i = 0; i < 4; i++)
 627       new_mask |= ((mask >> i) & 1) << (3 - i);
 628
 629    return new_mask;
 630 }
 631
 632 backend_shader::backend_shader(const struct brw_compiler *compiler,
 633                                void *log_data,
 634                                void *mem_ctx,
 635                                const nir_shader *shader,
 636                                struct brw_stage_prog_data *stage_prog_data)
 637    : compiler(compiler),
 638      log_data(log_data),
 639      devinfo(compiler->devinfo),
 640      nir(shader),
 641      stage_prog_data(stage_prog_data),
 642      mem_ctx(mem_ctx),
 643      cfg(NULL),
 644      stage(shader->stage)
 645 {
 646    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 647    stage_name = _mesa_shader_stage_to_string(stage);
 648    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 649 }
 650
 651 bool
 652 backend_reg::equals(const backend_reg &r) const
 653 {
 654    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 655           reg_offset == r.reg_offset;
 656 }
 657
 658 bool
 659 backend_reg::is_zero() const
 660 {
 661    if (file != IMM)
 662       return false;
 663
 664    return d == 0;
 665 }
 666
 667 bool
 668 backend_reg::is_one() const
 669 {
 670    if (file != IMM)
 671       return false;
 672
 673    return type == BRW_REGISTER_TYPE_F
 674           ? f == 1.0
 675           : d == 1;
 676 }
 677
 678 bool
 679 backend_reg::is_negative_one() const
 680 {
 681    if (file != IMM)
 682       return false;
 683
 684    switch (type) {
 685    case BRW_REGISTER_TYPE_F:
 686       return f == -1.0;
 687    case BRW_REGISTER_TYPE_D:
 688       return d == -1;
 689    default:
 690       return false;
 691    }
 692 }
 693
 694 bool
 695 backend_reg::is_null() const
 696 {
 697    return file == ARF && nr == BRW_ARF_NULL;
 698 }
 699
 700
 701 bool
 702 backend_reg::is_accumulator() const
 703 {
 704    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 705 }
 706
 707 bool
 708 backend_reg::in_range(const backend_reg &r, unsigned n) const
 709 {
 710    return (file == r.file &&
 711            nr == r.nr &&
 712            reg_offset >= r.reg_offset &&
 713            reg_offset < r.reg_offset + n);
 714 }
 715
 716 bool
 717 backend_instruction::is_commutative() const
 718 {
 719    switch (opcode) {
 720    case BRW_OPCODE_AND:
 721    case BRW_OPCODE_OR:
 722    case BRW_OPCODE_XOR:
 723    case BRW_OPCODE_ADD:
 724    case BRW_OPCODE_MUL:
 725    case SHADER_OPCODE_MULH:
 726       return true;
 727    case BRW_OPCODE_SEL:
 728       /* MIN and MAX are commutative. */
 729       if (conditional_mod == BRW_CONDITIONAL_GE ||
 730           conditional_mod == BRW_CONDITIONAL_L) {
 731          return true;
 732       }
 733       /* fallthrough */
 734    default:
 735       return false;
 736    }
 737 }
 738
 739 bool
 740 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
 741 {
 742    return ::is_3src(devinfo, opcode);
 743 }
 744
 745 bool
 746 backend_instruction::is_tex() const
 747 {
 748    return (opcode == SHADER_OPCODE_TEX ||
 749            opcode == FS_OPCODE_TXB ||
 750            opcode == SHADER_OPCODE_TXD ||
 751            opcode == SHADER_OPCODE_TXF ||
 752            opcode == SHADER_OPCODE_TXF_CMS ||
 753            opcode == SHADER_OPCODE_TXF_CMS_W ||
 754            opcode == SHADER_OPCODE_TXF_UMS ||
 755            opcode == SHADER_OPCODE_TXF_MCS ||
 756            opcode == SHADER_OPCODE_TXL ||
 757            opcode == SHADER_OPCODE_TXS ||
 758            opcode == SHADER_OPCODE_LOD ||
 759            opcode == SHADER_OPCODE_TG4 ||
 760            opcode == SHADER_OPCODE_TG4_OFFSET ||
 761            opcode == SHADER_OPCODE_SAMPLEINFO);
 762 }
 763
 764 bool
 765 backend_instruction::is_math() const
 766 {
 767    return (opcode == SHADER_OPCODE_RCP ||
 768            opcode == SHADER_OPCODE_RSQ ||
 769            opcode == SHADER_OPCODE_SQRT ||
 770            opcode == SHADER_OPCODE_EXP2 ||
 771            opcode == SHADER_OPCODE_LOG2 ||
 772            opcode == SHADER_OPCODE_SIN ||
 773            opcode == SHADER_OPCODE_COS ||
 774            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 775            opcode == SHADER_OPCODE_INT_REMAINDER ||
 776            opcode == SHADER_OPCODE_POW);
 777 }
 778
 779 bool
 780 backend_instruction::is_control_flow() const
 781 {
 782    switch (opcode) {
 783    case BRW_OPCODE_DO:
 784    case BRW_OPCODE_WHILE:
 785    case BRW_OPCODE_IF:
 786    case BRW_OPCODE_ELSE:
 787    case BRW_OPCODE_ENDIF:
 788    case BRW_OPCODE_BREAK:
 789    case BRW_OPCODE_CONTINUE:
 790       return true;
 791    default:
 792       return false;
 793    }
 794 }
 795
 796 bool
 797 backend_instruction::can_do_source_mods() const
 798 {
 799    switch (opcode) {
 800    case BRW_OPCODE_ADDC:
 801    case BRW_OPCODE_BFE:
 802    case BRW_OPCODE_BFI1:
 803    case BRW_OPCODE_BFI2:
 804    case BRW_OPCODE_BFREV:
 805    case BRW_OPCODE_CBIT:
 806    case BRW_OPCODE_FBH:
 807    case BRW_OPCODE_FBL:
 808    case BRW_OPCODE_SUBB:
 809       return false;
 810    default:
 811       return true;
 812    }
 813 }
 814
 815 bool
 816 backend_instruction::can_do_saturate() const
 817 {
 818    switch (opcode) {
 819    case BRW_OPCODE_ADD:
 820    case BRW_OPCODE_ASR:
 821    case BRW_OPCODE_AVG:
 822    case BRW_OPCODE_DP2:
 823    case BRW_OPCODE_DP3:
 824    case BRW_OPCODE_DP4:
 825    case BRW_OPCODE_DPH:
 826    case BRW_OPCODE_F16TO32:
 827    case BRW_OPCODE_F32TO16:
 828    case BRW_OPCODE_LINE:
 829    case BRW_OPCODE_LRP:
 830    case BRW_OPCODE_MAC:
 831    case BRW_OPCODE_MAD:
 832    case BRW_OPCODE_MATH:
 833    case BRW_OPCODE_MOV:
 834    case BRW_OPCODE_MUL:
 835    case SHADER_OPCODE_MULH:
 836    case BRW_OPCODE_PLN:
 837    case BRW_OPCODE_RNDD:
 838    case BRW_OPCODE_RNDE:
 839    case BRW_OPCODE_RNDU:
 840    case BRW_OPCODE_RNDZ:
 841    case BRW_OPCODE_SEL:
 842    case BRW_OPCODE_SHL:
 843    case BRW_OPCODE_SHR:
 844    case FS_OPCODE_LINTERP:
 845    case SHADER_OPCODE_COS:
 846    case SHADER_OPCODE_EXP2:
 847    case SHADER_OPCODE_LOG2:
 848    case SHADER_OPCODE_POW:
 849    case SHADER_OPCODE_RCP:
 850    case SHADER_OPCODE_RSQ:
 851    case SHADER_OPCODE_SIN:
 852    case SHADER_OPCODE_SQRT:
 853       return true;
 854    default:
 855       return false;
 856    }
 857 }
 858
 859 bool
 860 backend_instruction::can_do_cmod() const
 861 {
 862    switch (opcode) {
 863    case BRW_OPCODE_ADD:
 864    case BRW_OPCODE_ADDC:
 865    case BRW_OPCODE_AND:
 866    case BRW_OPCODE_ASR:
 867    case BRW_OPCODE_AVG:
 868    case BRW_OPCODE_CMP:
 869    case BRW_OPCODE_CMPN:
 870    case BRW_OPCODE_DP2:
 871    case BRW_OPCODE_DP3:
 872    case BRW_OPCODE_DP4:
 873    case BRW_OPCODE_DPH:
 874    case BRW_OPCODE_F16TO32:
 875    case BRW_OPCODE_F32TO16:
 876    case BRW_OPCODE_FRC:
 877    case BRW_OPCODE_LINE:
 878    case BRW_OPCODE_LRP:
 879    case BRW_OPCODE_LZD:
 880    case BRW_OPCODE_MAC:
 881    case BRW_OPCODE_MACH:
 882    case BRW_OPCODE_MAD:
 883    case BRW_OPCODE_MOV:
 884    case BRW_OPCODE_MUL:
 885    case BRW_OPCODE_NOT:
 886    case BRW_OPCODE_OR:
 887    case BRW_OPCODE_PLN:
 888    case BRW_OPCODE_RNDD:
 889    case BRW_OPCODE_RNDE:
 890    case BRW_OPCODE_RNDU:
 891    case BRW_OPCODE_RNDZ:
 892    case BRW_OPCODE_SAD2:
 893    case BRW_OPCODE_SADA2:
 894    case BRW_OPCODE_SHL:
 895    case BRW_OPCODE_SHR:
 896    case BRW_OPCODE_SUBB:
 897    case BRW_OPCODE_XOR:
 898    case FS_OPCODE_CINTERP:
 899    case FS_OPCODE_LINTERP:
 900       return true;
 901    default:
 902       return false;
 903    }
 904 }
 905
 906 bool
 907 backend_instruction::reads_accumulator_implicitly() const
 908 {
 909    switch (opcode) {
 910    case BRW_OPCODE_MAC:
 911    case BRW_OPCODE_MACH:
 912    case BRW_OPCODE_SADA2:
 913       return true;
 914    default:
 915       return false;
 916    }
 917 }
 918
 919 bool
 920 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 921 {
 922    return writes_accumulator ||
 923           (devinfo->gen < 6 &&
 924            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 925             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 926              opcode != FS_OPCODE_CINTERP)));
 927 }
 928
 929 bool
 930 backend_instruction::has_side_effects() const
 931 {
 932    switch (opcode) {
 933    case SHADER_OPCODE_UNTYPED_ATOMIC:
 934    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 935    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 936    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 937    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 938    case SHADER_OPCODE_TYPED_ATOMIC:
 939    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 940    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 941    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 942    case SHADER_OPCODE_MEMORY_FENCE:
 943    case SHADER_OPCODE_URB_WRITE_SIMD8:
 944    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 945    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 946    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 947    case FS_OPCODE_FB_WRITE:
 948    case SHADER_OPCODE_BARRIER:
 949    case TCS_OPCODE_URB_WRITE:
 950    case TCS_OPCODE_RELEASE_INPUT:
 951       return true;
 952    default:
 953       return false;
 954    }
 955 }
 956
 957 bool
 958 backend_instruction::is_volatile() const
 959 {
 960    switch (opcode) {
 961    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 962    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 963    case SHADER_OPCODE_TYPED_SURFACE_READ:
 964    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 965    case SHADER_OPCODE_URB_READ_SIMD8:
 966    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 967    case VEC4_OPCODE_URB_READ:
 968       return true;
 969    default:
 970       return false;
 971    }
 972 }
 973
 974 #ifndef NDEBUG
 975 static bool
 976 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 977 {
 978    bool found = false;
 979    foreach_inst_in_block (backend_instruction, i, block) {
 980       if (inst == i) {
 981          found = true;
 982       }
 983    }
 984    return found;
 985 }
 986 #endif
 987
 988 static void
 989 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 990 {
 991    for (bblock_t *block_iter = start_block->next();
 992         block_iter;
 993         block_iter = block_iter->next()) {
 994       block_iter->start_ip += ip_adjustment;
 995       block_iter->end_ip += ip_adjustment;
 996    }
 997 }
 998
 999 void
1000 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1001 {
1002    assert(this != inst);
1003
1004    if (!this->is_head_sentinel())
1005       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1006
1007    block->end_ip++;
1008
1009    adjust_later_block_ips(block, 1);
1010
1011    exec_node::insert_after(inst);
1012 }
1013
1014 void
1015 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1016 {
1017    assert(this != inst);
1018
1019    if (!this->is_tail_sentinel())
1020       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1021
1022    block->end_ip++;
1023
1024    adjust_later_block_ips(block, 1);
1025
1026    exec_node::insert_before(inst);
1027 }
1028
1029 void
1030 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1031 {
1032    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1033
1034    unsigned num_inst = list->length();
1035
1036    block->end_ip += num_inst;
1037
1038    adjust_later_block_ips(block, num_inst);
1039
1040    exec_node::insert_before(list);
1041 }
1042
1043 void
1044 backend_instruction::remove(bblock_t *block)
1045 {
1046    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1047
1048    adjust_later_block_ips(block, -1);
1049
1050    if (block->start_ip == block->end_ip) {
1051       block->cfg->remove_block(block);
1052    } else {
1053       block->end_ip--;
1054    }
1055
1056    exec_node::remove();
1057 }
1058
1059 void
1060 backend_shader::dump_instructions()
1061 {
1062    dump_instructions(NULL);
1063 }
1064
1065 void
1066 backend_shader::dump_instructions(const char *name)
1067 {
1068    FILE *file = stderr;
1069    if (name && geteuid() != 0) {
1070       file = fopen(name, "w");
1071       if (!file)
1072          file = stderr;
1073    }
1074
1075    if (cfg) {
1076       int ip = 0;
1077       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1078          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1079             fprintf(file, "%4d: ", ip++);
1080          dump_instruction(inst, file);
1081       }
1082    } else {
1083       int ip = 0;
1084       foreach_in_list(backend_instruction, inst, &instructions) {
1085          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1086             fprintf(file, "%4d: ", ip++);
1087          dump_instruction(inst, file);
1088       }
1089    }
1090
1091    if (file != stderr) {
1092       fclose(file);
1093    }
1094 }
1095
1096 void
1097 backend_shader::calculate_cfg()
1098 {
1099    if (this->cfg)
1100       return;
1101    cfg = new(mem_ctx) cfg_t(&this->instructions);
1102 }
1103
1104 /**
1105  * Sets up the starting offsets for the groups of binding table entries
1106  * commong to all pipeline stages.
1107  *
1108  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1109  * unused but also make sure that addition of small offsets to them will
1110  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1111  */
1112 void
1113 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1114                                         const struct brw_device_info *devinfo,
1115                                         const struct gl_shader_program *shader_prog,
1116                                         const struct gl_program *prog,
1117                                         struct brw_stage_prog_data *stage_prog_data,
1118                                         uint32_t next_binding_table_offset)
1119 {
1120    const struct gl_shader *shader = NULL;
1121    int num_textures = _mesa_fls(prog->SamplersUsed);
1122
1123    if (shader_prog)
1124       shader = shader_prog->_LinkedShaders[stage];
1125
1126    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1127    next_binding_table_offset += num_textures;
1128
1129    if (shader) {
1130       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1131       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1132       next_binding_table_offset += shader->NumUniformBlocks;
1133
1134       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1135       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1136       next_binding_table_offset += shader->NumShaderStorageBlocks;
1137    } else {
1138       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1139       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1140    }
1141
1142    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1143       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1144       next_binding_table_offset++;
1145    } else {
1146       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1147    }
1148
1149    if (prog->UsesGather) {
1150       if (devinfo->gen >= 8) {
1151          stage_prog_data->binding_table.gather_texture_start =
1152             stage_prog_data->binding_table.texture_start;
1153       } else {
1154          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1155          next_binding_table_offset += num_textures;
1156       }
1157    } else {
1158       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1159    }
1160
1161    if (shader && shader->NumAtomicBuffers) {
1162       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1163       next_binding_table_offset += shader->NumAtomicBuffers;
1164    } else {
1165       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1166    }
1167
1168    if (shader && shader->NumImages) {
1169       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1170       next_binding_table_offset += shader->NumImages;
1171    } else {
1172       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1173    }
1174
1175    /* This may or may not be used depending on how the compile goes. */
1176    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1177    next_binding_table_offset++;
1178
1179    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1180
1181    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1182 }
1183
1184 static void
1185 setup_vec4_uniform_value(const gl_constant_value **params,
1186                          const gl_constant_value *values,
1187                          unsigned n)
1188 {
1189    static const gl_constant_value zero = { 0 };
1190
1191    for (unsigned i = 0; i < n; ++i)
1192       params[i] = &values[i];
1193
1194    for (unsigned i = n; i < 4; ++i)
1195       params[i] = &zero;
1196 }
1197
1198 void
1199 brw_setup_image_uniform_values(gl_shader_stage stage,
1200                                struct brw_stage_prog_data *stage_prog_data,
1201                                unsigned param_start_index,
1202                                const gl_uniform_storage *storage)
1203 {
1204    const gl_constant_value **param =
1205       &stage_prog_data->param[param_start_index];
1206
1207    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1208       const unsigned image_idx = storage->opaque[stage].index + i;
1209       const brw_image_param *image_param =
1210          &stage_prog_data->image_param[image_idx];
1211
1212       /* Upload the brw_image_param structure.  The order is expected to match
1213        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1214        */
1215       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1216          (const gl_constant_value *)&image_param->surface_idx, 1);
1217       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1218          (const gl_constant_value *)image_param->offset, 2);
1219       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1220          (const gl_constant_value *)image_param->size, 3);
1221       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1222          (const gl_constant_value *)image_param->stride, 4);
1223       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1224          (const gl_constant_value *)image_param->tiling, 3);
1225       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1226          (const gl_constant_value *)image_param->swizzling, 2);
1227       param += BRW_IMAGE_PARAM_SIZE;
1228
1229       brw_mark_surface_used(
1230          stage_prog_data,
1231          stage_prog_data->binding_table.image_start + image_idx);
1232    }
1233 }
1234
1235 /**
1236  * Decide which set of clip planes should be used when clipping via
1237  * gl_Position or gl_ClipVertex.
1238  */
1239 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1240 {
1241    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1242       /* There is currently a GLSL vertex shader, so clip according to GLSL
1243        * rules, which means compare gl_ClipVertex (or gl_Position, if
1244        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1245        * that were stored in EyeUserPlane at the time the clip planes were
1246        * specified.
1247        */
1248       return ctx->Transform.EyeUserPlane;
1249    } else {
1250       /* Either we are using fixed function or an ARB vertex program.  In
1251        * either case the clip planes are going to be compared against
1252        * gl_Position (which is in clip coordinates) so we have to clip using
1253        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1254        * core.
1255        */
1256       return ctx->Transform._ClipUserPlane;
1257    }
1258 }
1259
1260 extern "C" const unsigned *
1261 brw_compile_tes(const struct brw_compiler *compiler,
1262                 void *log_data,
1263                 void *mem_ctx,
1264                 const struct brw_tes_prog_key *key,
1265                 struct brw_tes_prog_data *prog_data,
1266                 const nir_shader *src_shader,
1267                 struct gl_shader_program *shader_prog,
1268                 int shader_time_index,
1269                 unsigned *final_assembly_size,
1270                 char **error_str)
1271 {
1272    const struct brw_device_info *devinfo = compiler->devinfo;
1273    struct gl_shader *shader =
1274       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1275    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1276
1277    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1278    nir->info.inputs_read = key->inputs_read;
1279    nir->info.patch_inputs_read = key->patch_inputs_read;
1280
1281    struct brw_vue_map input_vue_map;
1282    brw_compute_tess_vue_map(&input_vue_map,
1283                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1284                             nir->info.patch_inputs_read);
1285
1286    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1287    brw_nir_lower_tes_inputs(nir, &input_vue_map);
1288    brw_nir_lower_vue_outputs(nir, is_scalar);
1289    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1290
1291    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1292                        nir->info.outputs_written,
1293                        nir->info.separate_shader);
1294
1295    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1296
1297    assert(output_size_bytes >= 1);
1298    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1299       if (error_str)
1300          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1301       return NULL;
1302    }
1303
1304    /* URB entry sizes are stored as a multiple of 64 bytes. */
1305    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1306
1307    bool need_patch_header = nir->info.system_values_read &
1308       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1309        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1310
1311    /* The TES will pull most inputs using URB read messages.
1312     *
1313     * However, we push the patch header for TessLevel factors when required,
1314     * as it's a tiny amount of extra data.
1315     */
1316    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1317
1318    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1319       fprintf(stderr, "TES Input ");
1320       brw_print_vue_map(stderr, &input_vue_map);
1321       fprintf(stderr, "TES Output ");
1322       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1323    }
1324
1325    if (is_scalar) {
1326       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1327                    &prog_data->base.base, shader->Program, nir, 8,
1328                    shader_time_index, &input_vue_map);
1329       if (!v.run_tes()) {
1330          if (error_str)
1331             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1332          return NULL;
1333       }
1334
1335       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1336
1337       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1338                      &prog_data->base.base, v.promoted_constants, false,
1339                      MESA_SHADER_TESS_EVAL);
1340       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1341          g.enable_debug(ralloc_asprintf(mem_ctx,
1342                                         "%s tessellation evaluation shader %s",
1343                                         nir->info.label ? nir->info.label
1344                                                         : "unnamed",
1345                                         nir->info.name));
1346       }
1347
1348       g.generate_code(v.cfg, 8);
1349
1350       return g.get_assembly(final_assembly_size);
1351    } else {
1352       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1353                               nir, mem_ctx, shader_time_index);
1354       if (!v.run()) {
1355          if (error_str)
1356             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1357          return NULL;
1358       }
1359
1360       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1361          v.dump_instructions();
1362
1363       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1364                                         &prog_data->base, v.cfg,
1365                                         final_assembly_size);
1366    }
1367 }