src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32
  33 extern "C" struct gl_shader *
  34 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  35 {
  36    struct brw_shader *shader;
  37
  38    shader = rzalloc(NULL, struct brw_shader);
  39    if (shader) {
  40       shader->base.Type = type;
  41       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  42       shader->base.Name = name;
  43       _mesa_init_shader(ctx, &shader->base);
  44    }
  45
  46    return &shader->base;
  47 }
  48
  49 extern "C" void
  50 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  51                       unsigned surf_index)
  52 {
  53    assert(surf_index < BRW_MAX_SURFACES);
  54
  55    prog_data->binding_table.size_bytes =
  56       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  57 }
  58
  59 enum brw_reg_type
  60 brw_type_for_base_type(const struct glsl_type *type)
  61 {
  62    switch (type->base_type) {
  63    case GLSL_TYPE_FLOAT:
  64       return BRW_REGISTER_TYPE_F;
  65    case GLSL_TYPE_INT:
  66    case GLSL_TYPE_BOOL:
  67    case GLSL_TYPE_SUBROUTINE:
  68       return BRW_REGISTER_TYPE_D;
  69    case GLSL_TYPE_UINT:
  70       return BRW_REGISTER_TYPE_UD;
  71    case GLSL_TYPE_ARRAY:
  72       return brw_type_for_base_type(type->fields.array);
  73    case GLSL_TYPE_STRUCT:
  74    case GLSL_TYPE_SAMPLER:
  75    case GLSL_TYPE_ATOMIC_UINT:
  76       /* These should be overridden with the type of the member when
  77        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  78        * way to trip up if we don't.
  79        */
  80       return BRW_REGISTER_TYPE_UD;
  81    case GLSL_TYPE_IMAGE:
  82       return BRW_REGISTER_TYPE_UD;
  83    case GLSL_TYPE_VOID:
  84    case GLSL_TYPE_ERROR:
  85    case GLSL_TYPE_INTERFACE:
  86    case GLSL_TYPE_DOUBLE:
  87       unreachable("not reached");
  88    }
  89
  90    return BRW_REGISTER_TYPE_F;
  91 }
  92
  93 enum brw_conditional_mod
  94 brw_conditional_for_comparison(unsigned int op)
  95 {
  96    switch (op) {
  97    case ir_binop_less:
  98       return BRW_CONDITIONAL_L;
  99    case ir_binop_greater:
 100       return BRW_CONDITIONAL_G;
 101    case ir_binop_lequal:
 102       return BRW_CONDITIONAL_LE;
 103    case ir_binop_gequal:
 104       return BRW_CONDITIONAL_GE;
 105    case ir_binop_equal:
 106    case ir_binop_all_equal: /* same as equal for scalars */
 107       return BRW_CONDITIONAL_Z;
 108    case ir_binop_nequal:
 109    case ir_binop_any_nequal: /* same as nequal for scalars */
 110       return BRW_CONDITIONAL_NZ;
 111    default:
 112       unreachable("not reached: bad operation for comparison");
 113    }
 114 }
 115
 116 uint32_t
 117 brw_math_function(enum opcode op)
 118 {
 119    switch (op) {
 120    case SHADER_OPCODE_RCP:
 121       return BRW_MATH_FUNCTION_INV;
 122    case SHADER_OPCODE_RSQ:
 123       return BRW_MATH_FUNCTION_RSQ;
 124    case SHADER_OPCODE_SQRT:
 125       return BRW_MATH_FUNCTION_SQRT;
 126    case SHADER_OPCODE_EXP2:
 127       return BRW_MATH_FUNCTION_EXP;
 128    case SHADER_OPCODE_LOG2:
 129       return BRW_MATH_FUNCTION_LOG;
 130    case SHADER_OPCODE_POW:
 131       return BRW_MATH_FUNCTION_POW;
 132    case SHADER_OPCODE_SIN:
 133       return BRW_MATH_FUNCTION_SIN;
 134    case SHADER_OPCODE_COS:
 135       return BRW_MATH_FUNCTION_COS;
 136    case SHADER_OPCODE_INT_QUOTIENT:
 137       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 138    case SHADER_OPCODE_INT_REMAINDER:
 139       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 140    default:
 141       unreachable("not reached: unknown math function");
 142    }
 143 }
 144
 145 uint32_t
 146 brw_texture_offset(int *offsets, unsigned num_components)
 147 {
 148    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 149
 150    /* Combine all three offsets into a single unsigned dword:
 151     *
 152     *    bits 11:8 - U Offset (X component)
 153     *    bits  7:4 - V Offset (Y component)
 154     *    bits  3:0 - R Offset (Z component)
 155     */
 156    unsigned offset_bits = 0;
 157    for (unsigned i = 0; i < num_components; i++) {
 158       const unsigned shift = 4 * (2 - i);
 159       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 160    }
 161    return offset_bits;
 162 }
 163
 164 const char *
 165 brw_instruction_name(enum opcode op)
 166 {
 167    switch (op) {
 168    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 169       assert(opcode_descs[op].name);
 170       return opcode_descs[op].name;
 171    case FS_OPCODE_FB_WRITE:
 172       return "fb_write";
 173    case FS_OPCODE_FB_WRITE_LOGICAL:
 174       return "fb_write_logical";
 175    case FS_OPCODE_PACK_STENCIL_REF:
 176       return "pack_stencil_ref";
 177    case FS_OPCODE_BLORP_FB_WRITE:
 178       return "blorp_fb_write";
 179    case FS_OPCODE_REP_FB_WRITE:
 180       return "rep_fb_write";
 181
 182    case SHADER_OPCODE_RCP:
 183       return "rcp";
 184    case SHADER_OPCODE_RSQ:
 185       return "rsq";
 186    case SHADER_OPCODE_SQRT:
 187       return "sqrt";
 188    case SHADER_OPCODE_EXP2:
 189       return "exp2";
 190    case SHADER_OPCODE_LOG2:
 191       return "log2";
 192    case SHADER_OPCODE_POW:
 193       return "pow";
 194    case SHADER_OPCODE_INT_QUOTIENT:
 195       return "int_quot";
 196    case SHADER_OPCODE_INT_REMAINDER:
 197       return "int_rem";
 198    case SHADER_OPCODE_SIN:
 199       return "sin";
 200    case SHADER_OPCODE_COS:
 201       return "cos";
 202
 203    case SHADER_OPCODE_TEX:
 204       return "tex";
 205    case SHADER_OPCODE_TEX_LOGICAL:
 206       return "tex_logical";
 207    case SHADER_OPCODE_TXD:
 208       return "txd";
 209    case SHADER_OPCODE_TXD_LOGICAL:
 210       return "txd_logical";
 211    case SHADER_OPCODE_TXF:
 212       return "txf";
 213    case SHADER_OPCODE_TXF_LOGICAL:
 214       return "txf_logical";
 215    case SHADER_OPCODE_TXL:
 216       return "txl";
 217    case SHADER_OPCODE_TXL_LOGICAL:
 218       return "txl_logical";
 219    case SHADER_OPCODE_TXS:
 220       return "txs";
 221    case SHADER_OPCODE_TXS_LOGICAL:
 222       return "txs_logical";
 223    case FS_OPCODE_TXB:
 224       return "txb";
 225    case FS_OPCODE_TXB_LOGICAL:
 226       return "txb_logical";
 227    case SHADER_OPCODE_TXF_CMS:
 228       return "txf_cms";
 229    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 230       return "txf_cms_logical";
 231    case SHADER_OPCODE_TXF_CMS_W:
 232       return "txf_cms_w";
 233    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 234       return "txf_cms_w_logical";
 235    case SHADER_OPCODE_TXF_UMS:
 236       return "txf_ums";
 237    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 238       return "txf_ums_logical";
 239    case SHADER_OPCODE_TXF_MCS:
 240       return "txf_mcs";
 241    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 242       return "txf_mcs_logical";
 243    case SHADER_OPCODE_LOD:
 244       return "lod";
 245    case SHADER_OPCODE_LOD_LOGICAL:
 246       return "lod_logical";
 247    case SHADER_OPCODE_TG4:
 248       return "tg4";
 249    case SHADER_OPCODE_TG4_LOGICAL:
 250       return "tg4_logical";
 251    case SHADER_OPCODE_TG4_OFFSET:
 252       return "tg4_offset";
 253    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 254       return "tg4_offset_logical";
 255    case SHADER_OPCODE_SAMPLEINFO:
 256       return "sampleinfo";
 257
 258    case SHADER_OPCODE_SHADER_TIME_ADD:
 259       return "shader_time_add";
 260
 261    case SHADER_OPCODE_UNTYPED_ATOMIC:
 262       return "untyped_atomic";
 263    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 264       return "untyped_atomic_logical";
 265    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 266       return "untyped_surface_read";
 267    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 268       return "untyped_surface_read_logical";
 269    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 270       return "untyped_surface_write";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 272       return "untyped_surface_write_logical";
 273    case SHADER_OPCODE_TYPED_ATOMIC:
 274       return "typed_atomic";
 275    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 276       return "typed_atomic_logical";
 277    case SHADER_OPCODE_TYPED_SURFACE_READ:
 278       return "typed_surface_read";
 279    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 280       return "typed_surface_read_logical";
 281    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 282       return "typed_surface_write";
 283    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 284       return "typed_surface_write_logical";
 285    case SHADER_OPCODE_MEMORY_FENCE:
 286       return "memory_fence";
 287
 288    case SHADER_OPCODE_LOAD_PAYLOAD:
 289       return "load_payload";
 290
 291    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 292       return "gen4_scratch_read";
 293    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 294       return "gen4_scratch_write";
 295    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 296       return "gen7_scratch_read";
 297    case SHADER_OPCODE_URB_WRITE_SIMD8:
 298       return "gen8_urb_write_simd8";
 299    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 300       return "gen8_urb_write_simd8_per_slot";
 301    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 302       return "gen8_urb_write_simd8_masked";
 303    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 304       return "gen8_urb_write_simd8_masked_per_slot";
 305    case SHADER_OPCODE_URB_READ_SIMD8:
 306       return "urb_read_simd8";
 307    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 308       return "urb_read_simd8_per_slot";
 309
 310    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 311       return "find_live_channel";
 312    case SHADER_OPCODE_BROADCAST:
 313       return "broadcast";
 314
 315    case SHADER_OPCODE_EXTRACT_BYTE:
 316       return "extract_byte";
 317    case SHADER_OPCODE_EXTRACT_WORD:
 318       return "extract_word";
 319    case VEC4_OPCODE_MOV_BYTES:
 320       return "mov_bytes";
 321    case VEC4_OPCODE_PACK_BYTES:
 322       return "pack_bytes";
 323    case VEC4_OPCODE_UNPACK_UNIFORM:
 324       return "unpack_uniform";
 325
 326    case FS_OPCODE_DDX_COARSE:
 327       return "ddx_coarse";
 328    case FS_OPCODE_DDX_FINE:
 329       return "ddx_fine";
 330    case FS_OPCODE_DDY_COARSE:
 331       return "ddy_coarse";
 332    case FS_OPCODE_DDY_FINE:
 333       return "ddy_fine";
 334
 335    case FS_OPCODE_CINTERP:
 336       return "cinterp";
 337    case FS_OPCODE_LINTERP:
 338       return "linterp";
 339
 340    case FS_OPCODE_PIXEL_X:
 341       return "pixel_x";
 342    case FS_OPCODE_PIXEL_Y:
 343       return "pixel_y";
 344
 345    case FS_OPCODE_GET_BUFFER_SIZE:
 346       return "fs_get_buffer_size";
 347
 348    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 349       return "uniform_pull_const";
 350    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 351       return "uniform_pull_const_gen7";
 352    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 353       return "varying_pull_const";
 354    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 355       return "varying_pull_const_gen7";
 356
 357    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 358       return "mov_dispatch_to_flags";
 359    case FS_OPCODE_DISCARD_JUMP:
 360       return "discard_jump";
 361
 362    case FS_OPCODE_SET_SAMPLE_ID:
 363       return "set_sample_id";
 364    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 365       return "set_simd4x2_offset";
 366
 367    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 368       return "pack_half_2x16_split";
 369    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 370       return "unpack_half_2x16_split_x";
 371    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 372       return "unpack_half_2x16_split_y";
 373
 374    case FS_OPCODE_PLACEHOLDER_HALT:
 375       return "placeholder_halt";
 376
 377    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 378       return "interp_centroid";
 379    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 380       return "interp_sample";
 381    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 382       return "interp_shared_offset";
 383    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 384       return "interp_per_slot_offset";
 385
 386    case VS_OPCODE_URB_WRITE:
 387       return "vs_urb_write";
 388    case VS_OPCODE_PULL_CONSTANT_LOAD:
 389       return "pull_constant_load";
 390    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 391       return "pull_constant_load_gen7";
 392
 393    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 394       return "set_simd4x2_header_gen9";
 395
 396    case VS_OPCODE_GET_BUFFER_SIZE:
 397       return "vs_get_buffer_size";
 398
 399    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 400       return "unpack_flags_simd4x2";
 401
 402    case GS_OPCODE_URB_WRITE:
 403       return "gs_urb_write";
 404    case GS_OPCODE_URB_WRITE_ALLOCATE:
 405       return "gs_urb_write_allocate";
 406    case GS_OPCODE_THREAD_END:
 407       return "gs_thread_end";
 408    case GS_OPCODE_SET_WRITE_OFFSET:
 409       return "set_write_offset";
 410    case GS_OPCODE_SET_VERTEX_COUNT:
 411       return "set_vertex_count";
 412    case GS_OPCODE_SET_DWORD_2:
 413       return "set_dword_2";
 414    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 415       return "prepare_channel_masks";
 416    case GS_OPCODE_SET_CHANNEL_MASKS:
 417       return "set_channel_masks";
 418    case GS_OPCODE_GET_INSTANCE_ID:
 419       return "get_instance_id";
 420    case GS_OPCODE_FF_SYNC:
 421       return "ff_sync";
 422    case GS_OPCODE_SET_PRIMITIVE_ID:
 423       return "set_primitive_id";
 424    case GS_OPCODE_SVB_WRITE:
 425       return "gs_svb_write";
 426    case GS_OPCODE_SVB_SET_DST_INDEX:
 427       return "gs_svb_set_dst_index";
 428    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 429       return "gs_ff_sync_set_primitives";
 430    case CS_OPCODE_CS_TERMINATE:
 431       return "cs_terminate";
 432    case SHADER_OPCODE_BARRIER:
 433       return "barrier";
 434    case SHADER_OPCODE_MULH:
 435       return "mulh";
 436    case SHADER_OPCODE_MOV_INDIRECT:
 437       return "mov_indirect";
 438
 439    case VEC4_OPCODE_URB_READ:
 440       return "urb_read";
 441    case TCS_OPCODE_GET_INSTANCE_ID:
 442       return "tcs_get_instance_id";
 443    case TCS_OPCODE_URB_WRITE:
 444       return "tcs_urb_write";
 445    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 446       return "tcs_set_input_urb_offsets";
 447    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 448       return "tcs_set_output_urb_offsets";
 449    case TCS_OPCODE_GET_PRIMITIVE_ID:
 450       return "tcs_get_primitive_id";
 451    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 452       return "tcs_create_barrier_header";
 453    case TCS_OPCODE_SRC0_010_IS_ZERO:
 454       return "tcs_src0<0,1,0>_is_zero";
 455    case TCS_OPCODE_RELEASE_INPUT:
 456       return "tcs_release_input";
 457    case TCS_OPCODE_THREAD_END:
 458       return "tcs_thread_end";
 459    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 460       return "tes_create_input_read_header";
 461    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 462       return "tes_add_indirect_urb_offset";
 463    case TES_OPCODE_GET_PRIMITIVE_ID:
 464       return "tes_get_primitive_id";
 465    }
 466
 467    unreachable("not reached");
 468 }
 469
 470 bool
 471 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 472 {
 473    union {
 474       unsigned ud;
 475       int d;
 476       float f;
 477    } imm = { reg->ud }, sat_imm = { 0 };
 478
 479    switch (type) {
 480    case BRW_REGISTER_TYPE_UD:
 481    case BRW_REGISTER_TYPE_D:
 482    case BRW_REGISTER_TYPE_UW:
 483    case BRW_REGISTER_TYPE_W:
 484    case BRW_REGISTER_TYPE_UQ:
 485    case BRW_REGISTER_TYPE_Q:
 486       /* Nothing to do. */
 487       return false;
 488    case BRW_REGISTER_TYPE_F:
 489       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 490       break;
 491    case BRW_REGISTER_TYPE_UB:
 492    case BRW_REGISTER_TYPE_B:
 493       unreachable("no UB/B immediates");
 494    case BRW_REGISTER_TYPE_V:
 495    case BRW_REGISTER_TYPE_UV:
 496    case BRW_REGISTER_TYPE_VF:
 497       unreachable("unimplemented: saturate vector immediate");
 498    case BRW_REGISTER_TYPE_DF:
 499    case BRW_REGISTER_TYPE_HF:
 500       unreachable("unimplemented: saturate DF/HF immediate");
 501    }
 502
 503    if (imm.ud != sat_imm.ud) {
 504       reg->ud = sat_imm.ud;
 505       return true;
 506    }
 507    return false;
 508 }
 509
 510 bool
 511 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 512 {
 513    switch (type) {
 514    case BRW_REGISTER_TYPE_D:
 515    case BRW_REGISTER_TYPE_UD:
 516       reg->d = -reg->d;
 517       return true;
 518    case BRW_REGISTER_TYPE_W:
 519    case BRW_REGISTER_TYPE_UW:
 520       reg->d = -(int16_t)reg->ud;
 521       return true;
 522    case BRW_REGISTER_TYPE_F:
 523       reg->f = -reg->f;
 524       return true;
 525    case BRW_REGISTER_TYPE_VF:
 526       reg->ud ^= 0x80808080;
 527       return true;
 528    case BRW_REGISTER_TYPE_UB:
 529    case BRW_REGISTER_TYPE_B:
 530       unreachable("no UB/B immediates");
 531    case BRW_REGISTER_TYPE_UV:
 532    case BRW_REGISTER_TYPE_V:
 533       assert(!"unimplemented: negate UV/V immediate");
 534    case BRW_REGISTER_TYPE_UQ:
 535    case BRW_REGISTER_TYPE_Q:
 536       assert(!"unimplemented: negate UQ/Q immediate");
 537    case BRW_REGISTER_TYPE_DF:
 538    case BRW_REGISTER_TYPE_HF:
 539       assert(!"unimplemented: negate DF/HF immediate");
 540    }
 541
 542    return false;
 543 }
 544
 545 bool
 546 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 547 {
 548    switch (type) {
 549    case BRW_REGISTER_TYPE_D:
 550       reg->d = abs(reg->d);
 551       return true;
 552    case BRW_REGISTER_TYPE_W:
 553       reg->d = abs((int16_t)reg->ud);
 554       return true;
 555    case BRW_REGISTER_TYPE_F:
 556       reg->f = fabsf(reg->f);
 557       return true;
 558    case BRW_REGISTER_TYPE_VF:
 559       reg->ud &= ~0x80808080;
 560       return true;
 561    case BRW_REGISTER_TYPE_UB:
 562    case BRW_REGISTER_TYPE_B:
 563       unreachable("no UB/B immediates");
 564    case BRW_REGISTER_TYPE_UQ:
 565    case BRW_REGISTER_TYPE_UD:
 566    case BRW_REGISTER_TYPE_UW:
 567    case BRW_REGISTER_TYPE_UV:
 568       /* Presumably the absolute value modifier on an unsigned source is a
 569        * nop, but it would be nice to confirm.
 570        */
 571       assert(!"unimplemented: abs unsigned immediate");
 572    case BRW_REGISTER_TYPE_V:
 573       assert(!"unimplemented: abs V immediate");
 574    case BRW_REGISTER_TYPE_Q:
 575       assert(!"unimplemented: abs Q immediate");
 576    case BRW_REGISTER_TYPE_DF:
 577    case BRW_REGISTER_TYPE_HF:
 578       assert(!"unimplemented: abs DF/HF immediate");
 579    }
 580
 581    return false;
 582 }
 583
 584 backend_shader::backend_shader(const struct brw_compiler *compiler,
 585                                void *log_data,
 586                                void *mem_ctx,
 587                                const nir_shader *shader,
 588                                struct brw_stage_prog_data *stage_prog_data)
 589    : compiler(compiler),
 590      log_data(log_data),
 591      devinfo(compiler->devinfo),
 592      nir(shader),
 593      stage_prog_data(stage_prog_data),
 594      mem_ctx(mem_ctx),
 595      cfg(NULL),
 596      stage(shader->stage)
 597 {
 598    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 599    stage_name = _mesa_shader_stage_to_string(stage);
 600    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 601 }
 602
 603 bool
 604 backend_reg::equals(const backend_reg &r) const
 605 {
 606    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 607           reg_offset == r.reg_offset;
 608 }
 609
 610 bool
 611 backend_reg::is_zero() const
 612 {
 613    if (file != IMM)
 614       return false;
 615
 616    return d == 0;
 617 }
 618
 619 bool
 620 backend_reg::is_one() const
 621 {
 622    if (file != IMM)
 623       return false;
 624
 625    return type == BRW_REGISTER_TYPE_F
 626           ? f == 1.0
 627           : d == 1;
 628 }
 629
 630 bool
 631 backend_reg::is_negative_one() const
 632 {
 633    if (file != IMM)
 634       return false;
 635
 636    switch (type) {
 637    case BRW_REGISTER_TYPE_F:
 638       return f == -1.0;
 639    case BRW_REGISTER_TYPE_D:
 640       return d == -1;
 641    default:
 642       return false;
 643    }
 644 }
 645
 646 bool
 647 backend_reg::is_null() const
 648 {
 649    return file == ARF && nr == BRW_ARF_NULL;
 650 }
 651
 652
 653 bool
 654 backend_reg::is_accumulator() const
 655 {
 656    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 657 }
 658
 659 bool
 660 backend_reg::in_range(const backend_reg &r, unsigned n) const
 661 {
 662    return (file == r.file &&
 663            nr == r.nr &&
 664            reg_offset >= r.reg_offset &&
 665            reg_offset < r.reg_offset + n);
 666 }
 667
 668 bool
 669 backend_instruction::is_commutative() const
 670 {
 671    switch (opcode) {
 672    case BRW_OPCODE_AND:
 673    case BRW_OPCODE_OR:
 674    case BRW_OPCODE_XOR:
 675    case BRW_OPCODE_ADD:
 676    case BRW_OPCODE_MUL:
 677    case SHADER_OPCODE_MULH:
 678       return true;
 679    case BRW_OPCODE_SEL:
 680       /* MIN and MAX are commutative. */
 681       if (conditional_mod == BRW_CONDITIONAL_GE ||
 682           conditional_mod == BRW_CONDITIONAL_L) {
 683          return true;
 684       }
 685       /* fallthrough */
 686    default:
 687       return false;
 688    }
 689 }
 690
 691 bool
 692 backend_instruction::is_3src() const
 693 {
 694    return ::is_3src(opcode);
 695 }
 696
 697 bool
 698 backend_instruction::is_tex() const
 699 {
 700    return (opcode == SHADER_OPCODE_TEX ||
 701            opcode == FS_OPCODE_TXB ||
 702            opcode == SHADER_OPCODE_TXD ||
 703            opcode == SHADER_OPCODE_TXF ||
 704            opcode == SHADER_OPCODE_TXF_CMS ||
 705            opcode == SHADER_OPCODE_TXF_CMS_W ||
 706            opcode == SHADER_OPCODE_TXF_UMS ||
 707            opcode == SHADER_OPCODE_TXF_MCS ||
 708            opcode == SHADER_OPCODE_TXL ||
 709            opcode == SHADER_OPCODE_TXS ||
 710            opcode == SHADER_OPCODE_LOD ||
 711            opcode == SHADER_OPCODE_TG4 ||
 712            opcode == SHADER_OPCODE_TG4_OFFSET);
 713 }
 714
 715 bool
 716 backend_instruction::is_math() const
 717 {
 718    return (opcode == SHADER_OPCODE_RCP ||
 719            opcode == SHADER_OPCODE_RSQ ||
 720            opcode == SHADER_OPCODE_SQRT ||
 721            opcode == SHADER_OPCODE_EXP2 ||
 722            opcode == SHADER_OPCODE_LOG2 ||
 723            opcode == SHADER_OPCODE_SIN ||
 724            opcode == SHADER_OPCODE_COS ||
 725            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 726            opcode == SHADER_OPCODE_INT_REMAINDER ||
 727            opcode == SHADER_OPCODE_POW);
 728 }
 729
 730 bool
 731 backend_instruction::is_control_flow() const
 732 {
 733    switch (opcode) {
 734    case BRW_OPCODE_DO:
 735    case BRW_OPCODE_WHILE:
 736    case BRW_OPCODE_IF:
 737    case BRW_OPCODE_ELSE:
 738    case BRW_OPCODE_ENDIF:
 739    case BRW_OPCODE_BREAK:
 740    case BRW_OPCODE_CONTINUE:
 741       return true;
 742    default:
 743       return false;
 744    }
 745 }
 746
 747 bool
 748 backend_instruction::can_do_source_mods() const
 749 {
 750    switch (opcode) {
 751    case BRW_OPCODE_ADDC:
 752    case BRW_OPCODE_BFE:
 753    case BRW_OPCODE_BFI1:
 754    case BRW_OPCODE_BFI2:
 755    case BRW_OPCODE_BFREV:
 756    case BRW_OPCODE_CBIT:
 757    case BRW_OPCODE_FBH:
 758    case BRW_OPCODE_FBL:
 759    case BRW_OPCODE_SUBB:
 760       return false;
 761    default:
 762       return true;
 763    }
 764 }
 765
 766 bool
 767 backend_instruction::can_do_saturate() const
 768 {
 769    switch (opcode) {
 770    case BRW_OPCODE_ADD:
 771    case BRW_OPCODE_ASR:
 772    case BRW_OPCODE_AVG:
 773    case BRW_OPCODE_DP2:
 774    case BRW_OPCODE_DP3:
 775    case BRW_OPCODE_DP4:
 776    case BRW_OPCODE_DPH:
 777    case BRW_OPCODE_F16TO32:
 778    case BRW_OPCODE_F32TO16:
 779    case BRW_OPCODE_LINE:
 780    case BRW_OPCODE_LRP:
 781    case BRW_OPCODE_MAC:
 782    case BRW_OPCODE_MAD:
 783    case BRW_OPCODE_MATH:
 784    case BRW_OPCODE_MOV:
 785    case BRW_OPCODE_MUL:
 786    case SHADER_OPCODE_MULH:
 787    case BRW_OPCODE_PLN:
 788    case BRW_OPCODE_RNDD:
 789    case BRW_OPCODE_RNDE:
 790    case BRW_OPCODE_RNDU:
 791    case BRW_OPCODE_RNDZ:
 792    case BRW_OPCODE_SEL:
 793    case BRW_OPCODE_SHL:
 794    case BRW_OPCODE_SHR:
 795    case FS_OPCODE_LINTERP:
 796    case SHADER_OPCODE_COS:
 797    case SHADER_OPCODE_EXP2:
 798    case SHADER_OPCODE_LOG2:
 799    case SHADER_OPCODE_POW:
 800    case SHADER_OPCODE_RCP:
 801    case SHADER_OPCODE_RSQ:
 802    case SHADER_OPCODE_SIN:
 803    case SHADER_OPCODE_SQRT:
 804       return true;
 805    default:
 806       return false;
 807    }
 808 }
 809
 810 bool
 811 backend_instruction::can_do_cmod() const
 812 {
 813    switch (opcode) {
 814    case BRW_OPCODE_ADD:
 815    case BRW_OPCODE_ADDC:
 816    case BRW_OPCODE_AND:
 817    case BRW_OPCODE_ASR:
 818    case BRW_OPCODE_AVG:
 819    case BRW_OPCODE_CMP:
 820    case BRW_OPCODE_CMPN:
 821    case BRW_OPCODE_DP2:
 822    case BRW_OPCODE_DP3:
 823    case BRW_OPCODE_DP4:
 824    case BRW_OPCODE_DPH:
 825    case BRW_OPCODE_F16TO32:
 826    case BRW_OPCODE_F32TO16:
 827    case BRW_OPCODE_FRC:
 828    case BRW_OPCODE_LINE:
 829    case BRW_OPCODE_LRP:
 830    case BRW_OPCODE_LZD:
 831    case BRW_OPCODE_MAC:
 832    case BRW_OPCODE_MACH:
 833    case BRW_OPCODE_MAD:
 834    case BRW_OPCODE_MOV:
 835    case BRW_OPCODE_MUL:
 836    case BRW_OPCODE_NOT:
 837    case BRW_OPCODE_OR:
 838    case BRW_OPCODE_PLN:
 839    case BRW_OPCODE_RNDD:
 840    case BRW_OPCODE_RNDE:
 841    case BRW_OPCODE_RNDU:
 842    case BRW_OPCODE_RNDZ:
 843    case BRW_OPCODE_SAD2:
 844    case BRW_OPCODE_SADA2:
 845    case BRW_OPCODE_SHL:
 846    case BRW_OPCODE_SHR:
 847    case BRW_OPCODE_SUBB:
 848    case BRW_OPCODE_XOR:
 849    case FS_OPCODE_CINTERP:
 850    case FS_OPCODE_LINTERP:
 851       return true;
 852    default:
 853       return false;
 854    }
 855 }
 856
 857 bool
 858 backend_instruction::reads_accumulator_implicitly() const
 859 {
 860    switch (opcode) {
 861    case BRW_OPCODE_MAC:
 862    case BRW_OPCODE_MACH:
 863    case BRW_OPCODE_SADA2:
 864       return true;
 865    default:
 866       return false;
 867    }
 868 }
 869
 870 bool
 871 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 872 {
 873    return writes_accumulator ||
 874           (devinfo->gen < 6 &&
 875            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 876             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 877              opcode != FS_OPCODE_CINTERP)));
 878 }
 879
 880 bool
 881 backend_instruction::has_side_effects() const
 882 {
 883    switch (opcode) {
 884    case SHADER_OPCODE_UNTYPED_ATOMIC:
 885    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 886    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 887    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 888    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 889    case SHADER_OPCODE_TYPED_ATOMIC:
 890    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 891    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 892    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 893    case SHADER_OPCODE_MEMORY_FENCE:
 894    case SHADER_OPCODE_URB_WRITE_SIMD8:
 895    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 896    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 897    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 898    case FS_OPCODE_FB_WRITE:
 899    case SHADER_OPCODE_BARRIER:
 900    case TCS_OPCODE_URB_WRITE:
 901    case TCS_OPCODE_RELEASE_INPUT:
 902       return true;
 903    default:
 904       return false;
 905    }
 906 }
 907
 908 bool
 909 backend_instruction::is_volatile() const
 910 {
 911    switch (opcode) {
 912    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 913    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 914    case SHADER_OPCODE_TYPED_SURFACE_READ:
 915    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 916       return true;
 917    default:
 918       return false;
 919    }
 920 }
 921
 922 #ifndef NDEBUG
 923 static bool
 924 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 925 {
 926    bool found = false;
 927    foreach_inst_in_block (backend_instruction, i, block) {
 928       if (inst == i) {
 929          found = true;
 930       }
 931    }
 932    return found;
 933 }
 934 #endif
 935
 936 static void
 937 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 938 {
 939    for (bblock_t *block_iter = start_block->next();
 940         !block_iter->link.is_tail_sentinel();
 941         block_iter = block_iter->next()) {
 942       block_iter->start_ip += ip_adjustment;
 943       block_iter->end_ip += ip_adjustment;
 944    }
 945 }
 946
 947 void
 948 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
 949 {
 950    if (!this->is_head_sentinel())
 951       assert(inst_is_in_block(block, this) || !"Instruction not in block");
 952
 953    block->end_ip++;
 954
 955    adjust_later_block_ips(block, 1);
 956
 957    exec_node::insert_after(inst);
 958 }
 959
 960 void
 961 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
 962 {
 963    if (!this->is_tail_sentinel())
 964       assert(inst_is_in_block(block, this) || !"Instruction not in block");
 965
 966    block->end_ip++;
 967
 968    adjust_later_block_ips(block, 1);
 969
 970    exec_node::insert_before(inst);
 971 }
 972
 973 void
 974 backend_instruction::insert_before(bblock_t *block, exec_list *list)
 975 {
 976    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 977
 978    unsigned num_inst = list->length();
 979
 980    block->end_ip += num_inst;
 981
 982    adjust_later_block_ips(block, num_inst);
 983
 984    exec_node::insert_before(list);
 985 }
 986
 987 void
 988 backend_instruction::remove(bblock_t *block)
 989 {
 990    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 991
 992    adjust_later_block_ips(block, -1);
 993
 994    if (block->start_ip == block->end_ip) {
 995       block->cfg->remove_block(block);
 996    } else {
 997       block->end_ip--;
 998    }
 999
1000    exec_node::remove();
1001 }
1002
1003 void
1004 backend_shader::dump_instructions()
1005 {
1006    dump_instructions(NULL);
1007 }
1008
1009 void
1010 backend_shader::dump_instructions(const char *name)
1011 {
1012    FILE *file = stderr;
1013    if (name && geteuid() != 0) {
1014       file = fopen(name, "w");
1015       if (!file)
1016          file = stderr;
1017    }
1018
1019    if (cfg) {
1020       int ip = 0;
1021       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1022          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1023             fprintf(file, "%4d: ", ip++);
1024          dump_instruction(inst, file);
1025       }
1026    } else {
1027       int ip = 0;
1028       foreach_in_list(backend_instruction, inst, &instructions) {
1029          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1030             fprintf(file, "%4d: ", ip++);
1031          dump_instruction(inst, file);
1032       }
1033    }
1034
1035    if (file != stderr) {
1036       fclose(file);
1037    }
1038 }
1039
1040 void
1041 backend_shader::calculate_cfg()
1042 {
1043    if (this->cfg)
1044       return;
1045    cfg = new(mem_ctx) cfg_t(&this->instructions);
1046 }
1047
1048 void
1049 backend_shader::invalidate_cfg()
1050 {
1051    ralloc_free(this->cfg);
1052    this->cfg = NULL;
1053 }
1054
1055 /**
1056  * Sets up the starting offsets for the groups of binding table entries
1057  * commong to all pipeline stages.
1058  *
1059  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1060  * unused but also make sure that addition of small offsets to them will
1061  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1062  */
1063 void
1064 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1065                                         const struct brw_device_info *devinfo,
1066                                         const struct gl_shader_program *shader_prog,
1067                                         const struct gl_program *prog,
1068                                         struct brw_stage_prog_data *stage_prog_data,
1069                                         uint32_t next_binding_table_offset)
1070 {
1071    const struct gl_shader *shader = NULL;
1072    int num_textures = _mesa_fls(prog->SamplersUsed);
1073
1074    if (shader_prog)
1075       shader = shader_prog->_LinkedShaders[stage];
1076
1077    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1078    next_binding_table_offset += num_textures;
1079
1080    if (shader) {
1081       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1082       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1083       next_binding_table_offset += shader->NumUniformBlocks;
1084
1085       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1086       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1087       next_binding_table_offset += shader->NumShaderStorageBlocks;
1088    } else {
1089       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1090       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1091    }
1092
1093    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1094       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1095       next_binding_table_offset++;
1096    } else {
1097       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1098    }
1099
1100    if (prog->UsesGather) {
1101       if (devinfo->gen >= 8) {
1102          stage_prog_data->binding_table.gather_texture_start =
1103             stage_prog_data->binding_table.texture_start;
1104       } else {
1105          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1106          next_binding_table_offset += num_textures;
1107       }
1108    } else {
1109       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1110    }
1111
1112    if (shader && shader->NumAtomicBuffers) {
1113       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1114       next_binding_table_offset += shader->NumAtomicBuffers;
1115    } else {
1116       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1117    }
1118
1119    if (shader && shader->NumImages) {
1120       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1121       next_binding_table_offset += shader->NumImages;
1122    } else {
1123       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1124    }
1125
1126    /* This may or may not be used depending on how the compile goes. */
1127    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1128    next_binding_table_offset++;
1129
1130    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1131
1132    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1133 }
1134
1135 static void
1136 setup_vec4_uniform_value(const gl_constant_value **params,
1137                          const gl_constant_value *values,
1138                          unsigned n)
1139 {
1140    static const gl_constant_value zero = { 0 };
1141
1142    for (unsigned i = 0; i < n; ++i)
1143       params[i] = &values[i];
1144
1145    for (unsigned i = n; i < 4; ++i)
1146       params[i] = &zero;
1147 }
1148
1149 void
1150 brw_setup_image_uniform_values(gl_shader_stage stage,
1151                                struct brw_stage_prog_data *stage_prog_data,
1152                                unsigned param_start_index,
1153                                const gl_uniform_storage *storage)
1154 {
1155    const gl_constant_value **param =
1156       &stage_prog_data->param[param_start_index];
1157
1158    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1159       const unsigned image_idx = storage->opaque[stage].index + i;
1160       const brw_image_param *image_param =
1161          &stage_prog_data->image_param[image_idx];
1162
1163       /* Upload the brw_image_param structure.  The order is expected to match
1164        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1165        */
1166       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1167          (const gl_constant_value *)&image_param->surface_idx, 1);
1168       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1169          (const gl_constant_value *)image_param->offset, 2);
1170       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1171          (const gl_constant_value *)image_param->size, 3);
1172       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1173          (const gl_constant_value *)image_param->stride, 4);
1174       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1175          (const gl_constant_value *)image_param->tiling, 3);
1176       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1177          (const gl_constant_value *)image_param->swizzling, 2);
1178       param += BRW_IMAGE_PARAM_SIZE;
1179
1180       brw_mark_surface_used(
1181          stage_prog_data,
1182          stage_prog_data->binding_table.image_start + image_idx);
1183    }
1184 }
1185
1186 /**
1187  * Decide which set of clip planes should be used when clipping via
1188  * gl_Position or gl_ClipVertex.
1189  */
1190 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1191 {
1192    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1193       /* There is currently a GLSL vertex shader, so clip according to GLSL
1194        * rules, which means compare gl_ClipVertex (or gl_Position, if
1195        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1196        * that were stored in EyeUserPlane at the time the clip planes were
1197        * specified.
1198        */
1199       return ctx->Transform.EyeUserPlane;
1200    } else {
1201       /* Either we are using fixed function or an ARB vertex program.  In
1202        * either case the clip planes are going to be compared against
1203        * gl_Position (which is in clip coordinates) so we have to clip using
1204        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1205        * core.
1206        */
1207       return ctx->Transform._ClipUserPlane;
1208    }
1209 }
1210
1211 extern "C" const unsigned *
1212 brw_compile_tes(const struct brw_compiler *compiler,
1213                 void *log_data,
1214                 void *mem_ctx,
1215                 const struct brw_tes_prog_key *key,
1216                 struct brw_tes_prog_data *prog_data,
1217                 const nir_shader *src_shader,
1218                 struct gl_shader_program *shader_prog,
1219                 int shader_time_index,
1220                 unsigned *final_assembly_size,
1221                 char **error_str)
1222 {
1223    const struct brw_device_info *devinfo = compiler->devinfo;
1224    struct gl_shader *shader =
1225       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1226    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1227
1228    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1229    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1230    nir->info.inputs_read = key->inputs_read;
1231    nir->info.patch_inputs_read = key->patch_inputs_read;
1232    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
1233    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1234
1235    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1236                        nir->info.outputs_written,
1237                        nir->info.separate_shader);
1238
1239    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1240
1241    assert(output_size_bytes >= 1);
1242    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1243       if (error_str)
1244          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1245       return NULL;
1246    }
1247
1248    /* URB entry sizes are stored as a multiple of 64 bytes. */
1249    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1250
1251    struct brw_vue_map input_vue_map;
1252    brw_compute_tess_vue_map(&input_vue_map,
1253                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1254                             nir->info.patch_inputs_read);
1255
1256    bool need_patch_header = nir->info.system_values_read &
1257       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1258        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1259
1260    /* The TES will pull most inputs using URB read messages.
1261     *
1262     * However, we push the patch header for TessLevel factors when required,
1263     * as it's a tiny amount of extra data.
1264     */
1265    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1266
1267    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1268       fprintf(stderr, "TES Input ");
1269       brw_print_vue_map(stderr, &input_vue_map);
1270       fprintf(stderr, "TES Output ");
1271       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1272    }
1273
1274    if (is_scalar) {
1275       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1276                    &prog_data->base.base, shader->Program, nir, 8,
1277                    shader_time_index, &input_vue_map);
1278       if (!v.run_tes()) {
1279          if (error_str)
1280             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1281          return NULL;
1282       }
1283
1284       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1285
1286       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1287                      &prog_data->base.base, v.promoted_constants, false,
1288                      MESA_SHADER_TESS_EVAL);
1289       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1290          g.enable_debug(ralloc_asprintf(mem_ctx,
1291                                         "%s tessellation evaluation shader %s",
1292                                         nir->info.label ? nir->info.label
1293                                                         : "unnamed",
1294                                         nir->info.name));
1295       }
1296
1297       g.generate_code(v.cfg, 8);
1298
1299       return g.get_assembly(final_assembly_size);
1300    } else {
1301       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1302                               nir, mem_ctx, shader_time_index);
1303       if (!v.run()) {
1304          if (error_str)
1305             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1306          return NULL;
1307       }
1308
1309       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1310          v.dump_instructions();
1311
1312       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1313                                         &prog_data->base, v.cfg,
1314                                         final_assembly_size);
1315    }
1316 }