src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32
  33 extern "C" struct gl_shader *
  34 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  35 {
  36    struct brw_shader *shader;
  37
  38    shader = rzalloc(NULL, struct brw_shader);
  39    if (shader) {
  40       shader->base.Type = type;
  41       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  42       shader->base.Name = name;
  43       _mesa_init_shader(ctx, &shader->base);
  44    }
  45
  46    return &shader->base;
  47 }
  48
  49 extern "C" void
  50 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  51                       unsigned surf_index)
  52 {
  53    assert(surf_index < BRW_MAX_SURFACES);
  54
  55    prog_data->binding_table.size_bytes =
  56       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  57 }
  58
  59 enum brw_reg_type
  60 brw_type_for_base_type(const struct glsl_type *type)
  61 {
  62    switch (type->base_type) {
  63    case GLSL_TYPE_FLOAT:
  64       return BRW_REGISTER_TYPE_F;
  65    case GLSL_TYPE_INT:
  66    case GLSL_TYPE_BOOL:
  67    case GLSL_TYPE_SUBROUTINE:
  68       return BRW_REGISTER_TYPE_D;
  69    case GLSL_TYPE_UINT:
  70       return BRW_REGISTER_TYPE_UD;
  71    case GLSL_TYPE_ARRAY:
  72       return brw_type_for_base_type(type->fields.array);
  73    case GLSL_TYPE_STRUCT:
  74    case GLSL_TYPE_SAMPLER:
  75    case GLSL_TYPE_ATOMIC_UINT:
  76       /* These should be overridden with the type of the member when
  77        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  78        * way to trip up if we don't.
  79        */
  80       return BRW_REGISTER_TYPE_UD;
  81    case GLSL_TYPE_IMAGE:
  82       return BRW_REGISTER_TYPE_UD;
  83    case GLSL_TYPE_VOID:
  84    case GLSL_TYPE_ERROR:
  85    case GLSL_TYPE_INTERFACE:
  86    case GLSL_TYPE_DOUBLE:
  87       unreachable("not reached");
  88    }
  89
  90    return BRW_REGISTER_TYPE_F;
  91 }
  92
  93 enum brw_conditional_mod
  94 brw_conditional_for_comparison(unsigned int op)
  95 {
  96    switch (op) {
  97    case ir_binop_less:
  98       return BRW_CONDITIONAL_L;
  99    case ir_binop_greater:
 100       return BRW_CONDITIONAL_G;
 101    case ir_binop_lequal:
 102       return BRW_CONDITIONAL_LE;
 103    case ir_binop_gequal:
 104       return BRW_CONDITIONAL_GE;
 105    case ir_binop_equal:
 106    case ir_binop_all_equal: /* same as equal for scalars */
 107       return BRW_CONDITIONAL_Z;
 108    case ir_binop_nequal:
 109    case ir_binop_any_nequal: /* same as nequal for scalars */
 110       return BRW_CONDITIONAL_NZ;
 111    default:
 112       unreachable("not reached: bad operation for comparison");
 113    }
 114 }
 115
 116 uint32_t
 117 brw_math_function(enum opcode op)
 118 {
 119    switch (op) {
 120    case SHADER_OPCODE_RCP:
 121       return BRW_MATH_FUNCTION_INV;
 122    case SHADER_OPCODE_RSQ:
 123       return BRW_MATH_FUNCTION_RSQ;
 124    case SHADER_OPCODE_SQRT:
 125       return BRW_MATH_FUNCTION_SQRT;
 126    case SHADER_OPCODE_EXP2:
 127       return BRW_MATH_FUNCTION_EXP;
 128    case SHADER_OPCODE_LOG2:
 129       return BRW_MATH_FUNCTION_LOG;
 130    case SHADER_OPCODE_POW:
 131       return BRW_MATH_FUNCTION_POW;
 132    case SHADER_OPCODE_SIN:
 133       return BRW_MATH_FUNCTION_SIN;
 134    case SHADER_OPCODE_COS:
 135       return BRW_MATH_FUNCTION_COS;
 136    case SHADER_OPCODE_INT_QUOTIENT:
 137       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 138    case SHADER_OPCODE_INT_REMAINDER:
 139       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 140    default:
 141       unreachable("not reached: unknown math function");
 142    }
 143 }
 144
 145 uint32_t
 146 brw_texture_offset(int *offsets, unsigned num_components)
 147 {
 148    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 149
 150    /* Combine all three offsets into a single unsigned dword:
 151     *
 152     *    bits 11:8 - U Offset (X component)
 153     *    bits  7:4 - V Offset (Y component)
 154     *    bits  3:0 - R Offset (Z component)
 155     */
 156    unsigned offset_bits = 0;
 157    for (unsigned i = 0; i < num_components; i++) {
 158       const unsigned shift = 4 * (2 - i);
 159       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 160    }
 161    return offset_bits;
 162 }
 163
 164 const char *
 165 brw_instruction_name(enum opcode op)
 166 {
 167    switch (op) {
 168    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 169       assert(opcode_descs[op].name);
 170       return opcode_descs[op].name;
 171    case FS_OPCODE_FB_WRITE:
 172       return "fb_write";
 173    case FS_OPCODE_FB_WRITE_LOGICAL:
 174       return "fb_write_logical";
 175    case FS_OPCODE_PACK_STENCIL_REF:
 176       return "pack_stencil_ref";
 177    case FS_OPCODE_BLORP_FB_WRITE:
 178       return "blorp_fb_write";
 179    case FS_OPCODE_REP_FB_WRITE:
 180       return "rep_fb_write";
 181
 182    case SHADER_OPCODE_RCP:
 183       return "rcp";
 184    case SHADER_OPCODE_RSQ:
 185       return "rsq";
 186    case SHADER_OPCODE_SQRT:
 187       return "sqrt";
 188    case SHADER_OPCODE_EXP2:
 189       return "exp2";
 190    case SHADER_OPCODE_LOG2:
 191       return "log2";
 192    case SHADER_OPCODE_POW:
 193       return "pow";
 194    case SHADER_OPCODE_INT_QUOTIENT:
 195       return "int_quot";
 196    case SHADER_OPCODE_INT_REMAINDER:
 197       return "int_rem";
 198    case SHADER_OPCODE_SIN:
 199       return "sin";
 200    case SHADER_OPCODE_COS:
 201       return "cos";
 202
 203    case SHADER_OPCODE_TEX:
 204       return "tex";
 205    case SHADER_OPCODE_TEX_LOGICAL:
 206       return "tex_logical";
 207    case SHADER_OPCODE_TXD:
 208       return "txd";
 209    case SHADER_OPCODE_TXD_LOGICAL:
 210       return "txd_logical";
 211    case SHADER_OPCODE_TXF:
 212       return "txf";
 213    case SHADER_OPCODE_TXF_LOGICAL:
 214       return "txf_logical";
 215    case SHADER_OPCODE_TXL:
 216       return "txl";
 217    case SHADER_OPCODE_TXL_LOGICAL:
 218       return "txl_logical";
 219    case SHADER_OPCODE_TXS:
 220       return "txs";
 221    case SHADER_OPCODE_TXS_LOGICAL:
 222       return "txs_logical";
 223    case FS_OPCODE_TXB:
 224       return "txb";
 225    case FS_OPCODE_TXB_LOGICAL:
 226       return "txb_logical";
 227    case SHADER_OPCODE_TXF_CMS:
 228       return "txf_cms";
 229    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 230       return "txf_cms_logical";
 231    case SHADER_OPCODE_TXF_CMS_W:
 232       return "txf_cms_w";
 233    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 234       return "txf_cms_w_logical";
 235    case SHADER_OPCODE_TXF_UMS:
 236       return "txf_ums";
 237    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 238       return "txf_ums_logical";
 239    case SHADER_OPCODE_TXF_MCS:
 240       return "txf_mcs";
 241    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 242       return "txf_mcs_logical";
 243    case SHADER_OPCODE_LOD:
 244       return "lod";
 245    case SHADER_OPCODE_LOD_LOGICAL:
 246       return "lod_logical";
 247    case SHADER_OPCODE_TG4:
 248       return "tg4";
 249    case SHADER_OPCODE_TG4_LOGICAL:
 250       return "tg4_logical";
 251    case SHADER_OPCODE_TG4_OFFSET:
 252       return "tg4_offset";
 253    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 254       return "tg4_offset_logical";
 255    case SHADER_OPCODE_SAMPLEINFO:
 256       return "sampleinfo";
 257
 258    case SHADER_OPCODE_SHADER_TIME_ADD:
 259       return "shader_time_add";
 260
 261    case SHADER_OPCODE_UNTYPED_ATOMIC:
 262       return "untyped_atomic";
 263    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 264       return "untyped_atomic_logical";
 265    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 266       return "untyped_surface_read";
 267    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 268       return "untyped_surface_read_logical";
 269    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 270       return "untyped_surface_write";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 272       return "untyped_surface_write_logical";
 273    case SHADER_OPCODE_TYPED_ATOMIC:
 274       return "typed_atomic";
 275    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 276       return "typed_atomic_logical";
 277    case SHADER_OPCODE_TYPED_SURFACE_READ:
 278       return "typed_surface_read";
 279    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 280       return "typed_surface_read_logical";
 281    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 282       return "typed_surface_write";
 283    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 284       return "typed_surface_write_logical";
 285    case SHADER_OPCODE_MEMORY_FENCE:
 286       return "memory_fence";
 287
 288    case SHADER_OPCODE_LOAD_PAYLOAD:
 289       return "load_payload";
 290
 291    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 292       return "gen4_scratch_read";
 293    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 294       return "gen4_scratch_write";
 295    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 296       return "gen7_scratch_read";
 297    case SHADER_OPCODE_URB_WRITE_SIMD8:
 298       return "gen8_urb_write_simd8";
 299    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 300       return "gen8_urb_write_simd8_per_slot";
 301    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 302       return "gen8_urb_write_simd8_masked";
 303    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 304       return "gen8_urb_write_simd8_masked_per_slot";
 305    case SHADER_OPCODE_URB_READ_SIMD8:
 306       return "urb_read_simd8";
 307    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 308       return "urb_read_simd8_per_slot";
 309
 310    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 311       return "find_live_channel";
 312    case SHADER_OPCODE_BROADCAST:
 313       return "broadcast";
 314
 315    case VEC4_OPCODE_MOV_BYTES:
 316       return "mov_bytes";
 317    case VEC4_OPCODE_PACK_BYTES:
 318       return "pack_bytes";
 319    case VEC4_OPCODE_UNPACK_UNIFORM:
 320       return "unpack_uniform";
 321
 322    case FS_OPCODE_DDX_COARSE:
 323       return "ddx_coarse";
 324    case FS_OPCODE_DDX_FINE:
 325       return "ddx_fine";
 326    case FS_OPCODE_DDY_COARSE:
 327       return "ddy_coarse";
 328    case FS_OPCODE_DDY_FINE:
 329       return "ddy_fine";
 330
 331    case FS_OPCODE_CINTERP:
 332       return "cinterp";
 333    case FS_OPCODE_LINTERP:
 334       return "linterp";
 335
 336    case FS_OPCODE_PIXEL_X:
 337       return "pixel_x";
 338    case FS_OPCODE_PIXEL_Y:
 339       return "pixel_y";
 340
 341    case FS_OPCODE_GET_BUFFER_SIZE:
 342       return "fs_get_buffer_size";
 343
 344    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 345       return "uniform_pull_const";
 346    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 347       return "uniform_pull_const_gen7";
 348    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 349       return "varying_pull_const";
 350    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 351       return "varying_pull_const_gen7";
 352
 353    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 354       return "mov_dispatch_to_flags";
 355    case FS_OPCODE_DISCARD_JUMP:
 356       return "discard_jump";
 357
 358    case FS_OPCODE_SET_SAMPLE_ID:
 359       return "set_sample_id";
 360    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 361       return "set_simd4x2_offset";
 362
 363    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 364       return "pack_half_2x16_split";
 365    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 366       return "unpack_half_2x16_split_x";
 367    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 368       return "unpack_half_2x16_split_y";
 369
 370    case FS_OPCODE_PLACEHOLDER_HALT:
 371       return "placeholder_halt";
 372
 373    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 374       return "interp_centroid";
 375    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 376       return "interp_sample";
 377    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 378       return "interp_shared_offset";
 379    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 380       return "interp_per_slot_offset";
 381
 382    case VS_OPCODE_URB_WRITE:
 383       return "vs_urb_write";
 384    case VS_OPCODE_PULL_CONSTANT_LOAD:
 385       return "pull_constant_load";
 386    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 387       return "pull_constant_load_gen7";
 388
 389    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 390       return "set_simd4x2_header_gen9";
 391
 392    case VS_OPCODE_GET_BUFFER_SIZE:
 393       return "vs_get_buffer_size";
 394
 395    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 396       return "unpack_flags_simd4x2";
 397
 398    case GS_OPCODE_URB_WRITE:
 399       return "gs_urb_write";
 400    case GS_OPCODE_URB_WRITE_ALLOCATE:
 401       return "gs_urb_write_allocate";
 402    case GS_OPCODE_THREAD_END:
 403       return "gs_thread_end";
 404    case GS_OPCODE_SET_WRITE_OFFSET:
 405       return "set_write_offset";
 406    case GS_OPCODE_SET_VERTEX_COUNT:
 407       return "set_vertex_count";
 408    case GS_OPCODE_SET_DWORD_2:
 409       return "set_dword_2";
 410    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 411       return "prepare_channel_masks";
 412    case GS_OPCODE_SET_CHANNEL_MASKS:
 413       return "set_channel_masks";
 414    case GS_OPCODE_GET_INSTANCE_ID:
 415       return "get_instance_id";
 416    case GS_OPCODE_FF_SYNC:
 417       return "ff_sync";
 418    case GS_OPCODE_SET_PRIMITIVE_ID:
 419       return "set_primitive_id";
 420    case GS_OPCODE_SVB_WRITE:
 421       return "gs_svb_write";
 422    case GS_OPCODE_SVB_SET_DST_INDEX:
 423       return "gs_svb_set_dst_index";
 424    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 425       return "gs_ff_sync_set_primitives";
 426    case CS_OPCODE_CS_TERMINATE:
 427       return "cs_terminate";
 428    case SHADER_OPCODE_BARRIER:
 429       return "barrier";
 430    case SHADER_OPCODE_MULH:
 431       return "mulh";
 432    case SHADER_OPCODE_MOV_INDIRECT:
 433       return "mov_indirect";
 434
 435    case VEC4_OPCODE_URB_READ:
 436       return "urb_read";
 437    case TCS_OPCODE_GET_INSTANCE_ID:
 438       return "tcs_get_instance_id";
 439    case TCS_OPCODE_URB_WRITE:
 440       return "tcs_urb_write";
 441    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 442       return "tcs_set_input_urb_offsets";
 443    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 444       return "tcs_set_output_urb_offsets";
 445    case TCS_OPCODE_GET_PRIMITIVE_ID:
 446       return "tcs_get_primitive_id";
 447    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 448       return "tcs_create_barrier_header";
 449    case TCS_OPCODE_SRC0_010_IS_ZERO:
 450       return "tcs_src0<0,1,0>_is_zero";
 451    case TCS_OPCODE_RELEASE_INPUT:
 452       return "tcs_release_input";
 453    case TCS_OPCODE_THREAD_END:
 454       return "tcs_thread_end";
 455    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 456       return "tes_create_input_read_header";
 457    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 458       return "tes_add_indirect_urb_offset";
 459    case TES_OPCODE_GET_PRIMITIVE_ID:
 460       return "tes_get_primitive_id";
 461    }
 462
 463    unreachable("not reached");
 464 }
 465
 466 bool
 467 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 468 {
 469    union {
 470       unsigned ud;
 471       int d;
 472       float f;
 473    } imm = { reg->ud }, sat_imm = { 0 };
 474
 475    switch (type) {
 476    case BRW_REGISTER_TYPE_UD:
 477    case BRW_REGISTER_TYPE_D:
 478    case BRW_REGISTER_TYPE_UW:
 479    case BRW_REGISTER_TYPE_W:
 480    case BRW_REGISTER_TYPE_UQ:
 481    case BRW_REGISTER_TYPE_Q:
 482       /* Nothing to do. */
 483       return false;
 484    case BRW_REGISTER_TYPE_F:
 485       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 486       break;
 487    case BRW_REGISTER_TYPE_UB:
 488    case BRW_REGISTER_TYPE_B:
 489       unreachable("no UB/B immediates");
 490    case BRW_REGISTER_TYPE_V:
 491    case BRW_REGISTER_TYPE_UV:
 492    case BRW_REGISTER_TYPE_VF:
 493       unreachable("unimplemented: saturate vector immediate");
 494    case BRW_REGISTER_TYPE_DF:
 495    case BRW_REGISTER_TYPE_HF:
 496       unreachable("unimplemented: saturate DF/HF immediate");
 497    }
 498
 499    if (imm.ud != sat_imm.ud) {
 500       reg->ud = sat_imm.ud;
 501       return true;
 502    }
 503    return false;
 504 }
 505
 506 bool
 507 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 508 {
 509    switch (type) {
 510    case BRW_REGISTER_TYPE_D:
 511    case BRW_REGISTER_TYPE_UD:
 512       reg->d = -reg->d;
 513       return true;
 514    case BRW_REGISTER_TYPE_W:
 515    case BRW_REGISTER_TYPE_UW:
 516       reg->d = -(int16_t)reg->ud;
 517       return true;
 518    case BRW_REGISTER_TYPE_F:
 519       reg->f = -reg->f;
 520       return true;
 521    case BRW_REGISTER_TYPE_VF:
 522       reg->ud ^= 0x80808080;
 523       return true;
 524    case BRW_REGISTER_TYPE_UB:
 525    case BRW_REGISTER_TYPE_B:
 526       unreachable("no UB/B immediates");
 527    case BRW_REGISTER_TYPE_UV:
 528    case BRW_REGISTER_TYPE_V:
 529       assert(!"unimplemented: negate UV/V immediate");
 530    case BRW_REGISTER_TYPE_UQ:
 531    case BRW_REGISTER_TYPE_Q:
 532       assert(!"unimplemented: negate UQ/Q immediate");
 533    case BRW_REGISTER_TYPE_DF:
 534    case BRW_REGISTER_TYPE_HF:
 535       assert(!"unimplemented: negate DF/HF immediate");
 536    }
 537
 538    return false;
 539 }
 540
 541 bool
 542 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 543 {
 544    switch (type) {
 545    case BRW_REGISTER_TYPE_D:
 546       reg->d = abs(reg->d);
 547       return true;
 548    case BRW_REGISTER_TYPE_W:
 549       reg->d = abs((int16_t)reg->ud);
 550       return true;
 551    case BRW_REGISTER_TYPE_F:
 552       reg->f = fabsf(reg->f);
 553       return true;
 554    case BRW_REGISTER_TYPE_VF:
 555       reg->ud &= ~0x80808080;
 556       return true;
 557    case BRW_REGISTER_TYPE_UB:
 558    case BRW_REGISTER_TYPE_B:
 559       unreachable("no UB/B immediates");
 560    case BRW_REGISTER_TYPE_UQ:
 561    case BRW_REGISTER_TYPE_UD:
 562    case BRW_REGISTER_TYPE_UW:
 563    case BRW_REGISTER_TYPE_UV:
 564       /* Presumably the absolute value modifier on an unsigned source is a
 565        * nop, but it would be nice to confirm.
 566        */
 567       assert(!"unimplemented: abs unsigned immediate");
 568    case BRW_REGISTER_TYPE_V:
 569       assert(!"unimplemented: abs V immediate");
 570    case BRW_REGISTER_TYPE_Q:
 571       assert(!"unimplemented: abs Q immediate");
 572    case BRW_REGISTER_TYPE_DF:
 573    case BRW_REGISTER_TYPE_HF:
 574       assert(!"unimplemented: abs DF/HF immediate");
 575    }
 576
 577    return false;
 578 }
 579
 580 backend_shader::backend_shader(const struct brw_compiler *compiler,
 581                                void *log_data,
 582                                void *mem_ctx,
 583                                const nir_shader *shader,
 584                                struct brw_stage_prog_data *stage_prog_data)
 585    : compiler(compiler),
 586      log_data(log_data),
 587      devinfo(compiler->devinfo),
 588      nir(shader),
 589      stage_prog_data(stage_prog_data),
 590      mem_ctx(mem_ctx),
 591      cfg(NULL),
 592      stage(shader->stage)
 593 {
 594    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 595    stage_name = _mesa_shader_stage_to_string(stage);
 596    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 597 }
 598
 599 bool
 600 backend_reg::equals(const backend_reg &r) const
 601 {
 602    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 603           reg_offset == r.reg_offset;
 604 }
 605
 606 bool
 607 backend_reg::is_zero() const
 608 {
 609    if (file != IMM)
 610       return false;
 611
 612    return d == 0;
 613 }
 614
 615 bool
 616 backend_reg::is_one() const
 617 {
 618    if (file != IMM)
 619       return false;
 620
 621    return type == BRW_REGISTER_TYPE_F
 622           ? f == 1.0
 623           : d == 1;
 624 }
 625
 626 bool
 627 backend_reg::is_negative_one() const
 628 {
 629    if (file != IMM)
 630       return false;
 631
 632    switch (type) {
 633    case BRW_REGISTER_TYPE_F:
 634       return f == -1.0;
 635    case BRW_REGISTER_TYPE_D:
 636       return d == -1;
 637    default:
 638       return false;
 639    }
 640 }
 641
 642 bool
 643 backend_reg::is_null() const
 644 {
 645    return file == ARF && nr == BRW_ARF_NULL;
 646 }
 647
 648
 649 bool
 650 backend_reg::is_accumulator() const
 651 {
 652    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 653 }
 654
 655 bool
 656 backend_reg::in_range(const backend_reg &r, unsigned n) const
 657 {
 658    return (file == r.file &&
 659            nr == r.nr &&
 660            reg_offset >= r.reg_offset &&
 661            reg_offset < r.reg_offset + n);
 662 }
 663
 664 bool
 665 backend_instruction::is_commutative() const
 666 {
 667    switch (opcode) {
 668    case BRW_OPCODE_AND:
 669    case BRW_OPCODE_OR:
 670    case BRW_OPCODE_XOR:
 671    case BRW_OPCODE_ADD:
 672    case BRW_OPCODE_MUL:
 673    case SHADER_OPCODE_MULH:
 674       return true;
 675    case BRW_OPCODE_SEL:
 676       /* MIN and MAX are commutative. */
 677       if (conditional_mod == BRW_CONDITIONAL_GE ||
 678           conditional_mod == BRW_CONDITIONAL_L) {
 679          return true;
 680       }
 681       /* fallthrough */
 682    default:
 683       return false;
 684    }
 685 }
 686
 687 bool
 688 backend_instruction::is_3src() const
 689 {
 690    return ::is_3src(opcode);
 691 }
 692
 693 bool
 694 backend_instruction::is_tex() const
 695 {
 696    return (opcode == SHADER_OPCODE_TEX ||
 697            opcode == FS_OPCODE_TXB ||
 698            opcode == SHADER_OPCODE_TXD ||
 699            opcode == SHADER_OPCODE_TXF ||
 700            opcode == SHADER_OPCODE_TXF_CMS ||
 701            opcode == SHADER_OPCODE_TXF_CMS_W ||
 702            opcode == SHADER_OPCODE_TXF_UMS ||
 703            opcode == SHADER_OPCODE_TXF_MCS ||
 704            opcode == SHADER_OPCODE_TXL ||
 705            opcode == SHADER_OPCODE_TXS ||
 706            opcode == SHADER_OPCODE_LOD ||
 707            opcode == SHADER_OPCODE_TG4 ||
 708            opcode == SHADER_OPCODE_TG4_OFFSET);
 709 }
 710
 711 bool
 712 backend_instruction::is_math() const
 713 {
 714    return (opcode == SHADER_OPCODE_RCP ||
 715            opcode == SHADER_OPCODE_RSQ ||
 716            opcode == SHADER_OPCODE_SQRT ||
 717            opcode == SHADER_OPCODE_EXP2 ||
 718            opcode == SHADER_OPCODE_LOG2 ||
 719            opcode == SHADER_OPCODE_SIN ||
 720            opcode == SHADER_OPCODE_COS ||
 721            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 722            opcode == SHADER_OPCODE_INT_REMAINDER ||
 723            opcode == SHADER_OPCODE_POW);
 724 }
 725
 726 bool
 727 backend_instruction::is_control_flow() const
 728 {
 729    switch (opcode) {
 730    case BRW_OPCODE_DO:
 731    case BRW_OPCODE_WHILE:
 732    case BRW_OPCODE_IF:
 733    case BRW_OPCODE_ELSE:
 734    case BRW_OPCODE_ENDIF:
 735    case BRW_OPCODE_BREAK:
 736    case BRW_OPCODE_CONTINUE:
 737       return true;
 738    default:
 739       return false;
 740    }
 741 }
 742
 743 bool
 744 backend_instruction::can_do_source_mods() const
 745 {
 746    switch (opcode) {
 747    case BRW_OPCODE_ADDC:
 748    case BRW_OPCODE_BFE:
 749    case BRW_OPCODE_BFI1:
 750    case BRW_OPCODE_BFI2:
 751    case BRW_OPCODE_BFREV:
 752    case BRW_OPCODE_CBIT:
 753    case BRW_OPCODE_FBH:
 754    case BRW_OPCODE_FBL:
 755    case BRW_OPCODE_SUBB:
 756       return false;
 757    default:
 758       return true;
 759    }
 760 }
 761
 762 bool
 763 backend_instruction::can_do_saturate() const
 764 {
 765    switch (opcode) {
 766    case BRW_OPCODE_ADD:
 767    case BRW_OPCODE_ASR:
 768    case BRW_OPCODE_AVG:
 769    case BRW_OPCODE_DP2:
 770    case BRW_OPCODE_DP3:
 771    case BRW_OPCODE_DP4:
 772    case BRW_OPCODE_DPH:
 773    case BRW_OPCODE_F16TO32:
 774    case BRW_OPCODE_F32TO16:
 775    case BRW_OPCODE_LINE:
 776    case BRW_OPCODE_LRP:
 777    case BRW_OPCODE_MAC:
 778    case BRW_OPCODE_MAD:
 779    case BRW_OPCODE_MATH:
 780    case BRW_OPCODE_MOV:
 781    case BRW_OPCODE_MUL:
 782    case SHADER_OPCODE_MULH:
 783    case BRW_OPCODE_PLN:
 784    case BRW_OPCODE_RNDD:
 785    case BRW_OPCODE_RNDE:
 786    case BRW_OPCODE_RNDU:
 787    case BRW_OPCODE_RNDZ:
 788    case BRW_OPCODE_SEL:
 789    case BRW_OPCODE_SHL:
 790    case BRW_OPCODE_SHR:
 791    case FS_OPCODE_LINTERP:
 792    case SHADER_OPCODE_COS:
 793    case SHADER_OPCODE_EXP2:
 794    case SHADER_OPCODE_LOG2:
 795    case SHADER_OPCODE_POW:
 796    case SHADER_OPCODE_RCP:
 797    case SHADER_OPCODE_RSQ:
 798    case SHADER_OPCODE_SIN:
 799    case SHADER_OPCODE_SQRT:
 800       return true;
 801    default:
 802       return false;
 803    }
 804 }
 805
 806 bool
 807 backend_instruction::can_do_cmod() const
 808 {
 809    switch (opcode) {
 810    case BRW_OPCODE_ADD:
 811    case BRW_OPCODE_ADDC:
 812    case BRW_OPCODE_AND:
 813    case BRW_OPCODE_ASR:
 814    case BRW_OPCODE_AVG:
 815    case BRW_OPCODE_CMP:
 816    case BRW_OPCODE_CMPN:
 817    case BRW_OPCODE_DP2:
 818    case BRW_OPCODE_DP3:
 819    case BRW_OPCODE_DP4:
 820    case BRW_OPCODE_DPH:
 821    case BRW_OPCODE_F16TO32:
 822    case BRW_OPCODE_F32TO16:
 823    case BRW_OPCODE_FRC:
 824    case BRW_OPCODE_LINE:
 825    case BRW_OPCODE_LRP:
 826    case BRW_OPCODE_LZD:
 827    case BRW_OPCODE_MAC:
 828    case BRW_OPCODE_MACH:
 829    case BRW_OPCODE_MAD:
 830    case BRW_OPCODE_MOV:
 831    case BRW_OPCODE_MUL:
 832    case BRW_OPCODE_NOT:
 833    case BRW_OPCODE_OR:
 834    case BRW_OPCODE_PLN:
 835    case BRW_OPCODE_RNDD:
 836    case BRW_OPCODE_RNDE:
 837    case BRW_OPCODE_RNDU:
 838    case BRW_OPCODE_RNDZ:
 839    case BRW_OPCODE_SAD2:
 840    case BRW_OPCODE_SADA2:
 841    case BRW_OPCODE_SHL:
 842    case BRW_OPCODE_SHR:
 843    case BRW_OPCODE_SUBB:
 844    case BRW_OPCODE_XOR:
 845    case FS_OPCODE_CINTERP:
 846    case FS_OPCODE_LINTERP:
 847       return true;
 848    default:
 849       return false;
 850    }
 851 }
 852
 853 bool
 854 backend_instruction::reads_accumulator_implicitly() const
 855 {
 856    switch (opcode) {
 857    case BRW_OPCODE_MAC:
 858    case BRW_OPCODE_MACH:
 859    case BRW_OPCODE_SADA2:
 860       return true;
 861    default:
 862       return false;
 863    }
 864 }
 865
 866 bool
 867 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 868 {
 869    return writes_accumulator ||
 870           (devinfo->gen < 6 &&
 871            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 872             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 873              opcode != FS_OPCODE_CINTERP)));
 874 }
 875
 876 bool
 877 backend_instruction::has_side_effects() const
 878 {
 879    switch (opcode) {
 880    case SHADER_OPCODE_UNTYPED_ATOMIC:
 881    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 882    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 883    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 884    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 885    case SHADER_OPCODE_TYPED_ATOMIC:
 886    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 887    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 888    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 889    case SHADER_OPCODE_MEMORY_FENCE:
 890    case SHADER_OPCODE_URB_WRITE_SIMD8:
 891    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 892    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 893    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 894    case FS_OPCODE_FB_WRITE:
 895    case SHADER_OPCODE_BARRIER:
 896    case TCS_OPCODE_URB_WRITE:
 897    case TCS_OPCODE_RELEASE_INPUT:
 898       return true;
 899    default:
 900       return false;
 901    }
 902 }
 903
 904 bool
 905 backend_instruction::is_volatile() const
 906 {
 907    switch (opcode) {
 908    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 909    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 910    case SHADER_OPCODE_TYPED_SURFACE_READ:
 911    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 912       return true;
 913    default:
 914       return false;
 915    }
 916 }
 917
 918 #ifndef NDEBUG
 919 static bool
 920 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 921 {
 922    bool found = false;
 923    foreach_inst_in_block (backend_instruction, i, block) {
 924       if (inst == i) {
 925          found = true;
 926       }
 927    }
 928    return found;
 929 }
 930 #endif
 931
 932 static void
 933 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 934 {
 935    for (bblock_t *block_iter = start_block->next();
 936         !block_iter->link.is_tail_sentinel();
 937         block_iter = block_iter->next()) {
 938       block_iter->start_ip += ip_adjustment;
 939       block_iter->end_ip += ip_adjustment;
 940    }
 941 }
 942
 943 void
 944 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
 945 {
 946    if (!this->is_head_sentinel())
 947       assert(inst_is_in_block(block, this) || !"Instruction not in block");
 948
 949    block->end_ip++;
 950
 951    adjust_later_block_ips(block, 1);
 952
 953    exec_node::insert_after(inst);
 954 }
 955
 956 void
 957 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
 958 {
 959    if (!this->is_tail_sentinel())
 960       assert(inst_is_in_block(block, this) || !"Instruction not in block");
 961
 962    block->end_ip++;
 963
 964    adjust_later_block_ips(block, 1);
 965
 966    exec_node::insert_before(inst);
 967 }
 968
 969 void
 970 backend_instruction::insert_before(bblock_t *block, exec_list *list)
 971 {
 972    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 973
 974    unsigned num_inst = list->length();
 975
 976    block->end_ip += num_inst;
 977
 978    adjust_later_block_ips(block, num_inst);
 979
 980    exec_node::insert_before(list);
 981 }
 982
 983 void
 984 backend_instruction::remove(bblock_t *block)
 985 {
 986    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 987
 988    adjust_later_block_ips(block, -1);
 989
 990    if (block->start_ip == block->end_ip) {
 991       block->cfg->remove_block(block);
 992    } else {
 993       block->end_ip--;
 994    }
 995
 996    exec_node::remove();
 997 }
 998
 999 void
1000 backend_shader::dump_instructions()
1001 {
1002    dump_instructions(NULL);
1003 }
1004
1005 void
1006 backend_shader::dump_instructions(const char *name)
1007 {
1008    FILE *file = stderr;
1009    if (name && geteuid() != 0) {
1010       file = fopen(name, "w");
1011       if (!file)
1012          file = stderr;
1013    }
1014
1015    if (cfg) {
1016       int ip = 0;
1017       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1018          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1019             fprintf(file, "%4d: ", ip++);
1020          dump_instruction(inst, file);
1021       }
1022    } else {
1023       int ip = 0;
1024       foreach_in_list(backend_instruction, inst, &instructions) {
1025          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1026             fprintf(file, "%4d: ", ip++);
1027          dump_instruction(inst, file);
1028       }
1029    }
1030
1031    if (file != stderr) {
1032       fclose(file);
1033    }
1034 }
1035
1036 void
1037 backend_shader::calculate_cfg()
1038 {
1039    if (this->cfg)
1040       return;
1041    cfg = new(mem_ctx) cfg_t(&this->instructions);
1042 }
1043
1044 void
1045 backend_shader::invalidate_cfg()
1046 {
1047    ralloc_free(this->cfg);
1048    this->cfg = NULL;
1049 }
1050
1051 /**
1052  * Sets up the starting offsets for the groups of binding table entries
1053  * commong to all pipeline stages.
1054  *
1055  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1056  * unused but also make sure that addition of small offsets to them will
1057  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1058  */
1059 void
1060 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1061                                         const struct brw_device_info *devinfo,
1062                                         const struct gl_shader_program *shader_prog,
1063                                         const struct gl_program *prog,
1064                                         struct brw_stage_prog_data *stage_prog_data,
1065                                         uint32_t next_binding_table_offset)
1066 {
1067    const struct gl_shader *shader = NULL;
1068    int num_textures = _mesa_fls(prog->SamplersUsed);
1069
1070    if (shader_prog)
1071       shader = shader_prog->_LinkedShaders[stage];
1072
1073    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1074    next_binding_table_offset += num_textures;
1075
1076    if (shader) {
1077       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1078       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1079       next_binding_table_offset += shader->NumUniformBlocks;
1080
1081       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1082       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1083       next_binding_table_offset += shader->NumShaderStorageBlocks;
1084    } else {
1085       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1086       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1087    }
1088
1089    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1090       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1091       next_binding_table_offset++;
1092    } else {
1093       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1094    }
1095
1096    if (prog->UsesGather) {
1097       if (devinfo->gen >= 8) {
1098          stage_prog_data->binding_table.gather_texture_start =
1099             stage_prog_data->binding_table.texture_start;
1100       } else {
1101          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1102          next_binding_table_offset += num_textures;
1103       }
1104    } else {
1105       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1106    }
1107
1108    if (shader && shader->NumAtomicBuffers) {
1109       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1110       next_binding_table_offset += shader->NumAtomicBuffers;
1111    } else {
1112       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1113    }
1114
1115    if (shader && shader->NumImages) {
1116       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1117       next_binding_table_offset += shader->NumImages;
1118    } else {
1119       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1120    }
1121
1122    /* This may or may not be used depending on how the compile goes. */
1123    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1124    next_binding_table_offset++;
1125
1126    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1127
1128    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1129 }
1130
1131 static void
1132 setup_vec4_uniform_value(const gl_constant_value **params,
1133                          const gl_constant_value *values,
1134                          unsigned n)
1135 {
1136    static const gl_constant_value zero = { 0 };
1137
1138    for (unsigned i = 0; i < n; ++i)
1139       params[i] = &values[i];
1140
1141    for (unsigned i = n; i < 4; ++i)
1142       params[i] = &zero;
1143 }
1144
1145 void
1146 brw_setup_image_uniform_values(gl_shader_stage stage,
1147                                struct brw_stage_prog_data *stage_prog_data,
1148                                unsigned param_start_index,
1149                                const gl_uniform_storage *storage)
1150 {
1151    const gl_constant_value **param =
1152       &stage_prog_data->param[param_start_index];
1153
1154    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1155       const unsigned image_idx = storage->opaque[stage].index + i;
1156       const brw_image_param *image_param =
1157          &stage_prog_data->image_param[image_idx];
1158
1159       /* Upload the brw_image_param structure.  The order is expected to match
1160        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1161        */
1162       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1163          (const gl_constant_value *)&image_param->surface_idx, 1);
1164       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1165          (const gl_constant_value *)image_param->offset, 2);
1166       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1167          (const gl_constant_value *)image_param->size, 3);
1168       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1169          (const gl_constant_value *)image_param->stride, 4);
1170       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1171          (const gl_constant_value *)image_param->tiling, 3);
1172       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1173          (const gl_constant_value *)image_param->swizzling, 2);
1174       param += BRW_IMAGE_PARAM_SIZE;
1175
1176       brw_mark_surface_used(
1177          stage_prog_data,
1178          stage_prog_data->binding_table.image_start + image_idx);
1179    }
1180 }
1181
1182 /**
1183  * Decide which set of clip planes should be used when clipping via
1184  * gl_Position or gl_ClipVertex.
1185  */
1186 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1187 {
1188    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1189       /* There is currently a GLSL vertex shader, so clip according to GLSL
1190        * rules, which means compare gl_ClipVertex (or gl_Position, if
1191        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1192        * that were stored in EyeUserPlane at the time the clip planes were
1193        * specified.
1194        */
1195       return ctx->Transform.EyeUserPlane;
1196    } else {
1197       /* Either we are using fixed function or an ARB vertex program.  In
1198        * either case the clip planes are going to be compared against
1199        * gl_Position (which is in clip coordinates) so we have to clip using
1200        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1201        * core.
1202        */
1203       return ctx->Transform._ClipUserPlane;
1204    }
1205 }
1206
1207 extern "C" const unsigned *
1208 brw_compile_tes(const struct brw_compiler *compiler,
1209                 void *log_data,
1210                 void *mem_ctx,
1211                 const struct brw_tes_prog_key *key,
1212                 struct brw_tes_prog_data *prog_data,
1213                 const nir_shader *src_shader,
1214                 struct gl_shader_program *shader_prog,
1215                 int shader_time_index,
1216                 unsigned *final_assembly_size,
1217                 char **error_str)
1218 {
1219    const struct brw_device_info *devinfo = compiler->devinfo;
1220    struct gl_shader *shader =
1221       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1222    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1223
1224    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1225    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1226    nir->info.inputs_read = key->inputs_read;
1227    nir->info.patch_inputs_read = key->patch_inputs_read;
1228    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
1229    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1230
1231    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1232                        nir->info.outputs_written,
1233                        nir->info.separate_shader);
1234
1235    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1236
1237    assert(output_size_bytes >= 1);
1238    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1239       if (error_str)
1240          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1241       return NULL;
1242    }
1243
1244    /* URB entry sizes are stored as a multiple of 64 bytes. */
1245    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1246
1247    struct brw_vue_map input_vue_map;
1248    brw_compute_tess_vue_map(&input_vue_map,
1249                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1250                             nir->info.patch_inputs_read);
1251
1252    bool need_patch_header = nir->info.system_values_read &
1253       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1254        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1255
1256    /* The TES will pull most inputs using URB read messages.
1257     *
1258     * However, we push the patch header for TessLevel factors when required,
1259     * as it's a tiny amount of extra data.
1260     */
1261    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1262
1263    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1264       fprintf(stderr, "TES Input ");
1265       brw_print_vue_map(stderr, &input_vue_map);
1266       fprintf(stderr, "TES Output ");
1267       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1268    }
1269
1270    if (is_scalar) {
1271       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1272                    &prog_data->base.base, shader->Program, nir, 8,
1273                    shader_time_index, &input_vue_map);
1274       if (!v.run_tes()) {
1275          if (error_str)
1276             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1277          return NULL;
1278       }
1279
1280       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1281
1282       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1283                      &prog_data->base.base, v.promoted_constants, false,
1284                      MESA_SHADER_TESS_EVAL);
1285       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1286          g.enable_debug(ralloc_asprintf(mem_ctx,
1287                                         "%s tessellation evaluation shader %s",
1288                                         nir->info.label ? nir->info.label
1289                                                         : "unnamed",
1290                                         nir->info.name));
1291       }
1292
1293       g.generate_code(v.cfg, 8);
1294
1295       return g.get_assembly(final_assembly_size);
1296    } else {
1297       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1298                               nir, mem_ctx, shader_time_index);
1299       if (!v.run()) {
1300          if (error_str)
1301             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1302          return NULL;
1303       }
1304
1305       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1306          v.dump_instructions();
1307
1308       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1309                                         &prog_data->base, v.cfg,
1310                                         final_assembly_size);
1311    }
1312 }