2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/macros.h"
26 #include "brw_context.h"
32 #include "glsl/ir_optimization.h"
33 #include "glsl/glsl_parser_extras.h"
34 #include "main/shaderapi.h"
37 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
39 struct brw_shader
*shader
;
41 shader
= rzalloc(NULL
, struct brw_shader
);
43 shader
->base
.Type
= type
;
44 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
45 shader
->base
.Name
= name
;
46 _mesa_init_shader(ctx
, &shader
->base
);
53 * Performs a compile of the shader stages even when we don't know
54 * what non-orthogonal state will be set, in the hope that it reflects
55 * the eventual NOS used, and thus allows us to produce link failures.
58 brw_shader_precompile(struct gl_context
*ctx
,
59 struct gl_shader_program
*sh_prog
)
61 struct gl_shader
*vs
= sh_prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
62 struct gl_shader
*gs
= sh_prog
->_LinkedShaders
[MESA_SHADER_GEOMETRY
];
63 struct gl_shader
*fs
= sh_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
65 if (fs
&& !brw_fs_precompile(ctx
, sh_prog
, fs
->Program
))
68 if (gs
&& !brw_gs_precompile(ctx
, sh_prog
, gs
->Program
))
71 if (vs
&& !brw_vs_precompile(ctx
, sh_prog
, vs
->Program
))
78 is_scalar_shader_stage(struct brw_context
*brw
, int stage
)
81 case MESA_SHADER_FRAGMENT
:
83 case MESA_SHADER_VERTEX
:
84 return brw
->scalar_vs
;
91 brw_lower_packing_builtins(struct brw_context
*brw
,
92 gl_shader_stage shader_type
,
95 int ops
= LOWER_PACK_SNORM_2x16
96 | LOWER_UNPACK_SNORM_2x16
97 | LOWER_PACK_UNORM_2x16
98 | LOWER_UNPACK_UNORM_2x16
;
100 if (is_scalar_shader_stage(brw
, shader_type
)) {
101 ops
|= LOWER_UNPACK_UNORM_4x8
102 | LOWER_UNPACK_SNORM_4x8
103 | LOWER_PACK_UNORM_4x8
104 | LOWER_PACK_SNORM_4x8
;
108 /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
109 * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
110 * lowering is needed. For SOA code, the Half2x16 ops must be
113 if (is_scalar_shader_stage(brw
, shader_type
)) {
114 ops
|= LOWER_PACK_HALF_2x16_TO_SPLIT
115 | LOWER_UNPACK_HALF_2x16_TO_SPLIT
;
118 ops
|= LOWER_PACK_HALF_2x16
119 | LOWER_UNPACK_HALF_2x16
;
122 lower_packing_builtins(ir
, ops
);
126 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*shProg
)
128 struct brw_context
*brw
= brw_context(ctx
);
131 for (stage
= 0; stage
< ARRAY_SIZE(shProg
->_LinkedShaders
); stage
++) {
132 const struct gl_shader_compiler_options
*options
=
133 &ctx
->Const
.ShaderCompilerOptions
[stage
];
134 struct brw_shader
*shader
=
135 (struct brw_shader
*)shProg
->_LinkedShaders
[stage
];
140 struct gl_program
*prog
=
141 ctx
->Driver
.NewProgram(ctx
, _mesa_shader_stage_to_program(stage
),
145 prog
->Parameters
= _mesa_new_parameter_list();
147 _mesa_copy_linked_program_data((gl_shader_stage
) stage
, shProg
, prog
);
151 /* lower_packing_builtins() inserts arithmetic instructions, so it
152 * must precede lower_instructions().
154 brw_lower_packing_builtins(brw
, (gl_shader_stage
) stage
, shader
->base
.ir
);
155 do_mat_op_to_vec(shader
->base
.ir
);
156 const int bitfield_insert
= brw
->gen
>= 7
157 ? BITFIELD_INSERT_TO_BFM_BFI
159 lower_instructions(shader
->base
.ir
,
168 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
169 * if-statements need to be flattened.
172 lower_if_to_cond_assign(shader
->base
.ir
, 16);
174 do_lower_texture_projection(shader
->base
.ir
);
175 brw_lower_texture_gradients(brw
, shader
->base
.ir
);
176 do_vec_index_to_cond_assign(shader
->base
.ir
);
177 lower_vector_insert(shader
->base
.ir
, true);
178 brw_do_cubemap_normalize(shader
->base
.ir
);
179 lower_offset_arrays(shader
->base
.ir
);
180 brw_do_lower_unnormalized_offset(shader
->base
.ir
);
181 lower_noise(shader
->base
.ir
);
182 lower_quadop_vector(shader
->base
.ir
, false);
184 bool lowered_variable_indexing
=
185 lower_variable_index_to_cond_assign(shader
->base
.ir
,
186 options
->EmitNoIndirectInput
,
187 options
->EmitNoIndirectOutput
,
188 options
->EmitNoIndirectTemp
,
189 options
->EmitNoIndirectUniform
);
191 if (unlikely(brw
->perf_debug
&& lowered_variable_indexing
)) {
192 perf_debug("Unsupported form of variable indexing in FS; falling "
193 "back to very inefficient code generation\n");
196 lower_ubo_reference(&shader
->base
, shader
->base
.ir
);
201 if (is_scalar_shader_stage(brw
, stage
)) {
202 brw_do_channel_expressions(shader
->base
.ir
);
203 brw_do_vector_splitting(shader
->base
.ir
);
206 progress
= do_lower_jumps(shader
->base
.ir
, true, true,
207 true, /* main return */
208 false, /* continue */
212 progress
= do_common_optimization(shader
->base
.ir
, true, true,
213 options
, ctx
->Const
.NativeIntegers
)
217 /* Make a pass over the IR to add state references for any built-in
218 * uniforms that are used. This has to be done now (during linking).
219 * Code generation doesn't happen until the first time this shader is
220 * used for rendering. Waiting until then to generate the parameters is
221 * too late. At that point, the values for the built-in uniforms won't
222 * get sent to the shader.
224 foreach_in_list(ir_instruction
, node
, shader
->base
.ir
) {
225 ir_variable
*var
= node
->as_variable();
227 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
228 || (strncmp(var
->name
, "gl_", 3) != 0))
231 const ir_state_slot
*const slots
= var
->get_state_slots();
232 assert(slots
!= NULL
);
234 for (unsigned int i
= 0; i
< var
->get_num_state_slots(); i
++) {
235 _mesa_add_state_reference(prog
->Parameters
,
236 (gl_state_index
*) slots
[i
].tokens
);
240 validate_ir_tree(shader
->base
.ir
);
242 do_set_program_inouts(shader
->base
.ir
, prog
, shader
->base
.Stage
);
244 prog
->SamplersUsed
= shader
->base
.active_samplers
;
245 prog
->ShadowSamplers
= shader
->base
.shadow_samplers
;
246 _mesa_update_shader_textures_used(shProg
, prog
);
248 _mesa_reference_program(ctx
, &shader
->base
.Program
, prog
);
250 brw_add_texrect_params(prog
);
252 _mesa_reference_program(ctx
, &prog
, NULL
);
254 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
255 fprintf(stderr
, "\n");
256 fprintf(stderr
, "GLSL IR for linked %s program %d:\n",
257 _mesa_shader_stage_to_string(shader
->base
.Stage
),
259 _mesa_print_ir(stderr
, shader
->base
.ir
, NULL
);
260 fprintf(stderr
, "\n");
264 if ((ctx
->_Shader
->Flags
& GLSL_DUMP
) && shProg
->Name
!= 0) {
265 for (unsigned i
= 0; i
< shProg
->NumShaders
; i
++) {
266 const struct gl_shader
*sh
= shProg
->Shaders
[i
];
270 fprintf(stderr
, "GLSL %s shader %d source for linked program %d:\n",
271 _mesa_shader_stage_to_string(sh
->Stage
),
273 fprintf(stderr
, "%s", sh
->Source
);
274 fprintf(stderr
, "\n");
278 if (brw
->precompile
&& !brw_shader_precompile(ctx
, shProg
))
286 brw_type_for_base_type(const struct glsl_type
*type
)
288 switch (type
->base_type
) {
289 case GLSL_TYPE_FLOAT
:
290 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_D
;
295 return BRW_REGISTER_TYPE_UD
;
296 case GLSL_TYPE_ARRAY
:
297 return brw_type_for_base_type(type
->fields
.array
);
298 case GLSL_TYPE_STRUCT
:
299 case GLSL_TYPE_SAMPLER
:
300 case GLSL_TYPE_ATOMIC_UINT
:
301 /* These should be overridden with the type of the member when
302 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
303 * way to trip up if we don't.
305 return BRW_REGISTER_TYPE_UD
;
306 case GLSL_TYPE_IMAGE
:
307 return BRW_REGISTER_TYPE_UD
;
309 case GLSL_TYPE_ERROR
:
310 case GLSL_TYPE_INTERFACE
:
311 unreachable("not reached");
314 return BRW_REGISTER_TYPE_F
;
317 enum brw_conditional_mod
318 brw_conditional_for_comparison(unsigned int op
)
322 return BRW_CONDITIONAL_L
;
323 case ir_binop_greater
:
324 return BRW_CONDITIONAL_G
;
325 case ir_binop_lequal
:
326 return BRW_CONDITIONAL_LE
;
327 case ir_binop_gequal
:
328 return BRW_CONDITIONAL_GE
;
330 case ir_binop_all_equal
: /* same as equal for scalars */
331 return BRW_CONDITIONAL_Z
;
332 case ir_binop_nequal
:
333 case ir_binop_any_nequal
: /* same as nequal for scalars */
334 return BRW_CONDITIONAL_NZ
;
336 unreachable("not reached: bad operation for comparison");
341 brw_math_function(enum opcode op
)
344 case SHADER_OPCODE_RCP
:
345 return BRW_MATH_FUNCTION_INV
;
346 case SHADER_OPCODE_RSQ
:
347 return BRW_MATH_FUNCTION_RSQ
;
348 case SHADER_OPCODE_SQRT
:
349 return BRW_MATH_FUNCTION_SQRT
;
350 case SHADER_OPCODE_EXP2
:
351 return BRW_MATH_FUNCTION_EXP
;
352 case SHADER_OPCODE_LOG2
:
353 return BRW_MATH_FUNCTION_LOG
;
354 case SHADER_OPCODE_POW
:
355 return BRW_MATH_FUNCTION_POW
;
356 case SHADER_OPCODE_SIN
:
357 return BRW_MATH_FUNCTION_SIN
;
358 case SHADER_OPCODE_COS
:
359 return BRW_MATH_FUNCTION_COS
;
360 case SHADER_OPCODE_INT_QUOTIENT
:
361 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
362 case SHADER_OPCODE_INT_REMAINDER
:
363 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
365 unreachable("not reached: unknown math function");
370 brw_texture_offset(struct gl_context
*ctx
, int *offsets
,
371 unsigned num_components
)
373 /* If the driver does not support GL_ARB_gpu_shader5, the offset
376 assert(offsets
!= NULL
|| ctx
->Extensions
.ARB_gpu_shader5
);
378 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
380 /* Combine all three offsets into a single unsigned dword:
382 * bits 11:8 - U Offset (X component)
383 * bits 7:4 - V Offset (Y component)
384 * bits 3:0 - R Offset (Z component)
386 unsigned offset_bits
= 0;
387 for (unsigned i
= 0; i
< num_components
; i
++) {
388 const unsigned shift
= 4 * (2 - i
);
389 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
395 brw_instruction_name(enum opcode op
)
398 case BRW_OPCODE_MOV
... BRW_OPCODE_NOP
:
399 assert(opcode_descs
[op
].name
);
400 return opcode_descs
[op
].name
;
401 case FS_OPCODE_FB_WRITE
:
403 case FS_OPCODE_BLORP_FB_WRITE
:
404 return "blorp_fb_write";
405 case FS_OPCODE_REP_FB_WRITE
:
406 return "rep_fb_write";
408 case SHADER_OPCODE_RCP
:
410 case SHADER_OPCODE_RSQ
:
412 case SHADER_OPCODE_SQRT
:
414 case SHADER_OPCODE_EXP2
:
416 case SHADER_OPCODE_LOG2
:
418 case SHADER_OPCODE_POW
:
420 case SHADER_OPCODE_INT_QUOTIENT
:
422 case SHADER_OPCODE_INT_REMAINDER
:
424 case SHADER_OPCODE_SIN
:
426 case SHADER_OPCODE_COS
:
429 case SHADER_OPCODE_TEX
:
431 case SHADER_OPCODE_TXD
:
433 case SHADER_OPCODE_TXF
:
435 case SHADER_OPCODE_TXL
:
437 case SHADER_OPCODE_TXS
:
441 case SHADER_OPCODE_TXF_CMS
:
443 case SHADER_OPCODE_TXF_UMS
:
445 case SHADER_OPCODE_TXF_MCS
:
447 case SHADER_OPCODE_LOD
:
449 case SHADER_OPCODE_TG4
:
451 case SHADER_OPCODE_TG4_OFFSET
:
453 case SHADER_OPCODE_SHADER_TIME_ADD
:
454 return "shader_time_add";
456 case SHADER_OPCODE_UNTYPED_ATOMIC
:
457 return "untyped_atomic";
458 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
459 return "untyped_surface_read";
461 case SHADER_OPCODE_LOAD_PAYLOAD
:
462 return "load_payload";
464 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
465 return "gen4_scratch_read";
466 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
467 return "gen4_scratch_write";
468 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
469 return "gen7_scratch_read";
470 case SHADER_OPCODE_URB_WRITE_SIMD8
:
471 return "gen8_urb_write_simd8";
473 case VEC4_OPCODE_PACK_BYTES
:
475 case VEC4_OPCODE_UNPACK_UNIFORM
:
476 return "unpack_uniform";
478 case FS_OPCODE_DDX_COARSE
:
480 case FS_OPCODE_DDX_FINE
:
482 case FS_OPCODE_DDY_COARSE
:
484 case FS_OPCODE_DDY_FINE
:
487 case FS_OPCODE_PIXEL_X
:
489 case FS_OPCODE_PIXEL_Y
:
492 case FS_OPCODE_CINTERP
:
494 case FS_OPCODE_LINTERP
:
497 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
498 return "uniform_pull_const";
499 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
500 return "uniform_pull_const_gen7";
501 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
502 return "varying_pull_const";
503 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
504 return "varying_pull_const_gen7";
506 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
507 return "mov_dispatch_to_flags";
508 case FS_OPCODE_DISCARD_JUMP
:
509 return "discard_jump";
511 case FS_OPCODE_SET_OMASK
:
513 case FS_OPCODE_SET_SAMPLE_ID
:
514 return "set_sample_id";
515 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
516 return "set_simd4x2_offset";
518 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
519 return "pack_half_2x16_split";
520 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
521 return "unpack_half_2x16_split_x";
522 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
523 return "unpack_half_2x16_split_y";
525 case FS_OPCODE_PLACEHOLDER_HALT
:
526 return "placeholder_halt";
528 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
529 return "interp_centroid";
530 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
531 return "interp_sample";
532 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
533 return "interp_shared_offset";
534 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
535 return "interp_per_slot_offset";
537 case VS_OPCODE_URB_WRITE
:
538 return "vs_urb_write";
539 case VS_OPCODE_PULL_CONSTANT_LOAD
:
540 return "pull_constant_load";
541 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
542 return "pull_constant_load_gen7";
543 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
544 return "unpack_flags_simd4x2";
546 case GS_OPCODE_URB_WRITE
:
547 return "gs_urb_write";
548 case GS_OPCODE_URB_WRITE_ALLOCATE
:
549 return "gs_urb_write_allocate";
550 case GS_OPCODE_THREAD_END
:
551 return "gs_thread_end";
552 case GS_OPCODE_SET_WRITE_OFFSET
:
553 return "set_write_offset";
554 case GS_OPCODE_SET_VERTEX_COUNT
:
555 return "set_vertex_count";
556 case GS_OPCODE_SET_DWORD_2
:
557 return "set_dword_2";
558 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
559 return "prepare_channel_masks";
560 case GS_OPCODE_SET_CHANNEL_MASKS
:
561 return "set_channel_masks";
562 case GS_OPCODE_GET_INSTANCE_ID
:
563 return "get_instance_id";
564 case GS_OPCODE_FF_SYNC
:
566 case GS_OPCODE_SET_PRIMITIVE_ID
:
567 return "set_primitive_id";
568 case GS_OPCODE_SVB_WRITE
:
569 return "gs_svb_write";
570 case GS_OPCODE_SVB_SET_DST_INDEX
:
571 return "gs_svb_set_dst_index";
572 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
573 return "gs_ff_sync_set_primitives";
576 unreachable("not reached");
580 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
586 } imm
= { reg
->dw1
.ud
}, sat_imm
;
589 case BRW_REGISTER_TYPE_UD
:
590 case BRW_REGISTER_TYPE_D
:
591 case BRW_REGISTER_TYPE_UQ
:
592 case BRW_REGISTER_TYPE_Q
:
595 case BRW_REGISTER_TYPE_UW
:
596 sat_imm
.ud
= CLAMP(imm
.ud
, 0, USHRT_MAX
);
598 case BRW_REGISTER_TYPE_W
:
599 sat_imm
.d
= CLAMP(imm
.d
, SHRT_MIN
, SHRT_MAX
);
601 case BRW_REGISTER_TYPE_F
:
602 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
604 case BRW_REGISTER_TYPE_UB
:
605 case BRW_REGISTER_TYPE_B
:
606 unreachable("no UB/B immediates");
607 case BRW_REGISTER_TYPE_V
:
608 case BRW_REGISTER_TYPE_UV
:
609 case BRW_REGISTER_TYPE_VF
:
610 assert(!"unimplemented: saturate vector immediate");
611 case BRW_REGISTER_TYPE_DF
:
612 case BRW_REGISTER_TYPE_HF
:
613 assert(!"unimplemented: saturate DF/HF immediate");
616 if (imm
.ud
!= sat_imm
.ud
) {
617 reg
->dw1
.ud
= sat_imm
.ud
;
624 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
627 case BRW_REGISTER_TYPE_D
:
628 case BRW_REGISTER_TYPE_UD
:
629 reg
->dw1
.d
= -reg
->dw1
.d
;
631 case BRW_REGISTER_TYPE_W
:
632 case BRW_REGISTER_TYPE_UW
:
633 reg
->dw1
.d
= -(int16_t)reg
->dw1
.ud
;
635 case BRW_REGISTER_TYPE_F
:
636 reg
->dw1
.f
= -reg
->dw1
.f
;
638 case BRW_REGISTER_TYPE_VF
:
639 reg
->dw1
.ud
^= 0x80808080;
641 case BRW_REGISTER_TYPE_UB
:
642 case BRW_REGISTER_TYPE_B
:
643 unreachable("no UB/B immediates");
644 case BRW_REGISTER_TYPE_UV
:
645 case BRW_REGISTER_TYPE_V
:
646 assert(!"unimplemented: negate UV/V immediate");
647 case BRW_REGISTER_TYPE_UQ
:
648 case BRW_REGISTER_TYPE_Q
:
649 assert(!"unimplemented: negate UQ/Q immediate");
650 case BRW_REGISTER_TYPE_DF
:
651 case BRW_REGISTER_TYPE_HF
:
652 assert(!"unimplemented: negate DF/HF immediate");
659 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
662 case BRW_REGISTER_TYPE_D
:
663 reg
->dw1
.d
= abs(reg
->dw1
.d
);
665 case BRW_REGISTER_TYPE_W
:
666 reg
->dw1
.d
= abs((int16_t)reg
->dw1
.ud
);
668 case BRW_REGISTER_TYPE_F
:
669 reg
->dw1
.f
= fabsf(reg
->dw1
.f
);
671 case BRW_REGISTER_TYPE_VF
:
672 reg
->dw1
.ud
&= ~0x80808080;
674 case BRW_REGISTER_TYPE_UB
:
675 case BRW_REGISTER_TYPE_B
:
676 unreachable("no UB/B immediates");
677 case BRW_REGISTER_TYPE_UQ
:
678 case BRW_REGISTER_TYPE_UD
:
679 case BRW_REGISTER_TYPE_UW
:
680 case BRW_REGISTER_TYPE_UV
:
681 /* Presumably the absolute value modifier on an unsigned source is a
682 * nop, but it would be nice to confirm.
684 assert(!"unimplemented: abs unsigned immediate");
685 case BRW_REGISTER_TYPE_V
:
686 assert(!"unimplemented: abs V immediate");
687 case BRW_REGISTER_TYPE_Q
:
688 assert(!"unimplemented: abs Q immediate");
689 case BRW_REGISTER_TYPE_DF
:
690 case BRW_REGISTER_TYPE_HF
:
691 assert(!"unimplemented: abs DF/HF immediate");
697 backend_visitor::backend_visitor(struct brw_context
*brw
,
698 struct gl_shader_program
*shader_prog
,
699 struct gl_program
*prog
,
700 struct brw_stage_prog_data
*stage_prog_data
,
701 gl_shader_stage stage
)
705 (struct brw_shader
*)shader_prog
->_LinkedShaders
[stage
] : NULL
),
706 shader_prog(shader_prog
),
708 stage_prog_data(stage_prog_data
),
715 backend_reg::is_zero() const
720 return fixed_hw_reg
.dw1
.d
== 0;
724 backend_reg::is_one() const
729 return type
== BRW_REGISTER_TYPE_F
730 ? fixed_hw_reg
.dw1
.f
== 1.0
731 : fixed_hw_reg
.dw1
.d
== 1;
735 backend_reg::is_null() const
737 return file
== HW_REG
&&
738 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
739 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
744 backend_reg::is_accumulator() const
746 return file
== HW_REG
&&
747 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
748 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
752 backend_instruction::is_3src() const
754 return opcode
< ARRAY_SIZE(opcode_descs
) && opcode_descs
[opcode
].nsrc
== 3;
758 backend_instruction::is_tex() const
760 return (opcode
== SHADER_OPCODE_TEX
||
761 opcode
== FS_OPCODE_TXB
||
762 opcode
== SHADER_OPCODE_TXD
||
763 opcode
== SHADER_OPCODE_TXF
||
764 opcode
== SHADER_OPCODE_TXF_CMS
||
765 opcode
== SHADER_OPCODE_TXF_UMS
||
766 opcode
== SHADER_OPCODE_TXF_MCS
||
767 opcode
== SHADER_OPCODE_TXL
||
768 opcode
== SHADER_OPCODE_TXS
||
769 opcode
== SHADER_OPCODE_LOD
||
770 opcode
== SHADER_OPCODE_TG4
||
771 opcode
== SHADER_OPCODE_TG4_OFFSET
);
775 backend_instruction::is_math() const
777 return (opcode
== SHADER_OPCODE_RCP
||
778 opcode
== SHADER_OPCODE_RSQ
||
779 opcode
== SHADER_OPCODE_SQRT
||
780 opcode
== SHADER_OPCODE_EXP2
||
781 opcode
== SHADER_OPCODE_LOG2
||
782 opcode
== SHADER_OPCODE_SIN
||
783 opcode
== SHADER_OPCODE_COS
||
784 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
785 opcode
== SHADER_OPCODE_INT_REMAINDER
||
786 opcode
== SHADER_OPCODE_POW
);
790 backend_instruction::is_control_flow() const
794 case BRW_OPCODE_WHILE
:
796 case BRW_OPCODE_ELSE
:
797 case BRW_OPCODE_ENDIF
:
798 case BRW_OPCODE_BREAK
:
799 case BRW_OPCODE_CONTINUE
:
807 backend_instruction::can_do_source_mods() const
810 case BRW_OPCODE_ADDC
:
812 case BRW_OPCODE_BFI1
:
813 case BRW_OPCODE_BFI2
:
814 case BRW_OPCODE_BFREV
:
815 case BRW_OPCODE_CBIT
:
818 case BRW_OPCODE_SUBB
:
826 backend_instruction::can_do_saturate() const
836 case BRW_OPCODE_F16TO32
:
837 case BRW_OPCODE_F32TO16
:
838 case BRW_OPCODE_LINE
:
841 case BRW_OPCODE_MACH
:
843 case BRW_OPCODE_MATH
:
847 case BRW_OPCODE_RNDD
:
848 case BRW_OPCODE_RNDE
:
849 case BRW_OPCODE_RNDU
:
850 case BRW_OPCODE_RNDZ
:
854 case FS_OPCODE_LINTERP
:
855 case SHADER_OPCODE_COS
:
856 case SHADER_OPCODE_EXP2
:
857 case SHADER_OPCODE_LOG2
:
858 case SHADER_OPCODE_POW
:
859 case SHADER_OPCODE_RCP
:
860 case SHADER_OPCODE_RSQ
:
861 case SHADER_OPCODE_SIN
:
862 case SHADER_OPCODE_SQRT
:
870 backend_instruction::can_do_cmod() const
874 case BRW_OPCODE_ADDC
:
879 case BRW_OPCODE_CMPN
:
884 case BRW_OPCODE_F16TO32
:
885 case BRW_OPCODE_F32TO16
:
887 case BRW_OPCODE_LINE
:
891 case BRW_OPCODE_MACH
:
898 case BRW_OPCODE_RNDD
:
899 case BRW_OPCODE_RNDE
:
900 case BRW_OPCODE_RNDU
:
901 case BRW_OPCODE_RNDZ
:
902 case BRW_OPCODE_SAD2
:
903 case BRW_OPCODE_SADA2
:
906 case BRW_OPCODE_SUBB
:
915 backend_instruction::reads_accumulator_implicitly() const
919 case BRW_OPCODE_MACH
:
920 case BRW_OPCODE_SADA2
:
928 backend_instruction::writes_accumulator_implicitly(struct brw_context
*brw
) const
930 return writes_accumulator
||
932 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
933 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
934 opcode
!= FS_OPCODE_CINTERP
)));
938 backend_instruction::has_side_effects() const
941 case SHADER_OPCODE_UNTYPED_ATOMIC
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8
:
943 case FS_OPCODE_FB_WRITE
:
952 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
955 foreach_inst_in_block (backend_instruction
, i
, block
) {
965 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
967 for (bblock_t
*block_iter
= start_block
->next();
968 !block_iter
->link
.is_tail_sentinel();
969 block_iter
= block_iter
->next()) {
970 block_iter
->start_ip
+= ip_adjustment
;
971 block_iter
->end_ip
+= ip_adjustment
;
976 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
978 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
982 adjust_later_block_ips(block
, 1);
984 exec_node::insert_after(inst
);
988 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
990 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
994 adjust_later_block_ips(block
, 1);
996 exec_node::insert_before(inst
);
1000 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1002 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1004 unsigned num_inst
= list
->length();
1006 block
->end_ip
+= num_inst
;
1008 adjust_later_block_ips(block
, num_inst
);
1010 exec_node::insert_before(list
);
1014 backend_instruction::remove(bblock_t
*block
)
1016 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1018 adjust_later_block_ips(block
, -1);
1020 if (block
->start_ip
== block
->end_ip
) {
1021 block
->cfg
->remove_block(block
);
1026 exec_node::remove();
1030 backend_visitor::dump_instructions()
1032 dump_instructions(NULL
);
1036 backend_visitor::dump_instructions(const char *name
)
1038 FILE *file
= stderr
;
1039 if (name
&& geteuid() != 0) {
1040 file
= fopen(name
, "w");
1046 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1048 fprintf(stderr
, "%d: ", ip
++);
1049 dump_instruction(inst
, file
);
1052 if (file
!= stderr
) {
1058 backend_visitor::calculate_cfg()
1062 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1066 backend_visitor::invalidate_cfg()
1068 ralloc_free(this->cfg
);
1073 * Sets up the starting offsets for the groups of binding table entries
1074 * commong to all pipeline stages.
1076 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1077 * unused but also make sure that addition of small offsets to them will
1078 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1081 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset
)
1083 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1085 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1086 next_binding_table_offset
+= num_textures
;
1089 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1090 next_binding_table_offset
+= shader
->base
.NumUniformBlocks
;
1092 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1095 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1096 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1097 next_binding_table_offset
++;
1099 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1102 if (prog
->UsesGather
) {
1103 if (brw
->gen
>= 8) {
1104 stage_prog_data
->binding_table
.gather_texture_start
=
1105 stage_prog_data
->binding_table
.texture_start
;
1107 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1108 next_binding_table_offset
+= num_textures
;
1111 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1114 if (shader_prog
&& shader_prog
->NumAtomicBuffers
) {
1115 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1116 next_binding_table_offset
+= shader_prog
->NumAtomicBuffers
;
1118 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1121 if (shader
&& shader
->base
.NumImages
) {
1122 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1123 next_binding_table_offset
+= shader
->base
.NumImages
;
1125 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1128 /* This may or may not be used depending on how the compile goes. */
1129 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1130 next_binding_table_offset
++;
1132 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1134 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */