src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32
  33 extern "C" struct gl_shader *
  34 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  35 {
  36    struct brw_shader *shader;
  37
  38    shader = rzalloc(NULL, struct brw_shader);
  39    if (shader) {
  40       shader->base.Type = type;
  41       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  42       shader->base.Name = name;
  43       _mesa_init_shader(ctx, &shader->base);
  44    }
  45
  46    return &shader->base;
  47 }
  48
  49 extern "C" void
  50 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  51                       unsigned surf_index)
  52 {
  53    assert(surf_index < BRW_MAX_SURFACES);
  54
  55    prog_data->binding_table.size_bytes =
  56       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  57 }
  58
  59 enum brw_reg_type
  60 brw_type_for_base_type(const struct glsl_type *type)
  61 {
  62    switch (type->base_type) {
  63    case GLSL_TYPE_FLOAT:
  64       return BRW_REGISTER_TYPE_F;
  65    case GLSL_TYPE_INT:
  66    case GLSL_TYPE_BOOL:
  67    case GLSL_TYPE_SUBROUTINE:
  68       return BRW_REGISTER_TYPE_D;
  69    case GLSL_TYPE_UINT:
  70       return BRW_REGISTER_TYPE_UD;
  71    case GLSL_TYPE_ARRAY:
  72       return brw_type_for_base_type(type->fields.array);
  73    case GLSL_TYPE_STRUCT:
  74    case GLSL_TYPE_SAMPLER:
  75    case GLSL_TYPE_ATOMIC_UINT:
  76       /* These should be overridden with the type of the member when
  77        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  78        * way to trip up if we don't.
  79        */
  80       return BRW_REGISTER_TYPE_UD;
  81    case GLSL_TYPE_IMAGE:
  82       return BRW_REGISTER_TYPE_UD;
  83    case GLSL_TYPE_DOUBLE:
  84       return BRW_REGISTER_TYPE_DF;
  85    case GLSL_TYPE_VOID:
  86    case GLSL_TYPE_ERROR:
  87    case GLSL_TYPE_INTERFACE:
  88    case GLSL_TYPE_FUNCTION:
  89       unreachable("not reached");
  90    }
  91
  92    return BRW_REGISTER_TYPE_F;
  93 }
  94
  95 enum brw_conditional_mod
  96 brw_conditional_for_comparison(unsigned int op)
  97 {
  98    switch (op) {
  99    case ir_binop_less:
 100       return BRW_CONDITIONAL_L;
 101    case ir_binop_greater:
 102       return BRW_CONDITIONAL_G;
 103    case ir_binop_lequal:
 104       return BRW_CONDITIONAL_LE;
 105    case ir_binop_gequal:
 106       return BRW_CONDITIONAL_GE;
 107    case ir_binop_equal:
 108    case ir_binop_all_equal: /* same as equal for scalars */
 109       return BRW_CONDITIONAL_Z;
 110    case ir_binop_nequal:
 111    case ir_binop_any_nequal: /* same as nequal for scalars */
 112       return BRW_CONDITIONAL_NZ;
 113    default:
 114       unreachable("not reached: bad operation for comparison");
 115    }
 116 }
 117
 118 uint32_t
 119 brw_math_function(enum opcode op)
 120 {
 121    switch (op) {
 122    case SHADER_OPCODE_RCP:
 123       return BRW_MATH_FUNCTION_INV;
 124    case SHADER_OPCODE_RSQ:
 125       return BRW_MATH_FUNCTION_RSQ;
 126    case SHADER_OPCODE_SQRT:
 127       return BRW_MATH_FUNCTION_SQRT;
 128    case SHADER_OPCODE_EXP2:
 129       return BRW_MATH_FUNCTION_EXP;
 130    case SHADER_OPCODE_LOG2:
 131       return BRW_MATH_FUNCTION_LOG;
 132    case SHADER_OPCODE_POW:
 133       return BRW_MATH_FUNCTION_POW;
 134    case SHADER_OPCODE_SIN:
 135       return BRW_MATH_FUNCTION_SIN;
 136    case SHADER_OPCODE_COS:
 137       return BRW_MATH_FUNCTION_COS;
 138    case SHADER_OPCODE_INT_QUOTIENT:
 139       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 140    case SHADER_OPCODE_INT_REMAINDER:
 141       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 142    default:
 143       unreachable("not reached: unknown math function");
 144    }
 145 }
 146
 147 uint32_t
 148 brw_texture_offset(int *offsets, unsigned num_components)
 149 {
 150    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 151
 152    /* Combine all three offsets into a single unsigned dword:
 153     *
 154     *    bits 11:8 - U Offset (X component)
 155     *    bits  7:4 - V Offset (Y component)
 156     *    bits  3:0 - R Offset (Z component)
 157     */
 158    unsigned offset_bits = 0;
 159    for (unsigned i = 0; i < num_components; i++) {
 160       const unsigned shift = 4 * (2 - i);
 161       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 162    }
 163    return offset_bits;
 164 }
 165
 166 const char *
 167 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
 168 {
 169    switch (op) {
 170    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 171       assert(brw_opcode_desc(devinfo, op)->name);
 172       return brw_opcode_desc(devinfo, op)->name;
 173    case FS_OPCODE_FB_WRITE:
 174       return "fb_write";
 175    case FS_OPCODE_FB_WRITE_LOGICAL:
 176       return "fb_write_logical";
 177    case FS_OPCODE_PACK_STENCIL_REF:
 178       return "pack_stencil_ref";
 179    case FS_OPCODE_BLORP_FB_WRITE:
 180       return "blorp_fb_write";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183
 184    case SHADER_OPCODE_RCP:
 185       return "rcp";
 186    case SHADER_OPCODE_RSQ:
 187       return "rsq";
 188    case SHADER_OPCODE_SQRT:
 189       return "sqrt";
 190    case SHADER_OPCODE_EXP2:
 191       return "exp2";
 192    case SHADER_OPCODE_LOG2:
 193       return "log2";
 194    case SHADER_OPCODE_POW:
 195       return "pow";
 196    case SHADER_OPCODE_INT_QUOTIENT:
 197       return "int_quot";
 198    case SHADER_OPCODE_INT_REMAINDER:
 199       return "int_rem";
 200    case SHADER_OPCODE_SIN:
 201       return "sin";
 202    case SHADER_OPCODE_COS:
 203       return "cos";
 204
 205    case SHADER_OPCODE_TEX:
 206       return "tex";
 207    case SHADER_OPCODE_TEX_LOGICAL:
 208       return "tex_logical";
 209    case SHADER_OPCODE_TXD:
 210       return "txd";
 211    case SHADER_OPCODE_TXD_LOGICAL:
 212       return "txd_logical";
 213    case SHADER_OPCODE_TXF:
 214       return "txf";
 215    case SHADER_OPCODE_TXF_LOGICAL:
 216       return "txf_logical";
 217    case SHADER_OPCODE_TXL:
 218       return "txl";
 219    case SHADER_OPCODE_TXL_LOGICAL:
 220       return "txl_logical";
 221    case SHADER_OPCODE_TXS:
 222       return "txs";
 223    case SHADER_OPCODE_TXS_LOGICAL:
 224       return "txs_logical";
 225    case FS_OPCODE_TXB:
 226       return "txb";
 227    case FS_OPCODE_TXB_LOGICAL:
 228       return "txb_logical";
 229    case SHADER_OPCODE_TXF_CMS:
 230       return "txf_cms";
 231    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 232       return "txf_cms_logical";
 233    case SHADER_OPCODE_TXF_CMS_W:
 234       return "txf_cms_w";
 235    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 236       return "txf_cms_w_logical";
 237    case SHADER_OPCODE_TXF_UMS:
 238       return "txf_ums";
 239    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 240       return "txf_ums_logical";
 241    case SHADER_OPCODE_TXF_MCS:
 242       return "txf_mcs";
 243    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 244       return "txf_mcs_logical";
 245    case SHADER_OPCODE_LOD:
 246       return "lod";
 247    case SHADER_OPCODE_LOD_LOGICAL:
 248       return "lod_logical";
 249    case SHADER_OPCODE_TG4:
 250       return "tg4";
 251    case SHADER_OPCODE_TG4_LOGICAL:
 252       return "tg4_logical";
 253    case SHADER_OPCODE_TG4_OFFSET:
 254       return "tg4_offset";
 255    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 256       return "tg4_offset_logical";
 257    case SHADER_OPCODE_SAMPLEINFO:
 258       return "sampleinfo";
 259
 260    case SHADER_OPCODE_SHADER_TIME_ADD:
 261       return "shader_time_add";
 262
 263    case SHADER_OPCODE_UNTYPED_ATOMIC:
 264       return "untyped_atomic";
 265    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 266       return "untyped_atomic_logical";
 267    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 268       return "untyped_surface_read";
 269    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 270       return "untyped_surface_read_logical";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 272       return "untyped_surface_write";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 274       return "untyped_surface_write_logical";
 275    case SHADER_OPCODE_TYPED_ATOMIC:
 276       return "typed_atomic";
 277    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 278       return "typed_atomic_logical";
 279    case SHADER_OPCODE_TYPED_SURFACE_READ:
 280       return "typed_surface_read";
 281    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 282       return "typed_surface_read_logical";
 283    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 284       return "typed_surface_write";
 285    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 286       return "typed_surface_write_logical";
 287    case SHADER_OPCODE_MEMORY_FENCE:
 288       return "memory_fence";
 289
 290    case SHADER_OPCODE_LOAD_PAYLOAD:
 291       return "load_payload";
 292
 293    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 294       return "gen4_scratch_read";
 295    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 296       return "gen4_scratch_write";
 297    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 298       return "gen7_scratch_read";
 299    case SHADER_OPCODE_URB_WRITE_SIMD8:
 300       return "gen8_urb_write_simd8";
 301    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 302       return "gen8_urb_write_simd8_per_slot";
 303    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 304       return "gen8_urb_write_simd8_masked";
 305    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 306       return "gen8_urb_write_simd8_masked_per_slot";
 307    case SHADER_OPCODE_URB_READ_SIMD8:
 308       return "urb_read_simd8";
 309    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 310       return "urb_read_simd8_per_slot";
 311
 312    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 313       return "find_live_channel";
 314    case SHADER_OPCODE_BROADCAST:
 315       return "broadcast";
 316
 317    case SHADER_OPCODE_EXTRACT_BYTE:
 318       return "extract_byte";
 319    case SHADER_OPCODE_EXTRACT_WORD:
 320       return "extract_word";
 321    case VEC4_OPCODE_MOV_BYTES:
 322       return "mov_bytes";
 323    case VEC4_OPCODE_PACK_BYTES:
 324       return "pack_bytes";
 325    case VEC4_OPCODE_UNPACK_UNIFORM:
 326       return "unpack_uniform";
 327
 328    case FS_OPCODE_DDX_COARSE:
 329       return "ddx_coarse";
 330    case FS_OPCODE_DDX_FINE:
 331       return "ddx_fine";
 332    case FS_OPCODE_DDY_COARSE:
 333       return "ddy_coarse";
 334    case FS_OPCODE_DDY_FINE:
 335       return "ddy_fine";
 336
 337    case FS_OPCODE_CINTERP:
 338       return "cinterp";
 339    case FS_OPCODE_LINTERP:
 340       return "linterp";
 341
 342    case FS_OPCODE_PIXEL_X:
 343       return "pixel_x";
 344    case FS_OPCODE_PIXEL_Y:
 345       return "pixel_y";
 346
 347    case FS_OPCODE_GET_BUFFER_SIZE:
 348       return "fs_get_buffer_size";
 349
 350    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 351       return "uniform_pull_const";
 352    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 353       return "uniform_pull_const_gen7";
 354    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 355       return "varying_pull_const";
 356    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 357       return "varying_pull_const_gen7";
 358
 359    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 360       return "mov_dispatch_to_flags";
 361    case FS_OPCODE_DISCARD_JUMP:
 362       return "discard_jump";
 363
 364    case FS_OPCODE_SET_SAMPLE_ID:
 365       return "set_sample_id";
 366    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 367       return "set_simd4x2_offset";
 368
 369    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 370       return "pack_half_2x16_split";
 371    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 372       return "unpack_half_2x16_split_x";
 373    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 374       return "unpack_half_2x16_split_y";
 375
 376    case FS_OPCODE_PLACEHOLDER_HALT:
 377       return "placeholder_halt";
 378
 379    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 380       return "interp_centroid";
 381    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 382       return "interp_sample";
 383    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 384       return "interp_shared_offset";
 385    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 386       return "interp_per_slot_offset";
 387
 388    case VS_OPCODE_URB_WRITE:
 389       return "vs_urb_write";
 390    case VS_OPCODE_PULL_CONSTANT_LOAD:
 391       return "pull_constant_load";
 392    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 393       return "pull_constant_load_gen7";
 394
 395    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 396       return "set_simd4x2_header_gen9";
 397
 398    case VS_OPCODE_GET_BUFFER_SIZE:
 399       return "vs_get_buffer_size";
 400
 401    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 402       return "unpack_flags_simd4x2";
 403
 404    case GS_OPCODE_URB_WRITE:
 405       return "gs_urb_write";
 406    case GS_OPCODE_URB_WRITE_ALLOCATE:
 407       return "gs_urb_write_allocate";
 408    case GS_OPCODE_THREAD_END:
 409       return "gs_thread_end";
 410    case GS_OPCODE_SET_WRITE_OFFSET:
 411       return "set_write_offset";
 412    case GS_OPCODE_SET_VERTEX_COUNT:
 413       return "set_vertex_count";
 414    case GS_OPCODE_SET_DWORD_2:
 415       return "set_dword_2";
 416    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 417       return "prepare_channel_masks";
 418    case GS_OPCODE_SET_CHANNEL_MASKS:
 419       return "set_channel_masks";
 420    case GS_OPCODE_GET_INSTANCE_ID:
 421       return "get_instance_id";
 422    case GS_OPCODE_FF_SYNC:
 423       return "ff_sync";
 424    case GS_OPCODE_SET_PRIMITIVE_ID:
 425       return "set_primitive_id";
 426    case GS_OPCODE_SVB_WRITE:
 427       return "gs_svb_write";
 428    case GS_OPCODE_SVB_SET_DST_INDEX:
 429       return "gs_svb_set_dst_index";
 430    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 431       return "gs_ff_sync_set_primitives";
 432    case CS_OPCODE_CS_TERMINATE:
 433       return "cs_terminate";
 434    case SHADER_OPCODE_BARRIER:
 435       return "barrier";
 436    case SHADER_OPCODE_MULH:
 437       return "mulh";
 438    case SHADER_OPCODE_MOV_INDIRECT:
 439       return "mov_indirect";
 440
 441    case VEC4_OPCODE_URB_READ:
 442       return "urb_read";
 443    case TCS_OPCODE_GET_INSTANCE_ID:
 444       return "tcs_get_instance_id";
 445    case TCS_OPCODE_URB_WRITE:
 446       return "tcs_urb_write";
 447    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 448       return "tcs_set_input_urb_offsets";
 449    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 450       return "tcs_set_output_urb_offsets";
 451    case TCS_OPCODE_GET_PRIMITIVE_ID:
 452       return "tcs_get_primitive_id";
 453    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 454       return "tcs_create_barrier_header";
 455    case TCS_OPCODE_SRC0_010_IS_ZERO:
 456       return "tcs_src0<0,1,0>_is_zero";
 457    case TCS_OPCODE_RELEASE_INPUT:
 458       return "tcs_release_input";
 459    case TCS_OPCODE_THREAD_END:
 460       return "tcs_thread_end";
 461    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 462       return "tes_create_input_read_header";
 463    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 464       return "tes_add_indirect_urb_offset";
 465    case TES_OPCODE_GET_PRIMITIVE_ID:
 466       return "tes_get_primitive_id";
 467    }
 468
 469    unreachable("not reached");
 470 }
 471
 472 bool
 473 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 474 {
 475    union {
 476       unsigned ud;
 477       int d;
 478       float f;
 479    } imm = { reg->ud }, sat_imm = { 0 };
 480
 481    switch (type) {
 482    case BRW_REGISTER_TYPE_UD:
 483    case BRW_REGISTER_TYPE_D:
 484    case BRW_REGISTER_TYPE_UW:
 485    case BRW_REGISTER_TYPE_W:
 486    case BRW_REGISTER_TYPE_UQ:
 487    case BRW_REGISTER_TYPE_Q:
 488       /* Nothing to do. */
 489       return false;
 490    case BRW_REGISTER_TYPE_F:
 491       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 492       break;
 493    case BRW_REGISTER_TYPE_UB:
 494    case BRW_REGISTER_TYPE_B:
 495       unreachable("no UB/B immediates");
 496    case BRW_REGISTER_TYPE_V:
 497    case BRW_REGISTER_TYPE_UV:
 498    case BRW_REGISTER_TYPE_VF:
 499       unreachable("unimplemented: saturate vector immediate");
 500    case BRW_REGISTER_TYPE_DF:
 501    case BRW_REGISTER_TYPE_HF:
 502       unreachable("unimplemented: saturate DF/HF immediate");
 503    }
 504
 505    if (imm.ud != sat_imm.ud) {
 506       reg->ud = sat_imm.ud;
 507       return true;
 508    }
 509    return false;
 510 }
 511
 512 bool
 513 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 514 {
 515    switch (type) {
 516    case BRW_REGISTER_TYPE_D:
 517    case BRW_REGISTER_TYPE_UD:
 518       reg->d = -reg->d;
 519       return true;
 520    case BRW_REGISTER_TYPE_W:
 521    case BRW_REGISTER_TYPE_UW:
 522       reg->d = -(int16_t)reg->ud;
 523       return true;
 524    case BRW_REGISTER_TYPE_F:
 525       reg->f = -reg->f;
 526       return true;
 527    case BRW_REGISTER_TYPE_VF:
 528       reg->ud ^= 0x80808080;
 529       return true;
 530    case BRW_REGISTER_TYPE_UB:
 531    case BRW_REGISTER_TYPE_B:
 532       unreachable("no UB/B immediates");
 533    case BRW_REGISTER_TYPE_UV:
 534    case BRW_REGISTER_TYPE_V:
 535       assert(!"unimplemented: negate UV/V immediate");
 536    case BRW_REGISTER_TYPE_UQ:
 537    case BRW_REGISTER_TYPE_Q:
 538       assert(!"unimplemented: negate UQ/Q immediate");
 539    case BRW_REGISTER_TYPE_DF:
 540    case BRW_REGISTER_TYPE_HF:
 541       assert(!"unimplemented: negate DF/HF immediate");
 542    }
 543
 544    return false;
 545 }
 546
 547 bool
 548 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 549 {
 550    switch (type) {
 551    case BRW_REGISTER_TYPE_D:
 552       reg->d = abs(reg->d);
 553       return true;
 554    case BRW_REGISTER_TYPE_W:
 555       reg->d = abs((int16_t)reg->ud);
 556       return true;
 557    case BRW_REGISTER_TYPE_F:
 558       reg->f = fabsf(reg->f);
 559       return true;
 560    case BRW_REGISTER_TYPE_VF:
 561       reg->ud &= ~0x80808080;
 562       return true;
 563    case BRW_REGISTER_TYPE_UB:
 564    case BRW_REGISTER_TYPE_B:
 565       unreachable("no UB/B immediates");
 566    case BRW_REGISTER_TYPE_UQ:
 567    case BRW_REGISTER_TYPE_UD:
 568    case BRW_REGISTER_TYPE_UW:
 569    case BRW_REGISTER_TYPE_UV:
 570       /* Presumably the absolute value modifier on an unsigned source is a
 571        * nop, but it would be nice to confirm.
 572        */
 573       assert(!"unimplemented: abs unsigned immediate");
 574    case BRW_REGISTER_TYPE_V:
 575       assert(!"unimplemented: abs V immediate");
 576    case BRW_REGISTER_TYPE_Q:
 577       assert(!"unimplemented: abs Q immediate");
 578    case BRW_REGISTER_TYPE_DF:
 579    case BRW_REGISTER_TYPE_HF:
 580       assert(!"unimplemented: abs DF/HF immediate");
 581    }
 582
 583    return false;
 584 }
 585
 586 unsigned
 587 tesslevel_outer_components(GLenum tes_primitive_mode)
 588 {
 589    switch (tes_primitive_mode) {
 590    case GL_QUADS:
 591       return 4;
 592    case GL_TRIANGLES:
 593       return 3;
 594    case GL_ISOLINES:
 595       return 2;
 596    default:
 597       unreachable("Bogus tessellation domain");
 598    }
 599    return 0;
 600 }
 601
 602 unsigned
 603 tesslevel_inner_components(GLenum tes_primitive_mode)
 604 {
 605    switch (tes_primitive_mode) {
 606    case GL_QUADS:
 607       return 2;
 608    case GL_TRIANGLES:
 609       return 1;
 610    case GL_ISOLINES:
 611       return 0;
 612    default:
 613       unreachable("Bogus tessellation domain");
 614    }
 615    return 0;
 616 }
 617
 618 /**
 619  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 620  * that's stored backwards, i.e. .wzyx.
 621  */
 622 unsigned
 623 writemask_for_backwards_vector(unsigned mask)
 624 {
 625    unsigned new_mask = 0;
 626
 627    for (int i = 0; i < 4; i++)
 628       new_mask |= ((mask >> i) & 1) << (3 - i);
 629
 630    return new_mask;
 631 }
 632
 633 backend_shader::backend_shader(const struct brw_compiler *compiler,
 634                                void *log_data,
 635                                void *mem_ctx,
 636                                const nir_shader *shader,
 637                                struct brw_stage_prog_data *stage_prog_data)
 638    : compiler(compiler),
 639      log_data(log_data),
 640      devinfo(compiler->devinfo),
 641      nir(shader),
 642      stage_prog_data(stage_prog_data),
 643      mem_ctx(mem_ctx),
 644      cfg(NULL),
 645      stage(shader->stage)
 646 {
 647    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 648    stage_name = _mesa_shader_stage_to_string(stage);
 649    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 650    is_passthrough_shader =
 651       nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
 652 }
 653
 654 bool
 655 backend_reg::equals(const backend_reg &r) const
 656 {
 657    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 658           reg_offset == r.reg_offset;
 659 }
 660
 661 bool
 662 backend_reg::is_zero() const
 663 {
 664    if (file != IMM)
 665       return false;
 666
 667    return d == 0;
 668 }
 669
 670 bool
 671 backend_reg::is_one() const
 672 {
 673    if (file != IMM)
 674       return false;
 675
 676    return type == BRW_REGISTER_TYPE_F
 677           ? f == 1.0
 678           : d == 1;
 679 }
 680
 681 bool
 682 backend_reg::is_negative_one() const
 683 {
 684    if (file != IMM)
 685       return false;
 686
 687    switch (type) {
 688    case BRW_REGISTER_TYPE_F:
 689       return f == -1.0;
 690    case BRW_REGISTER_TYPE_D:
 691       return d == -1;
 692    default:
 693       return false;
 694    }
 695 }
 696
 697 bool
 698 backend_reg::is_null() const
 699 {
 700    return file == ARF && nr == BRW_ARF_NULL;
 701 }
 702
 703
 704 bool
 705 backend_reg::is_accumulator() const
 706 {
 707    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 708 }
 709
 710 bool
 711 backend_reg::in_range(const backend_reg &r, unsigned n) const
 712 {
 713    return (file == r.file &&
 714            nr == r.nr &&
 715            reg_offset >= r.reg_offset &&
 716            reg_offset < r.reg_offset + n);
 717 }
 718
 719 bool
 720 backend_instruction::is_commutative() const
 721 {
 722    switch (opcode) {
 723    case BRW_OPCODE_AND:
 724    case BRW_OPCODE_OR:
 725    case BRW_OPCODE_XOR:
 726    case BRW_OPCODE_ADD:
 727    case BRW_OPCODE_MUL:
 728    case SHADER_OPCODE_MULH:
 729       return true;
 730    case BRW_OPCODE_SEL:
 731       /* MIN and MAX are commutative. */
 732       if (conditional_mod == BRW_CONDITIONAL_GE ||
 733           conditional_mod == BRW_CONDITIONAL_L) {
 734          return true;
 735       }
 736       /* fallthrough */
 737    default:
 738       return false;
 739    }
 740 }
 741
 742 bool
 743 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
 744 {
 745    return ::is_3src(devinfo, opcode);
 746 }
 747
 748 bool
 749 backend_instruction::is_tex() const
 750 {
 751    return (opcode == SHADER_OPCODE_TEX ||
 752            opcode == FS_OPCODE_TXB ||
 753            opcode == SHADER_OPCODE_TXD ||
 754            opcode == SHADER_OPCODE_TXF ||
 755            opcode == SHADER_OPCODE_TXF_CMS ||
 756            opcode == SHADER_OPCODE_TXF_CMS_W ||
 757            opcode == SHADER_OPCODE_TXF_UMS ||
 758            opcode == SHADER_OPCODE_TXF_MCS ||
 759            opcode == SHADER_OPCODE_TXL ||
 760            opcode == SHADER_OPCODE_TXS ||
 761            opcode == SHADER_OPCODE_LOD ||
 762            opcode == SHADER_OPCODE_TG4 ||
 763            opcode == SHADER_OPCODE_TG4_OFFSET ||
 764            opcode == SHADER_OPCODE_SAMPLEINFO);
 765 }
 766
 767 bool
 768 backend_instruction::is_math() const
 769 {
 770    return (opcode == SHADER_OPCODE_RCP ||
 771            opcode == SHADER_OPCODE_RSQ ||
 772            opcode == SHADER_OPCODE_SQRT ||
 773            opcode == SHADER_OPCODE_EXP2 ||
 774            opcode == SHADER_OPCODE_LOG2 ||
 775            opcode == SHADER_OPCODE_SIN ||
 776            opcode == SHADER_OPCODE_COS ||
 777            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 778            opcode == SHADER_OPCODE_INT_REMAINDER ||
 779            opcode == SHADER_OPCODE_POW);
 780 }
 781
 782 bool
 783 backend_instruction::is_control_flow() const
 784 {
 785    switch (opcode) {
 786    case BRW_OPCODE_DO:
 787    case BRW_OPCODE_WHILE:
 788    case BRW_OPCODE_IF:
 789    case BRW_OPCODE_ELSE:
 790    case BRW_OPCODE_ENDIF:
 791    case BRW_OPCODE_BREAK:
 792    case BRW_OPCODE_CONTINUE:
 793       return true;
 794    default:
 795       return false;
 796    }
 797 }
 798
 799 bool
 800 backend_instruction::can_do_source_mods() const
 801 {
 802    switch (opcode) {
 803    case BRW_OPCODE_ADDC:
 804    case BRW_OPCODE_BFE:
 805    case BRW_OPCODE_BFI1:
 806    case BRW_OPCODE_BFI2:
 807    case BRW_OPCODE_BFREV:
 808    case BRW_OPCODE_CBIT:
 809    case BRW_OPCODE_FBH:
 810    case BRW_OPCODE_FBL:
 811    case BRW_OPCODE_SUBB:
 812       return false;
 813    default:
 814       return true;
 815    }
 816 }
 817
 818 bool
 819 backend_instruction::can_do_saturate() const
 820 {
 821    switch (opcode) {
 822    case BRW_OPCODE_ADD:
 823    case BRW_OPCODE_ASR:
 824    case BRW_OPCODE_AVG:
 825    case BRW_OPCODE_DP2:
 826    case BRW_OPCODE_DP3:
 827    case BRW_OPCODE_DP4:
 828    case BRW_OPCODE_DPH:
 829    case BRW_OPCODE_F16TO32:
 830    case BRW_OPCODE_F32TO16:
 831    case BRW_OPCODE_LINE:
 832    case BRW_OPCODE_LRP:
 833    case BRW_OPCODE_MAC:
 834    case BRW_OPCODE_MAD:
 835    case BRW_OPCODE_MATH:
 836    case BRW_OPCODE_MOV:
 837    case BRW_OPCODE_MUL:
 838    case SHADER_OPCODE_MULH:
 839    case BRW_OPCODE_PLN:
 840    case BRW_OPCODE_RNDD:
 841    case BRW_OPCODE_RNDE:
 842    case BRW_OPCODE_RNDU:
 843    case BRW_OPCODE_RNDZ:
 844    case BRW_OPCODE_SEL:
 845    case BRW_OPCODE_SHL:
 846    case BRW_OPCODE_SHR:
 847    case FS_OPCODE_LINTERP:
 848    case SHADER_OPCODE_COS:
 849    case SHADER_OPCODE_EXP2:
 850    case SHADER_OPCODE_LOG2:
 851    case SHADER_OPCODE_POW:
 852    case SHADER_OPCODE_RCP:
 853    case SHADER_OPCODE_RSQ:
 854    case SHADER_OPCODE_SIN:
 855    case SHADER_OPCODE_SQRT:
 856       return true;
 857    default:
 858       return false;
 859    }
 860 }
 861
 862 bool
 863 backend_instruction::can_do_cmod() const
 864 {
 865    switch (opcode) {
 866    case BRW_OPCODE_ADD:
 867    case BRW_OPCODE_ADDC:
 868    case BRW_OPCODE_AND:
 869    case BRW_OPCODE_ASR:
 870    case BRW_OPCODE_AVG:
 871    case BRW_OPCODE_CMP:
 872    case BRW_OPCODE_CMPN:
 873    case BRW_OPCODE_DP2:
 874    case BRW_OPCODE_DP3:
 875    case BRW_OPCODE_DP4:
 876    case BRW_OPCODE_DPH:
 877    case BRW_OPCODE_F16TO32:
 878    case BRW_OPCODE_F32TO16:
 879    case BRW_OPCODE_FRC:
 880    case BRW_OPCODE_LINE:
 881    case BRW_OPCODE_LRP:
 882    case BRW_OPCODE_LZD:
 883    case BRW_OPCODE_MAC:
 884    case BRW_OPCODE_MACH:
 885    case BRW_OPCODE_MAD:
 886    case BRW_OPCODE_MOV:
 887    case BRW_OPCODE_MUL:
 888    case BRW_OPCODE_NOT:
 889    case BRW_OPCODE_OR:
 890    case BRW_OPCODE_PLN:
 891    case BRW_OPCODE_RNDD:
 892    case BRW_OPCODE_RNDE:
 893    case BRW_OPCODE_RNDU:
 894    case BRW_OPCODE_RNDZ:
 895    case BRW_OPCODE_SAD2:
 896    case BRW_OPCODE_SADA2:
 897    case BRW_OPCODE_SHL:
 898    case BRW_OPCODE_SHR:
 899    case BRW_OPCODE_SUBB:
 900    case BRW_OPCODE_XOR:
 901    case FS_OPCODE_CINTERP:
 902    case FS_OPCODE_LINTERP:
 903       return true;
 904    default:
 905       return false;
 906    }
 907 }
 908
 909 bool
 910 backend_instruction::reads_accumulator_implicitly() const
 911 {
 912    switch (opcode) {
 913    case BRW_OPCODE_MAC:
 914    case BRW_OPCODE_MACH:
 915    case BRW_OPCODE_SADA2:
 916       return true;
 917    default:
 918       return false;
 919    }
 920 }
 921
 922 bool
 923 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 924 {
 925    return writes_accumulator ||
 926           (devinfo->gen < 6 &&
 927            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 928             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 929              opcode != FS_OPCODE_CINTERP)));
 930 }
 931
 932 bool
 933 backend_instruction::has_side_effects() const
 934 {
 935    switch (opcode) {
 936    case SHADER_OPCODE_UNTYPED_ATOMIC:
 937    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 938    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 939    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 940    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 941    case SHADER_OPCODE_TYPED_ATOMIC:
 942    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 943    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 944    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 945    case SHADER_OPCODE_MEMORY_FENCE:
 946    case SHADER_OPCODE_URB_WRITE_SIMD8:
 947    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 948    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 949    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 950    case FS_OPCODE_FB_WRITE:
 951    case SHADER_OPCODE_BARRIER:
 952    case TCS_OPCODE_URB_WRITE:
 953    case TCS_OPCODE_RELEASE_INPUT:
 954       return true;
 955    default:
 956       return false;
 957    }
 958 }
 959
 960 bool
 961 backend_instruction::is_volatile() const
 962 {
 963    switch (opcode) {
 964    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 965    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 966    case SHADER_OPCODE_TYPED_SURFACE_READ:
 967    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 968    case SHADER_OPCODE_URB_READ_SIMD8:
 969    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 970    case VEC4_OPCODE_URB_READ:
 971       return true;
 972    default:
 973       return false;
 974    }
 975 }
 976
 977 #ifndef NDEBUG
 978 static bool
 979 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 980 {
 981    bool found = false;
 982    foreach_inst_in_block (backend_instruction, i, block) {
 983       if (inst == i) {
 984          found = true;
 985       }
 986    }
 987    return found;
 988 }
 989 #endif
 990
 991 static void
 992 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 993 {
 994    for (bblock_t *block_iter = start_block->next();
 995         block_iter;
 996         block_iter = block_iter->next()) {
 997       block_iter->start_ip += ip_adjustment;
 998       block_iter->end_ip += ip_adjustment;
 999    }
1000 }
1001
1002 void
1003 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1004 {
1005    assert(this != inst);
1006
1007    if (!this->is_head_sentinel())
1008       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1009
1010    block->end_ip++;
1011
1012    adjust_later_block_ips(block, 1);
1013
1014    exec_node::insert_after(inst);
1015 }
1016
1017 void
1018 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1019 {
1020    assert(this != inst);
1021
1022    if (!this->is_tail_sentinel())
1023       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1024
1025    block->end_ip++;
1026
1027    adjust_later_block_ips(block, 1);
1028
1029    exec_node::insert_before(inst);
1030 }
1031
1032 void
1033 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1034 {
1035    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1036
1037    unsigned num_inst = list->length();
1038
1039    block->end_ip += num_inst;
1040
1041    adjust_later_block_ips(block, num_inst);
1042
1043    exec_node::insert_before(list);
1044 }
1045
1046 void
1047 backend_instruction::remove(bblock_t *block)
1048 {
1049    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1050
1051    adjust_later_block_ips(block, -1);
1052
1053    if (block->start_ip == block->end_ip) {
1054       block->cfg->remove_block(block);
1055    } else {
1056       block->end_ip--;
1057    }
1058
1059    exec_node::remove();
1060 }
1061
1062 void
1063 backend_shader::dump_instructions()
1064 {
1065    dump_instructions(NULL);
1066 }
1067
1068 void
1069 backend_shader::dump_instructions(const char *name)
1070 {
1071    FILE *file = stderr;
1072    if (name && geteuid() != 0) {
1073       file = fopen(name, "w");
1074       if (!file)
1075          file = stderr;
1076    }
1077
1078    if (cfg) {
1079       int ip = 0;
1080       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1081          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1082             fprintf(file, "%4d: ", ip++);
1083          dump_instruction(inst, file);
1084       }
1085    } else {
1086       int ip = 0;
1087       foreach_in_list(backend_instruction, inst, &instructions) {
1088          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1089             fprintf(file, "%4d: ", ip++);
1090          dump_instruction(inst, file);
1091       }
1092    }
1093
1094    if (file != stderr) {
1095       fclose(file);
1096    }
1097 }
1098
1099 void
1100 backend_shader::calculate_cfg()
1101 {
1102    if (this->cfg)
1103       return;
1104    cfg = new(mem_ctx) cfg_t(&this->instructions);
1105 }
1106
1107 /**
1108  * Sets up the starting offsets for the groups of binding table entries
1109  * commong to all pipeline stages.
1110  *
1111  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1112  * unused but also make sure that addition of small offsets to them will
1113  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1114  */
1115 void
1116 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1117                                         const struct brw_device_info *devinfo,
1118                                         const struct gl_shader_program *shader_prog,
1119                                         const struct gl_program *prog,
1120                                         struct brw_stage_prog_data *stage_prog_data,
1121                                         uint32_t next_binding_table_offset)
1122 {
1123    const struct gl_shader *shader = NULL;
1124    int num_textures = _mesa_fls(prog->SamplersUsed);
1125
1126    if (shader_prog)
1127       shader = shader_prog->_LinkedShaders[stage];
1128
1129    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1130    next_binding_table_offset += num_textures;
1131
1132    if (shader) {
1133       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1134       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1135       next_binding_table_offset += shader->NumUniformBlocks;
1136
1137       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1138       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1139       next_binding_table_offset += shader->NumShaderStorageBlocks;
1140    } else {
1141       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1142       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1143    }
1144
1145    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1146       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1147       next_binding_table_offset++;
1148    } else {
1149       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1150    }
1151
1152    if (prog->UsesGather) {
1153       if (devinfo->gen >= 8) {
1154          stage_prog_data->binding_table.gather_texture_start =
1155             stage_prog_data->binding_table.texture_start;
1156       } else {
1157          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1158          next_binding_table_offset += num_textures;
1159       }
1160    } else {
1161       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1162    }
1163
1164    if (shader && shader->NumAtomicBuffers) {
1165       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1166       next_binding_table_offset += shader->NumAtomicBuffers;
1167    } else {
1168       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1169    }
1170
1171    if (shader && shader->NumImages) {
1172       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1173       next_binding_table_offset += shader->NumImages;
1174    } else {
1175       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1176    }
1177
1178    /* This may or may not be used depending on how the compile goes. */
1179    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1180    next_binding_table_offset++;
1181
1182    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1183
1184    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1185 }
1186
1187 static void
1188 setup_vec4_uniform_value(const gl_constant_value **params,
1189                          const gl_constant_value *values,
1190                          unsigned n)
1191 {
1192    static const gl_constant_value zero = { 0 };
1193
1194    for (unsigned i = 0; i < n; ++i)
1195       params[i] = &values[i];
1196
1197    for (unsigned i = n; i < 4; ++i)
1198       params[i] = &zero;
1199 }
1200
1201 void
1202 brw_setup_image_uniform_values(gl_shader_stage stage,
1203                                struct brw_stage_prog_data *stage_prog_data,
1204                                unsigned param_start_index,
1205                                const gl_uniform_storage *storage)
1206 {
1207    const gl_constant_value **param =
1208       &stage_prog_data->param[param_start_index];
1209
1210    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1211       const unsigned image_idx = storage->opaque[stage].index + i;
1212       const brw_image_param *image_param =
1213          &stage_prog_data->image_param[image_idx];
1214
1215       /* Upload the brw_image_param structure.  The order is expected to match
1216        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1217        */
1218       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1219          (const gl_constant_value *)&image_param->surface_idx, 1);
1220       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1221          (const gl_constant_value *)image_param->offset, 2);
1222       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1223          (const gl_constant_value *)image_param->size, 3);
1224       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1225          (const gl_constant_value *)image_param->stride, 4);
1226       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1227          (const gl_constant_value *)image_param->tiling, 3);
1228       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1229          (const gl_constant_value *)image_param->swizzling, 2);
1230       param += BRW_IMAGE_PARAM_SIZE;
1231
1232       brw_mark_surface_used(
1233          stage_prog_data,
1234          stage_prog_data->binding_table.image_start + image_idx);
1235    }
1236 }
1237
1238 /**
1239  * Decide which set of clip planes should be used when clipping via
1240  * gl_Position or gl_ClipVertex.
1241  */
1242 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1243 {
1244    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1245       /* There is currently a GLSL vertex shader, so clip according to GLSL
1246        * rules, which means compare gl_ClipVertex (or gl_Position, if
1247        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1248        * that were stored in EyeUserPlane at the time the clip planes were
1249        * specified.
1250        */
1251       return ctx->Transform.EyeUserPlane;
1252    } else {
1253       /* Either we are using fixed function or an ARB vertex program.  In
1254        * either case the clip planes are going to be compared against
1255        * gl_Position (which is in clip coordinates) so we have to clip using
1256        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1257        * core.
1258        */
1259       return ctx->Transform._ClipUserPlane;
1260    }
1261 }
1262
1263 extern "C" const unsigned *
1264 brw_compile_tes(const struct brw_compiler *compiler,
1265                 void *log_data,
1266                 void *mem_ctx,
1267                 const struct brw_tes_prog_key *key,
1268                 struct brw_tes_prog_data *prog_data,
1269                 const nir_shader *src_shader,
1270                 struct gl_shader_program *shader_prog,
1271                 int shader_time_index,
1272                 unsigned *final_assembly_size,
1273                 char **error_str)
1274 {
1275    const struct brw_device_info *devinfo = compiler->devinfo;
1276    struct gl_shader *shader =
1277       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1278    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1279
1280    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1281    nir->info.inputs_read = key->inputs_read;
1282    nir->info.patch_inputs_read = key->patch_inputs_read;
1283
1284    struct brw_vue_map input_vue_map;
1285    brw_compute_tess_vue_map(&input_vue_map,
1286                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1287                             nir->info.patch_inputs_read);
1288
1289    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1290    brw_nir_lower_tes_inputs(nir, &input_vue_map);
1291    brw_nir_lower_vue_outputs(nir, is_scalar);
1292    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1293
1294    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1295                        nir->info.outputs_written,
1296                        nir->info.separate_shader);
1297
1298    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1299
1300    assert(output_size_bytes >= 1);
1301    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1302       if (error_str)
1303          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1304       return NULL;
1305    }
1306
1307    /* URB entry sizes are stored as a multiple of 64 bytes. */
1308    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1309
1310    bool need_patch_header = nir->info.system_values_read &
1311       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1312        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1313
1314    /* The TES will pull most inputs using URB read messages.
1315     *
1316     * However, we push the patch header for TessLevel factors when required,
1317     * as it's a tiny amount of extra data.
1318     */
1319    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1320
1321    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1322       fprintf(stderr, "TES Input ");
1323       brw_print_vue_map(stderr, &input_vue_map);
1324       fprintf(stderr, "TES Output ");
1325       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1326    }
1327
1328    if (is_scalar) {
1329       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1330                    &prog_data->base.base, shader->Program, nir, 8,
1331                    shader_time_index, &input_vue_map);
1332       if (!v.run_tes()) {
1333          if (error_str)
1334             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1335          return NULL;
1336       }
1337
1338       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1339
1340       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1341                      &prog_data->base.base, v.promoted_constants, false,
1342                      MESA_SHADER_TESS_EVAL);
1343       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1344          g.enable_debug(ralloc_asprintf(mem_ctx,
1345                                         "%s tessellation evaluation shader %s",
1346                                         nir->info.label ? nir->info.label
1347                                                         : "unnamed",
1348                                         nir->info.name));
1349       }
1350
1351       g.generate_code(v.cfg, 8);
1352
1353       return g.get_assembly(final_assembly_size);
1354    } else {
1355       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1356                               nir, mem_ctx, shader_time_index);
1357       if (!v.run()) {
1358          if (error_str)
1359             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1360          return NULL;
1361       }
1362
1363       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1364          v.dump_instructions();
1365
1366       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1367                                         &prog_data->base, v.cfg,
1368                                         final_assembly_size);
1369    }
1370 }