src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "brw_context.h"
  27 }
  28 #include "brw_vs.h"
  29 #include "brw_vec4_gs.h"
  30 #include "brw_fs.h"
  31 #include "brw_cfg.h"
  32 #include "glsl/ir_optimization.h"
  33 #include "glsl/glsl_parser_extras.h"
  34 #include "main/shaderapi.h"
  35
  36 struct gl_shader *
  37 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  38 {
  39    struct brw_shader *shader;
  40
  41    shader = rzalloc(NULL, struct brw_shader);
  42    if (shader) {
  43       shader->base.Type = type;
  44       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  45       shader->base.Name = name;
  46       _mesa_init_shader(ctx, &shader->base);
  47    }
  48
  49    return &shader->base;
  50 }
  51
  52 struct gl_shader_program *
  53 brw_new_shader_program(struct gl_context *ctx, GLuint name)
  54 {
  55    struct gl_shader_program *prog = rzalloc(NULL, struct gl_shader_program);
  56    if (prog) {
  57       prog->Name = name;
  58       _mesa_init_shader_program(ctx, prog);
  59    }
  60    return prog;
  61 }
  62
  63 /**
  64  * Performs a compile of the shader stages even when we don't know
  65  * what non-orthogonal state will be set, in the hope that it reflects
  66  * the eventual NOS used, and thus allows us to produce link failures.
  67  */
  68 static bool
  69 brw_shader_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
  70 {
  71    struct brw_context *brw = brw_context(ctx);
  72
  73    if (brw->precompile && !brw_fs_precompile(ctx, prog))
  74       return false;
  75
  76    if (brw->precompile && !brw_gs_precompile(ctx, prog))
  77       return false;
  78
  79    if (brw->precompile && !brw_vs_precompile(ctx, prog))
  80       return false;
  81
  82    return true;
  83 }
  84
  85 static void
  86 brw_lower_packing_builtins(struct brw_context *brw,
  87                            gl_shader_stage shader_type,
  88                            exec_list *ir)
  89 {
  90    int ops = LOWER_PACK_SNORM_2x16
  91            | LOWER_UNPACK_SNORM_2x16
  92            | LOWER_PACK_UNORM_2x16
  93            | LOWER_UNPACK_UNORM_2x16
  94            | LOWER_PACK_SNORM_4x8
  95            | LOWER_UNPACK_SNORM_4x8
  96            | LOWER_PACK_UNORM_4x8
  97            | LOWER_UNPACK_UNORM_4x8;
  98
  99    if (brw->gen >= 7) {
 100       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 101        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 102        * lowering is needed. For SOA code, the Half2x16 ops must be
 103        * scalarized.
 104        */
 105       if (shader_type == MESA_SHADER_FRAGMENT) {
 106          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 107              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 108       }
 109    } else {
 110       ops |= LOWER_PACK_HALF_2x16
 111           |  LOWER_UNPACK_HALF_2x16;
 112    }
 113
 114    lower_packing_builtins(ir, ops);
 115 }
 116
 117 GLboolean
 118 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 119 {
 120    struct brw_context *brw = brw_context(ctx);
 121    unsigned int stage;
 122
 123    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 124       const struct gl_shader_compiler_options *options =
 125          &ctx->Const.ShaderCompilerOptions[stage];
 126       struct brw_shader *shader =
 127          (struct brw_shader *)shProg->_LinkedShaders[stage];
 128
 129       if (!shader)
 130          continue;
 131
 132       struct gl_program *prog =
 133          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 134                                 shader->base.Name);
 135       if (!prog)
 136         return false;
 137       prog->Parameters = _mesa_new_parameter_list();
 138
 139       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 140
 141       bool progress;
 142
 143       /* lower_packing_builtins() inserts arithmetic instructions, so it
 144        * must precede lower_instructions().
 145        */
 146       brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->base.ir);
 147       do_mat_op_to_vec(shader->base.ir);
 148       const int bitfield_insert = brw->gen >= 7
 149                                   ? BITFIELD_INSERT_TO_BFM_BFI
 150                                   : 0;
 151       lower_instructions(shader->base.ir,
 152                          MOD_TO_FRACT |
 153                          DIV_TO_MUL_RCP |
 154                          SUB_TO_ADD_NEG |
 155                          EXP_TO_EXP2 |
 156                          LOG_TO_LOG2 |
 157                          bitfield_insert |
 158                          LDEXP_TO_ARITH);
 159
 160       /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 161        * if-statements need to be flattened.
 162        */
 163       if (brw->gen < 6)
 164          lower_if_to_cond_assign(shader->base.ir, 16);
 165
 166       do_lower_texture_projection(shader->base.ir);
 167       brw_lower_texture_gradients(brw, shader->base.ir);
 168       do_vec_index_to_cond_assign(shader->base.ir);
 169       lower_vector_insert(shader->base.ir, true);
 170       brw_do_cubemap_normalize(shader->base.ir);
 171       lower_offset_arrays(shader->base.ir);
 172       brw_do_lower_unnormalized_offset(shader->base.ir);
 173       lower_noise(shader->base.ir);
 174       lower_quadop_vector(shader->base.ir, false);
 175
 176       bool lowered_variable_indexing =
 177          lower_variable_index_to_cond_assign(shader->base.ir,
 178                                              options->EmitNoIndirectInput,
 179                                              options->EmitNoIndirectOutput,
 180                                              options->EmitNoIndirectTemp,
 181                                              options->EmitNoIndirectUniform);
 182
 183       if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 184          perf_debug("Unsupported form of variable indexing in FS; falling "
 185                     "back to very inefficient code generation\n");
 186       }
 187
 188       lower_ubo_reference(&shader->base, shader->base.ir);
 189
 190       do {
 191          progress = false;
 192
 193          if (stage == MESA_SHADER_FRAGMENT) {
 194             brw_do_channel_expressions(shader->base.ir);
 195             brw_do_vector_splitting(shader->base.ir);
 196          }
 197
 198          progress = do_lower_jumps(shader->base.ir, true, true,
 199                                    true, /* main return */
 200                                    false, /* continue */
 201                                    false /* loops */
 202                                    ) || progress;
 203
 204          progress = do_common_optimization(shader->base.ir, true, true,
 205                                            options, ctx->Const.NativeIntegers)
 206            || progress;
 207       } while (progress);
 208
 209       /* Make a pass over the IR to add state references for any built-in
 210        * uniforms that are used.  This has to be done now (during linking).
 211        * Code generation doesn't happen until the first time this shader is
 212        * used for rendering.  Waiting until then to generate the parameters is
 213        * too late.  At that point, the values for the built-in uniforms won't
 214        * get sent to the shader.
 215        */
 216       foreach_in_list(ir_instruction, node, shader->base.ir) {
 217          ir_variable *var = node->as_variable();
 218
 219          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 220              || (strncmp(var->name, "gl_", 3) != 0))
 221             continue;
 222
 223          const ir_state_slot *const slots = var->state_slots;
 224          assert(var->state_slots != NULL);
 225
 226          for (unsigned int i = 0; i < var->num_state_slots; i++) {
 227             _mesa_add_state_reference(prog->Parameters,
 228                                       (gl_state_index *) slots[i].tokens);
 229          }
 230       }
 231
 232       validate_ir_tree(shader->base.ir);
 233
 234       do_set_program_inouts(shader->base.ir, prog, shader->base.Stage);
 235
 236       prog->SamplersUsed = shader->base.active_samplers;
 237       _mesa_update_shader_textures_used(shProg, prog);
 238
 239       _mesa_reference_program(ctx, &shader->base.Program, prog);
 240
 241       brw_add_texrect_params(prog);
 242
 243       _mesa_reference_program(ctx, &prog, NULL);
 244
 245       if (ctx->_Shader->Flags & GLSL_DUMP) {
 246          fprintf(stderr, "\n");
 247          fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 248                  _mesa_shader_stage_to_string(shader->base.Stage),
 249                  shProg->Name);
 250          _mesa_print_ir(stderr, shader->base.ir, NULL);
 251          fprintf(stderr, "\n");
 252       }
 253    }
 254
 255    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 256       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 257          const struct gl_shader *sh = shProg->Shaders[i];
 258          if (!sh)
 259             continue;
 260
 261          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 262                  _mesa_shader_stage_to_string(sh->Stage),
 263                  i, shProg->Name);
 264          fprintf(stderr, "%s", sh->Source);
 265          fprintf(stderr, "\n");
 266       }
 267    }
 268
 269    if (!brw_shader_precompile(ctx, shProg))
 270       return false;
 271
 272    return true;
 273 }
 274
 275
 276 enum brw_reg_type
 277 brw_type_for_base_type(const struct glsl_type *type)
 278 {
 279    switch (type->base_type) {
 280    case GLSL_TYPE_FLOAT:
 281       return BRW_REGISTER_TYPE_F;
 282    case GLSL_TYPE_INT:
 283    case GLSL_TYPE_BOOL:
 284       return BRW_REGISTER_TYPE_D;
 285    case GLSL_TYPE_UINT:
 286       return BRW_REGISTER_TYPE_UD;
 287    case GLSL_TYPE_ARRAY:
 288       return brw_type_for_base_type(type->fields.array);
 289    case GLSL_TYPE_STRUCT:
 290    case GLSL_TYPE_SAMPLER:
 291    case GLSL_TYPE_ATOMIC_UINT:
 292       /* These should be overridden with the type of the member when
 293        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 294        * way to trip up if we don't.
 295        */
 296       return BRW_REGISTER_TYPE_UD;
 297    case GLSL_TYPE_IMAGE:
 298       return BRW_REGISTER_TYPE_UD;
 299    case GLSL_TYPE_VOID:
 300    case GLSL_TYPE_ERROR:
 301    case GLSL_TYPE_INTERFACE:
 302       unreachable("not reached");
 303    }
 304
 305    return BRW_REGISTER_TYPE_F;
 306 }
 307
 308 enum brw_conditional_mod
 309 brw_conditional_for_comparison(unsigned int op)
 310 {
 311    switch (op) {
 312    case ir_binop_less:
 313       return BRW_CONDITIONAL_L;
 314    case ir_binop_greater:
 315       return BRW_CONDITIONAL_G;
 316    case ir_binop_lequal:
 317       return BRW_CONDITIONAL_LE;
 318    case ir_binop_gequal:
 319       return BRW_CONDITIONAL_GE;
 320    case ir_binop_equal:
 321    case ir_binop_all_equal: /* same as equal for scalars */
 322       return BRW_CONDITIONAL_Z;
 323    case ir_binop_nequal:
 324    case ir_binop_any_nequal: /* same as nequal for scalars */
 325       return BRW_CONDITIONAL_NZ;
 326    default:
 327       unreachable("not reached: bad operation for comparison");
 328    }
 329 }
 330
 331 uint32_t
 332 brw_math_function(enum opcode op)
 333 {
 334    switch (op) {
 335    case SHADER_OPCODE_RCP:
 336       return BRW_MATH_FUNCTION_INV;
 337    case SHADER_OPCODE_RSQ:
 338       return BRW_MATH_FUNCTION_RSQ;
 339    case SHADER_OPCODE_SQRT:
 340       return BRW_MATH_FUNCTION_SQRT;
 341    case SHADER_OPCODE_EXP2:
 342       return BRW_MATH_FUNCTION_EXP;
 343    case SHADER_OPCODE_LOG2:
 344       return BRW_MATH_FUNCTION_LOG;
 345    case SHADER_OPCODE_POW:
 346       return BRW_MATH_FUNCTION_POW;
 347    case SHADER_OPCODE_SIN:
 348       return BRW_MATH_FUNCTION_SIN;
 349    case SHADER_OPCODE_COS:
 350       return BRW_MATH_FUNCTION_COS;
 351    case SHADER_OPCODE_INT_QUOTIENT:
 352       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 353    case SHADER_OPCODE_INT_REMAINDER:
 354       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 355    default:
 356       unreachable("not reached: unknown math function");
 357    }
 358 }
 359
 360 uint32_t
 361 brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
 362 {
 363    /* If the driver does not support GL_ARB_gpu_shader5, the offset
 364     * must be constant.
 365     */
 366    assert(offset != NULL || ctx->Extensions.ARB_gpu_shader5);
 367
 368    if (!offset) return 0;  /* nonconstant offset; caller will handle it. */
 369
 370    signed char offsets[3];
 371    for (unsigned i = 0; i < offset->type->vector_elements; i++)
 372       offsets[i] = (signed char) offset->value.i[i];
 373
 374    /* Combine all three offsets into a single unsigned dword:
 375     *
 376     *    bits 11:8 - U Offset (X component)
 377     *    bits  7:4 - V Offset (Y component)
 378     *    bits  3:0 - R Offset (Z component)
 379     */
 380    unsigned offset_bits = 0;
 381    for (unsigned i = 0; i < offset->type->vector_elements; i++) {
 382       const unsigned shift = 4 * (2 - i);
 383       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 384    }
 385    return offset_bits;
 386 }
 387
 388 const char *
 389 brw_instruction_name(enum opcode op)
 390 {
 391    char *fallback;
 392
 393    if (op < ARRAY_SIZE(opcode_descs) && opcode_descs[op].name)
 394       return opcode_descs[op].name;
 395
 396    switch (op) {
 397    case FS_OPCODE_FB_WRITE:
 398       return "fb_write";
 399    case FS_OPCODE_BLORP_FB_WRITE:
 400       return "blorp_fb_write";
 401
 402    case SHADER_OPCODE_RCP:
 403       return "rcp";
 404    case SHADER_OPCODE_RSQ:
 405       return "rsq";
 406    case SHADER_OPCODE_SQRT:
 407       return "sqrt";
 408    case SHADER_OPCODE_EXP2:
 409       return "exp2";
 410    case SHADER_OPCODE_LOG2:
 411       return "log2";
 412    case SHADER_OPCODE_POW:
 413       return "pow";
 414    case SHADER_OPCODE_INT_QUOTIENT:
 415       return "int_quot";
 416    case SHADER_OPCODE_INT_REMAINDER:
 417       return "int_rem";
 418    case SHADER_OPCODE_SIN:
 419       return "sin";
 420    case SHADER_OPCODE_COS:
 421       return "cos";
 422
 423    case SHADER_OPCODE_TEX:
 424       return "tex";
 425    case SHADER_OPCODE_TXD:
 426       return "txd";
 427    case SHADER_OPCODE_TXF:
 428       return "txf";
 429    case SHADER_OPCODE_TXL:
 430       return "txl";
 431    case SHADER_OPCODE_TXS:
 432       return "txs";
 433    case FS_OPCODE_TXB:
 434       return "txb";
 435    case SHADER_OPCODE_TXF_CMS:
 436       return "txf_cms";
 437    case SHADER_OPCODE_TXF_UMS:
 438       return "txf_ums";
 439    case SHADER_OPCODE_TXF_MCS:
 440       return "txf_mcs";
 441    case SHADER_OPCODE_TG4:
 442       return "tg4";
 443    case SHADER_OPCODE_TG4_OFFSET:
 444       return "tg4_offset";
 445    case SHADER_OPCODE_SHADER_TIME_ADD:
 446       return "shader_time_add";
 447
 448    case SHADER_OPCODE_LOAD_PAYLOAD:
 449       return "load_payload";
 450
 451    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 452       return "gen4_scratch_read";
 453    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 454       return "gen4_scratch_write";
 455    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 456       return "gen7_scratch_read";
 457
 458    case FS_OPCODE_DDX:
 459       return "ddx";
 460    case FS_OPCODE_DDY:
 461       return "ddy";
 462
 463    case FS_OPCODE_PIXEL_X:
 464       return "pixel_x";
 465    case FS_OPCODE_PIXEL_Y:
 466       return "pixel_y";
 467
 468    case FS_OPCODE_CINTERP:
 469       return "cinterp";
 470    case FS_OPCODE_LINTERP:
 471       return "linterp";
 472
 473    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 474       return "uniform_pull_const";
 475    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 476       return "uniform_pull_const_gen7";
 477    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 478       return "varying_pull_const";
 479    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 480       return "varying_pull_const_gen7";
 481
 482    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 483       return "mov_dispatch_to_flags";
 484    case FS_OPCODE_DISCARD_JUMP:
 485       return "discard_jump";
 486
 487    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 488       return "set_simd4x2_offset";
 489
 490    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 491       return "pack_half_2x16_split";
 492    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 493       return "unpack_half_2x16_split_x";
 494    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 495       return "unpack_half_2x16_split_y";
 496
 497    case FS_OPCODE_PLACEHOLDER_HALT:
 498       return "placeholder_halt";
 499
 500    case VS_OPCODE_URB_WRITE:
 501       return "vs_urb_write";
 502    case VS_OPCODE_PULL_CONSTANT_LOAD:
 503       return "pull_constant_load";
 504    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 505       return "pull_constant_load_gen7";
 506    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 507       return "unpack_flags_simd4x2";
 508
 509    case GS_OPCODE_URB_WRITE:
 510       return "gs_urb_write";
 511    case GS_OPCODE_URB_WRITE_ALLOCATE:
 512       return "gs_urb_write_allocate";
 513    case GS_OPCODE_THREAD_END:
 514       return "gs_thread_end";
 515    case GS_OPCODE_SET_WRITE_OFFSET:
 516       return "set_write_offset";
 517    case GS_OPCODE_SET_VERTEX_COUNT:
 518       return "set_vertex_count";
 519    case GS_OPCODE_SET_DWORD_2:
 520       return "set_dword_2";
 521    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 522       return "prepare_channel_masks";
 523    case GS_OPCODE_SET_CHANNEL_MASKS:
 524       return "set_channel_masks";
 525    case GS_OPCODE_GET_INSTANCE_ID:
 526       return "get_instance_id";
 527    case GS_OPCODE_FF_SYNC:
 528       return "ff_sync";
 529    case GS_OPCODE_SET_PRIMITIVE_ID:
 530       return "set_primitive_id";
 531    case GS_OPCODE_SVB_WRITE:
 532       return "gs_svb_write";
 533    case GS_OPCODE_SVB_SET_DST_INDEX:
 534       return "gs_svb_set_dst_index";
 535
 536    default:
 537       /* Yes, this leaks.  It's in debug code, it should never occur, and if
 538        * it does, you should just add the case to the list above.
 539        */
 540       asprintf(&fallback, "op%d", op);
 541       return fallback;
 542    }
 543 }
 544
 545 backend_visitor::backend_visitor(struct brw_context *brw,
 546                                  struct gl_shader_program *shader_prog,
 547                                  struct gl_program *prog,
 548                                  struct brw_stage_prog_data *stage_prog_data,
 549                                  gl_shader_stage stage)
 550    : brw(brw),
 551      ctx(&brw->ctx),
 552      shader(shader_prog ?
 553         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 554      shader_prog(shader_prog),
 555      prog(prog),
 556      stage_prog_data(stage_prog_data),
 557      cfg(NULL),
 558      stage(stage)
 559 {
 560 }
 561
 562 bool
 563 backend_reg::is_zero() const
 564 {
 565    if (file != IMM)
 566       return false;
 567
 568    return fixed_hw_reg.dw1.d == 0;
 569 }
 570
 571 bool
 572 backend_reg::is_one() const
 573 {
 574    if (file != IMM)
 575       return false;
 576
 577    return type == BRW_REGISTER_TYPE_F
 578           ? fixed_hw_reg.dw1.f == 1.0
 579           : fixed_hw_reg.dw1.d == 1;
 580 }
 581
 582 bool
 583 backend_reg::is_null() const
 584 {
 585    return file == HW_REG &&
 586           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 587           fixed_hw_reg.nr == BRW_ARF_NULL;
 588 }
 589
 590
 591 bool
 592 backend_reg::is_accumulator() const
 593 {
 594    return file == HW_REG &&
 595           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 596           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 597 }
 598
 599 bool
 600 backend_instruction::is_tex() const
 601 {
 602    return (opcode == SHADER_OPCODE_TEX ||
 603            opcode == FS_OPCODE_TXB ||
 604            opcode == SHADER_OPCODE_TXD ||
 605            opcode == SHADER_OPCODE_TXF ||
 606            opcode == SHADER_OPCODE_TXF_CMS ||
 607            opcode == SHADER_OPCODE_TXF_UMS ||
 608            opcode == SHADER_OPCODE_TXF_MCS ||
 609            opcode == SHADER_OPCODE_TXL ||
 610            opcode == SHADER_OPCODE_TXS ||
 611            opcode == SHADER_OPCODE_LOD ||
 612            opcode == SHADER_OPCODE_TG4 ||
 613            opcode == SHADER_OPCODE_TG4_OFFSET);
 614 }
 615
 616 bool
 617 backend_instruction::is_math() const
 618 {
 619    return (opcode == SHADER_OPCODE_RCP ||
 620            opcode == SHADER_OPCODE_RSQ ||
 621            opcode == SHADER_OPCODE_SQRT ||
 622            opcode == SHADER_OPCODE_EXP2 ||
 623            opcode == SHADER_OPCODE_LOG2 ||
 624            opcode == SHADER_OPCODE_SIN ||
 625            opcode == SHADER_OPCODE_COS ||
 626            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 627            opcode == SHADER_OPCODE_INT_REMAINDER ||
 628            opcode == SHADER_OPCODE_POW);
 629 }
 630
 631 bool
 632 backend_instruction::is_control_flow() const
 633 {
 634    switch (opcode) {
 635    case BRW_OPCODE_DO:
 636    case BRW_OPCODE_WHILE:
 637    case BRW_OPCODE_IF:
 638    case BRW_OPCODE_ELSE:
 639    case BRW_OPCODE_ENDIF:
 640    case BRW_OPCODE_BREAK:
 641    case BRW_OPCODE_CONTINUE:
 642       return true;
 643    default:
 644       return false;
 645    }
 646 }
 647
 648 bool
 649 backend_instruction::can_do_source_mods() const
 650 {
 651    switch (opcode) {
 652    case BRW_OPCODE_ADDC:
 653    case BRW_OPCODE_BFE:
 654    case BRW_OPCODE_BFI1:
 655    case BRW_OPCODE_BFI2:
 656    case BRW_OPCODE_BFREV:
 657    case BRW_OPCODE_CBIT:
 658    case BRW_OPCODE_FBH:
 659    case BRW_OPCODE_FBL:
 660    case BRW_OPCODE_SUBB:
 661       return false;
 662    default:
 663       return true;
 664    }
 665 }
 666
 667 bool
 668 backend_instruction::can_do_saturate() const
 669 {
 670    switch (opcode) {
 671    case BRW_OPCODE_ADD:
 672    case BRW_OPCODE_ASR:
 673    case BRW_OPCODE_AVG:
 674    case BRW_OPCODE_DP2:
 675    case BRW_OPCODE_DP3:
 676    case BRW_OPCODE_DP4:
 677    case BRW_OPCODE_DPH:
 678    case BRW_OPCODE_F16TO32:
 679    case BRW_OPCODE_F32TO16:
 680    case BRW_OPCODE_LINE:
 681    case BRW_OPCODE_LRP:
 682    case BRW_OPCODE_MAC:
 683    case BRW_OPCODE_MACH:
 684    case BRW_OPCODE_MAD:
 685    case BRW_OPCODE_MATH:
 686    case BRW_OPCODE_MOV:
 687    case BRW_OPCODE_MUL:
 688    case BRW_OPCODE_PLN:
 689    case BRW_OPCODE_RNDD:
 690    case BRW_OPCODE_RNDE:
 691    case BRW_OPCODE_RNDU:
 692    case BRW_OPCODE_RNDZ:
 693    case BRW_OPCODE_SEL:
 694    case BRW_OPCODE_SHL:
 695    case BRW_OPCODE_SHR:
 696    case FS_OPCODE_LINTERP:
 697    case SHADER_OPCODE_COS:
 698    case SHADER_OPCODE_EXP2:
 699    case SHADER_OPCODE_LOG2:
 700    case SHADER_OPCODE_POW:
 701    case SHADER_OPCODE_RCP:
 702    case SHADER_OPCODE_RSQ:
 703    case SHADER_OPCODE_SIN:
 704    case SHADER_OPCODE_SQRT:
 705       return true;
 706    default:
 707       return false;
 708    }
 709 }
 710
 711 bool
 712 backend_instruction::reads_accumulator_implicitly() const
 713 {
 714    switch (opcode) {
 715    case BRW_OPCODE_MAC:
 716    case BRW_OPCODE_MACH:
 717    case BRW_OPCODE_SADA2:
 718       return true;
 719    default:
 720       return false;
 721    }
 722 }
 723
 724 bool
 725 backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
 726 {
 727    return writes_accumulator ||
 728           (brw->gen < 6 &&
 729            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 730             (opcode >= FS_OPCODE_DDX && opcode <= FS_OPCODE_LINTERP &&
 731              opcode != FS_OPCODE_CINTERP)));
 732 }
 733
 734 bool
 735 backend_instruction::has_side_effects() const
 736 {
 737    switch (opcode) {
 738    case SHADER_OPCODE_UNTYPED_ATOMIC:
 739       return true;
 740    default:
 741       return false;
 742    }
 743 }
 744
 745 #ifndef NDEBUG
 746 static bool
 747 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 748 {
 749    bool found = false;
 750    foreach_inst_in_block (backend_instruction, i, block) {
 751       if (inst == i) {
 752          found = true;
 753       }
 754    }
 755    return found;
 756 }
 757 #endif
 758
 759 static void
 760 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 761 {
 762    for (bblock_t *block_iter = (bblock_t *)start_block->link.next;
 763         !block_iter->link.is_tail_sentinel();
 764         block_iter = (bblock_t *)block_iter->link.next) {
 765       block_iter->start_ip += ip_adjustment;
 766       block_iter->end_ip += ip_adjustment;
 767    }
 768 }
 769
 770 void
 771 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
 772 {
 773    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 774
 775    block->end_ip++;
 776
 777    adjust_later_block_ips(block, 1);
 778
 779    if (block->end == this)
 780       block->end = inst;
 781
 782    exec_node::insert_after(inst);
 783 }
 784
 785 void
 786 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
 787 {
 788    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 789
 790    block->end_ip++;
 791
 792    adjust_later_block_ips(block, 1);
 793
 794    if (block->start == this)
 795       block->start = inst;
 796
 797    exec_node::insert_before(inst);
 798 }
 799
 800 void
 801 backend_instruction::insert_before(bblock_t *block, exec_list *list)
 802 {
 803    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 804
 805    unsigned num_inst = list->length();
 806
 807    block->end_ip += num_inst;
 808
 809    adjust_later_block_ips(block, num_inst);
 810
 811    if (block->start == this)
 812       block->start = (backend_instruction *)list->get_head();
 813
 814    exec_node::insert_before(list);
 815 }
 816
 817 void
 818 backend_instruction::remove(bblock_t *block)
 819 {
 820    assert(inst_is_in_block(block, this) || !"Instruction not in block");
 821
 822    adjust_later_block_ips(block, -1);
 823
 824    if (block->start_ip == block->end_ip) {
 825       block->cfg->remove_block(block);
 826    } else {
 827       block->end_ip--;
 828
 829       if (block->start == this)
 830          block->start = (backend_instruction *)this->next;
 831       if (block->end == this)
 832          block->end = (backend_instruction *)this->prev;
 833    }
 834
 835    exec_node::remove();
 836 }
 837
 838 void
 839 backend_visitor::dump_instructions()
 840 {
 841    dump_instructions(NULL);
 842 }
 843
 844 void
 845 backend_visitor::dump_instructions(const char *name)
 846 {
 847    FILE *file = stderr;
 848    if (name && geteuid() != 0) {
 849       file = fopen(name, "w");
 850       if (!file)
 851          file = stderr;
 852    }
 853
 854    int ip = 0;
 855    foreach_in_list(backend_instruction, inst, &instructions) {
 856       if (!name)
 857          fprintf(stderr, "%d: ", ip++);
 858       dump_instruction(inst, file);
 859    }
 860
 861    if (file != stderr) {
 862       fclose(file);
 863    }
 864 }
 865
 866 void
 867 backend_visitor::calculate_cfg()
 868 {
 869    if (this->cfg)
 870       return;
 871    cfg = new(mem_ctx) cfg_t(&this->instructions);
 872 }
 873
 874 void
 875 backend_visitor::invalidate_cfg()
 876 {
 877    ralloc_free(this->cfg);
 878    this->cfg = NULL;
 879 }
 880
 881 /**
 882  * Sets up the starting offsets for the groups of binding table entries
 883  * commong to all pipeline stages.
 884  *
 885  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 886  * unused but also make sure that addition of small offsets to them will
 887  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
 888  */
 889 void
 890 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
 891 {
 892    int num_textures = _mesa_fls(prog->SamplersUsed);
 893
 894    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
 895    next_binding_table_offset += num_textures;
 896
 897    if (shader) {
 898       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
 899       next_binding_table_offset += shader->base.NumUniformBlocks;
 900    } else {
 901       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
 902    }
 903
 904    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
 905       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
 906       next_binding_table_offset++;
 907    } else {
 908       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
 909    }
 910
 911    if (prog->UsesGather) {
 912       if (brw->gen >= 8) {
 913          stage_prog_data->binding_table.gather_texture_start =
 914             stage_prog_data->binding_table.texture_start;
 915       } else {
 916          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
 917          next_binding_table_offset += num_textures;
 918       }
 919    } else {
 920       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
 921    }
 922
 923    if (shader_prog && shader_prog->NumAtomicBuffers) {
 924       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
 925       next_binding_table_offset += shader_prog->NumAtomicBuffers;
 926    } else {
 927       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
 928    }
 929
 930    /* This may or may not be used depending on how the compile goes. */
 931    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
 932    next_binding_table_offset++;
 933
 934    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 935
 936    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 937 }