src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "glsl/glsl_parser_extras.h"
  31 #include "main/shaderobj.h"
  32 #include "main/uniforms.h"
  33 #include "util/debug.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  88       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  89    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = false;
  90    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
  91       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
  92    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  93       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  94    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  95    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  96
  97    nir_shader_compiler_options *nir_options =
  98       rzalloc(compiler, nir_shader_compiler_options);
  99    nir_options->native_integers = true;
 100    /* In order to help allow for better CSE at the NIR level we tell NIR
 101     * to split all ffma instructions during opt_algebraic and we then
 102     * re-combine them as a later step.
 103     */
 104    nir_options->lower_ffma = true;
 105    nir_options->lower_sub = true;
 106    nir_options->lower_fdiv = true;
 107    nir_options->lower_scmp = true;
 108    nir_options->lower_fmod = true;
 109    nir_options->lower_bitfield_insert = true;
 110    nir_options->lower_uadd_carry = true;
 111    nir_options->lower_usub_borrow = true;
 112
 113    /* In the vec4 backend, our dpN instruction replicates its result to all
 114     * the components of a vec4.  We would like NIR to give us replicated fdot
 115     * instructions because it can optimize better for us.
 116     *
 117     * For the FS backend, it should be lowered away by the scalarizing pass so
 118     * we should never see fdot anyway.
 119     */
 120    nir_options->fdot_replicates = true;
 121
 122    /* We want the GLSL compiler to emit code that uses condition codes */
 123    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 124       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 125       compiler->glsl_compiler_options[i].MaxIfDepth =
 126          devinfo->gen < 6 ? 16 : UINT_MAX;
 127
 128       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 129       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 130       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 131       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 132       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 133       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 134
 135       bool is_scalar = compiler->scalar_stage[i];
 136
 137       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 138       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 139       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 140
 141       /* !ARB_gpu_shader5 */
 142       if (devinfo->gen < 7)
 143          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 144
 145       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 146
 147       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 148    }
 149
 150    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 151    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 152
 153    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 154       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 155
 156    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 157       .LowerShaderSharedVariables = true;
 158
 159    return compiler;
 160 }
 161
 162 extern "C" struct gl_shader *
 163 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 164 {
 165    struct brw_shader *shader;
 166
 167    shader = rzalloc(NULL, struct brw_shader);
 168    if (shader) {
 169       shader->base.Type = type;
 170       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 171       shader->base.Name = name;
 172       _mesa_init_shader(ctx, &shader->base);
 173    }
 174
 175    return &shader->base;
 176 }
 177
 178 extern "C" void
 179 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 180                       unsigned surf_index)
 181 {
 182    assert(surf_index < BRW_MAX_SURFACES);
 183
 184    prog_data->binding_table.size_bytes =
 185       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 186 }
 187
 188 enum brw_reg_type
 189 brw_type_for_base_type(const struct glsl_type *type)
 190 {
 191    switch (type->base_type) {
 192    case GLSL_TYPE_FLOAT:
 193       return BRW_REGISTER_TYPE_F;
 194    case GLSL_TYPE_INT:
 195    case GLSL_TYPE_BOOL:
 196    case GLSL_TYPE_SUBROUTINE:
 197       return BRW_REGISTER_TYPE_D;
 198    case GLSL_TYPE_UINT:
 199       return BRW_REGISTER_TYPE_UD;
 200    case GLSL_TYPE_ARRAY:
 201       return brw_type_for_base_type(type->fields.array);
 202    case GLSL_TYPE_STRUCT:
 203    case GLSL_TYPE_SAMPLER:
 204    case GLSL_TYPE_ATOMIC_UINT:
 205       /* These should be overridden with the type of the member when
 206        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 207        * way to trip up if we don't.
 208        */
 209       return BRW_REGISTER_TYPE_UD;
 210    case GLSL_TYPE_IMAGE:
 211       return BRW_REGISTER_TYPE_UD;
 212    case GLSL_TYPE_VOID:
 213    case GLSL_TYPE_ERROR:
 214    case GLSL_TYPE_INTERFACE:
 215    case GLSL_TYPE_DOUBLE:
 216    case GLSL_TYPE_FUNCTION:
 217       unreachable("not reached");
 218    }
 219
 220    return BRW_REGISTER_TYPE_F;
 221 }
 222
 223 enum brw_conditional_mod
 224 brw_conditional_for_comparison(unsigned int op)
 225 {
 226    switch (op) {
 227    case ir_binop_less:
 228       return BRW_CONDITIONAL_L;
 229    case ir_binop_greater:
 230       return BRW_CONDITIONAL_G;
 231    case ir_binop_lequal:
 232       return BRW_CONDITIONAL_LE;
 233    case ir_binop_gequal:
 234       return BRW_CONDITIONAL_GE;
 235    case ir_binop_equal:
 236    case ir_binop_all_equal: /* same as equal for scalars */
 237       return BRW_CONDITIONAL_Z;
 238    case ir_binop_nequal:
 239    case ir_binop_any_nequal: /* same as nequal for scalars */
 240       return BRW_CONDITIONAL_NZ;
 241    default:
 242       unreachable("not reached: bad operation for comparison");
 243    }
 244 }
 245
 246 uint32_t
 247 brw_math_function(enum opcode op)
 248 {
 249    switch (op) {
 250    case SHADER_OPCODE_RCP:
 251       return BRW_MATH_FUNCTION_INV;
 252    case SHADER_OPCODE_RSQ:
 253       return BRW_MATH_FUNCTION_RSQ;
 254    case SHADER_OPCODE_SQRT:
 255       return BRW_MATH_FUNCTION_SQRT;
 256    case SHADER_OPCODE_EXP2:
 257       return BRW_MATH_FUNCTION_EXP;
 258    case SHADER_OPCODE_LOG2:
 259       return BRW_MATH_FUNCTION_LOG;
 260    case SHADER_OPCODE_POW:
 261       return BRW_MATH_FUNCTION_POW;
 262    case SHADER_OPCODE_SIN:
 263       return BRW_MATH_FUNCTION_SIN;
 264    case SHADER_OPCODE_COS:
 265       return BRW_MATH_FUNCTION_COS;
 266    case SHADER_OPCODE_INT_QUOTIENT:
 267       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 268    case SHADER_OPCODE_INT_REMAINDER:
 269       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 270    default:
 271       unreachable("not reached: unknown math function");
 272    }
 273 }
 274
 275 uint32_t
 276 brw_texture_offset(int *offsets, unsigned num_components)
 277 {
 278    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 279
 280    /* Combine all three offsets into a single unsigned dword:
 281     *
 282     *    bits 11:8 - U Offset (X component)
 283     *    bits  7:4 - V Offset (Y component)
 284     *    bits  3:0 - R Offset (Z component)
 285     */
 286    unsigned offset_bits = 0;
 287    for (unsigned i = 0; i < num_components; i++) {
 288       const unsigned shift = 4 * (2 - i);
 289       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 290    }
 291    return offset_bits;
 292 }
 293
 294 const char *
 295 brw_instruction_name(enum opcode op)
 296 {
 297    switch (op) {
 298    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 299       assert(opcode_descs[op].name);
 300       return opcode_descs[op].name;
 301    case FS_OPCODE_FB_WRITE:
 302       return "fb_write";
 303    case FS_OPCODE_FB_WRITE_LOGICAL:
 304       return "fb_write_logical";
 305    case FS_OPCODE_PACK_STENCIL_REF:
 306       return "pack_stencil_ref";
 307    case FS_OPCODE_BLORP_FB_WRITE:
 308       return "blorp_fb_write";
 309    case FS_OPCODE_REP_FB_WRITE:
 310       return "rep_fb_write";
 311
 312    case SHADER_OPCODE_RCP:
 313       return "rcp";
 314    case SHADER_OPCODE_RSQ:
 315       return "rsq";
 316    case SHADER_OPCODE_SQRT:
 317       return "sqrt";
 318    case SHADER_OPCODE_EXP2:
 319       return "exp2";
 320    case SHADER_OPCODE_LOG2:
 321       return "log2";
 322    case SHADER_OPCODE_POW:
 323       return "pow";
 324    case SHADER_OPCODE_INT_QUOTIENT:
 325       return "int_quot";
 326    case SHADER_OPCODE_INT_REMAINDER:
 327       return "int_rem";
 328    case SHADER_OPCODE_SIN:
 329       return "sin";
 330    case SHADER_OPCODE_COS:
 331       return "cos";
 332
 333    case SHADER_OPCODE_TEX:
 334       return "tex";
 335    case SHADER_OPCODE_TEX_LOGICAL:
 336       return "tex_logical";
 337    case SHADER_OPCODE_TXD:
 338       return "txd";
 339    case SHADER_OPCODE_TXD_LOGICAL:
 340       return "txd_logical";
 341    case SHADER_OPCODE_TXF:
 342       return "txf";
 343    case SHADER_OPCODE_TXF_LOGICAL:
 344       return "txf_logical";
 345    case SHADER_OPCODE_TXL:
 346       return "txl";
 347    case SHADER_OPCODE_TXL_LOGICAL:
 348       return "txl_logical";
 349    case SHADER_OPCODE_TXS:
 350       return "txs";
 351    case SHADER_OPCODE_TXS_LOGICAL:
 352       return "txs_logical";
 353    case FS_OPCODE_TXB:
 354       return "txb";
 355    case FS_OPCODE_TXB_LOGICAL:
 356       return "txb_logical";
 357    case SHADER_OPCODE_TXF_CMS:
 358       return "txf_cms";
 359    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 360       return "txf_cms_logical";
 361    case SHADER_OPCODE_TXF_CMS_W:
 362       return "txf_cms_w";
 363    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 364       return "txf_cms_w_logical";
 365    case SHADER_OPCODE_TXF_UMS:
 366       return "txf_ums";
 367    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 368       return "txf_ums_logical";
 369    case SHADER_OPCODE_TXF_MCS:
 370       return "txf_mcs";
 371    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 372       return "txf_mcs_logical";
 373    case SHADER_OPCODE_LOD:
 374       return "lod";
 375    case SHADER_OPCODE_LOD_LOGICAL:
 376       return "lod_logical";
 377    case SHADER_OPCODE_TG4:
 378       return "tg4";
 379    case SHADER_OPCODE_TG4_LOGICAL:
 380       return "tg4_logical";
 381    case SHADER_OPCODE_TG4_OFFSET:
 382       return "tg4_offset";
 383    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 384       return "tg4_offset_logical";
 385    case SHADER_OPCODE_SAMPLEINFO:
 386       return "sampleinfo";
 387
 388    case SHADER_OPCODE_SHADER_TIME_ADD:
 389       return "shader_time_add";
 390
 391    case SHADER_OPCODE_UNTYPED_ATOMIC:
 392       return "untyped_atomic";
 393    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 394       return "untyped_atomic_logical";
 395    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 396       return "untyped_surface_read";
 397    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 398       return "untyped_surface_read_logical";
 399    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 400       return "untyped_surface_write";
 401    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 402       return "untyped_surface_write_logical";
 403    case SHADER_OPCODE_TYPED_ATOMIC:
 404       return "typed_atomic";
 405    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 406       return "typed_atomic_logical";
 407    case SHADER_OPCODE_TYPED_SURFACE_READ:
 408       return "typed_surface_read";
 409    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 410       return "typed_surface_read_logical";
 411    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 412       return "typed_surface_write";
 413    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 414       return "typed_surface_write_logical";
 415    case SHADER_OPCODE_MEMORY_FENCE:
 416       return "memory_fence";
 417
 418    case SHADER_OPCODE_LOAD_PAYLOAD:
 419       return "load_payload";
 420
 421    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 422       return "gen4_scratch_read";
 423    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 424       return "gen4_scratch_write";
 425    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 426       return "gen7_scratch_read";
 427    case SHADER_OPCODE_URB_WRITE_SIMD8:
 428       return "gen8_urb_write_simd8";
 429    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 430       return "gen8_urb_write_simd8_per_slot";
 431    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 432       return "gen8_urb_write_simd8_masked";
 433    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 434       return "gen8_urb_write_simd8_masked_per_slot";
 435    case SHADER_OPCODE_URB_READ_SIMD8:
 436       return "urb_read_simd8";
 437    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 438       return "urb_read_simd8_per_slot";
 439
 440    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 441       return "find_live_channel";
 442    case SHADER_OPCODE_BROADCAST:
 443       return "broadcast";
 444
 445    case VEC4_OPCODE_MOV_BYTES:
 446       return "mov_bytes";
 447    case VEC4_OPCODE_PACK_BYTES:
 448       return "pack_bytes";
 449    case VEC4_OPCODE_UNPACK_UNIFORM:
 450       return "unpack_uniform";
 451
 452    case FS_OPCODE_DDX_COARSE:
 453       return "ddx_coarse";
 454    case FS_OPCODE_DDX_FINE:
 455       return "ddx_fine";
 456    case FS_OPCODE_DDY_COARSE:
 457       return "ddy_coarse";
 458    case FS_OPCODE_DDY_FINE:
 459       return "ddy_fine";
 460
 461    case FS_OPCODE_CINTERP:
 462       return "cinterp";
 463    case FS_OPCODE_LINTERP:
 464       return "linterp";
 465
 466    case FS_OPCODE_PIXEL_X:
 467       return "pixel_x";
 468    case FS_OPCODE_PIXEL_Y:
 469       return "pixel_y";
 470
 471    case FS_OPCODE_GET_BUFFER_SIZE:
 472       return "fs_get_buffer_size";
 473
 474    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 475       return "uniform_pull_const";
 476    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 477       return "uniform_pull_const_gen7";
 478    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 479       return "varying_pull_const";
 480    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 481       return "varying_pull_const_gen7";
 482
 483    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 484       return "mov_dispatch_to_flags";
 485    case FS_OPCODE_DISCARD_JUMP:
 486       return "discard_jump";
 487
 488    case FS_OPCODE_SET_SAMPLE_ID:
 489       return "set_sample_id";
 490    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 491       return "set_simd4x2_offset";
 492
 493    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 494       return "pack_half_2x16_split";
 495    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 496       return "unpack_half_2x16_split_x";
 497    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 498       return "unpack_half_2x16_split_y";
 499
 500    case FS_OPCODE_PLACEHOLDER_HALT:
 501       return "placeholder_halt";
 502
 503    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 504       return "interp_centroid";
 505    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 506       return "interp_sample";
 507    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 508       return "interp_shared_offset";
 509    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 510       return "interp_per_slot_offset";
 511
 512    case VS_OPCODE_URB_WRITE:
 513       return "vs_urb_write";
 514    case VS_OPCODE_PULL_CONSTANT_LOAD:
 515       return "pull_constant_load";
 516    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 517       return "pull_constant_load_gen7";
 518
 519    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 520       return "set_simd4x2_header_gen9";
 521
 522    case VS_OPCODE_GET_BUFFER_SIZE:
 523       return "vs_get_buffer_size";
 524
 525    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 526       return "unpack_flags_simd4x2";
 527
 528    case GS_OPCODE_URB_WRITE:
 529       return "gs_urb_write";
 530    case GS_OPCODE_URB_WRITE_ALLOCATE:
 531       return "gs_urb_write_allocate";
 532    case GS_OPCODE_THREAD_END:
 533       return "gs_thread_end";
 534    case GS_OPCODE_SET_WRITE_OFFSET:
 535       return "set_write_offset";
 536    case GS_OPCODE_SET_VERTEX_COUNT:
 537       return "set_vertex_count";
 538    case GS_OPCODE_SET_DWORD_2:
 539       return "set_dword_2";
 540    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 541       return "prepare_channel_masks";
 542    case GS_OPCODE_SET_CHANNEL_MASKS:
 543       return "set_channel_masks";
 544    case GS_OPCODE_GET_INSTANCE_ID:
 545       return "get_instance_id";
 546    case GS_OPCODE_FF_SYNC:
 547       return "ff_sync";
 548    case GS_OPCODE_SET_PRIMITIVE_ID:
 549       return "set_primitive_id";
 550    case GS_OPCODE_SVB_WRITE:
 551       return "gs_svb_write";
 552    case GS_OPCODE_SVB_SET_DST_INDEX:
 553       return "gs_svb_set_dst_index";
 554    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 555       return "gs_ff_sync_set_primitives";
 556    case CS_OPCODE_CS_TERMINATE:
 557       return "cs_terminate";
 558    case SHADER_OPCODE_BARRIER:
 559       return "barrier";
 560    case SHADER_OPCODE_MULH:
 561       return "mulh";
 562    case SHADER_OPCODE_MOV_INDIRECT:
 563       return "mov_indirect";
 564
 565    case VEC4_OPCODE_URB_READ:
 566       return "urb_read";
 567    case TCS_OPCODE_GET_INSTANCE_ID:
 568       return "tcs_get_instance_id";
 569    case TCS_OPCODE_URB_WRITE:
 570       return "tcs_urb_write";
 571    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 572       return "tcs_set_input_urb_offsets";
 573    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 574       return "tcs_set_output_urb_offsets";
 575    case TCS_OPCODE_GET_PRIMITIVE_ID:
 576       return "tcs_get_primitive_id";
 577    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 578       return "tcs_create_barrier_header";
 579    case TCS_OPCODE_SRC0_010_IS_ZERO:
 580       return "tcs_src0<0,1,0>_is_zero";
 581    case TCS_OPCODE_RELEASE_INPUT:
 582       return "tcs_release_input";
 583    case TCS_OPCODE_THREAD_END:
 584       return "tcs_thread_end";
 585    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 586       return "tes_create_input_read_header";
 587    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 588       return "tes_add_indirect_urb_offset";
 589    case TES_OPCODE_GET_PRIMITIVE_ID:
 590       return "tes_get_primitive_id";
 591    }
 592
 593    unreachable("not reached");
 594 }
 595
 596 bool
 597 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 598 {
 599    union {
 600       unsigned ud;
 601       int d;
 602       float f;
 603    } imm = { reg->ud }, sat_imm = { 0 };
 604
 605    switch (type) {
 606    case BRW_REGISTER_TYPE_UD:
 607    case BRW_REGISTER_TYPE_D:
 608    case BRW_REGISTER_TYPE_UW:
 609    case BRW_REGISTER_TYPE_W:
 610    case BRW_REGISTER_TYPE_UQ:
 611    case BRW_REGISTER_TYPE_Q:
 612       /* Nothing to do. */
 613       return false;
 614    case BRW_REGISTER_TYPE_F:
 615       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 616       break;
 617    case BRW_REGISTER_TYPE_UB:
 618    case BRW_REGISTER_TYPE_B:
 619       unreachable("no UB/B immediates");
 620    case BRW_REGISTER_TYPE_V:
 621    case BRW_REGISTER_TYPE_UV:
 622    case BRW_REGISTER_TYPE_VF:
 623       unreachable("unimplemented: saturate vector immediate");
 624    case BRW_REGISTER_TYPE_DF:
 625    case BRW_REGISTER_TYPE_HF:
 626       unreachable("unimplemented: saturate DF/HF immediate");
 627    }
 628
 629    if (imm.ud != sat_imm.ud) {
 630       reg->ud = sat_imm.ud;
 631       return true;
 632    }
 633    return false;
 634 }
 635
 636 bool
 637 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 638 {
 639    switch (type) {
 640    case BRW_REGISTER_TYPE_D:
 641    case BRW_REGISTER_TYPE_UD:
 642       reg->d = -reg->d;
 643       return true;
 644    case BRW_REGISTER_TYPE_W:
 645    case BRW_REGISTER_TYPE_UW:
 646       reg->d = -(int16_t)reg->ud;
 647       return true;
 648    case BRW_REGISTER_TYPE_F:
 649       reg->f = -reg->f;
 650       return true;
 651    case BRW_REGISTER_TYPE_VF:
 652       reg->ud ^= 0x80808080;
 653       return true;
 654    case BRW_REGISTER_TYPE_UB:
 655    case BRW_REGISTER_TYPE_B:
 656       unreachable("no UB/B immediates");
 657    case BRW_REGISTER_TYPE_UV:
 658    case BRW_REGISTER_TYPE_V:
 659       assert(!"unimplemented: negate UV/V immediate");
 660    case BRW_REGISTER_TYPE_UQ:
 661    case BRW_REGISTER_TYPE_Q:
 662       assert(!"unimplemented: negate UQ/Q immediate");
 663    case BRW_REGISTER_TYPE_DF:
 664    case BRW_REGISTER_TYPE_HF:
 665       assert(!"unimplemented: negate DF/HF immediate");
 666    }
 667
 668    return false;
 669 }
 670
 671 bool
 672 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 673 {
 674    switch (type) {
 675    case BRW_REGISTER_TYPE_D:
 676       reg->d = abs(reg->d);
 677       return true;
 678    case BRW_REGISTER_TYPE_W:
 679       reg->d = abs((int16_t)reg->ud);
 680       return true;
 681    case BRW_REGISTER_TYPE_F:
 682       reg->f = fabsf(reg->f);
 683       return true;
 684    case BRW_REGISTER_TYPE_VF:
 685       reg->ud &= ~0x80808080;
 686       return true;
 687    case BRW_REGISTER_TYPE_UB:
 688    case BRW_REGISTER_TYPE_B:
 689       unreachable("no UB/B immediates");
 690    case BRW_REGISTER_TYPE_UQ:
 691    case BRW_REGISTER_TYPE_UD:
 692    case BRW_REGISTER_TYPE_UW:
 693    case BRW_REGISTER_TYPE_UV:
 694       /* Presumably the absolute value modifier on an unsigned source is a
 695        * nop, but it would be nice to confirm.
 696        */
 697       assert(!"unimplemented: abs unsigned immediate");
 698    case BRW_REGISTER_TYPE_V:
 699       assert(!"unimplemented: abs V immediate");
 700    case BRW_REGISTER_TYPE_Q:
 701       assert(!"unimplemented: abs Q immediate");
 702    case BRW_REGISTER_TYPE_DF:
 703    case BRW_REGISTER_TYPE_HF:
 704       assert(!"unimplemented: abs DF/HF immediate");
 705    }
 706
 707    return false;
 708 }
 709
 710 backend_shader::backend_shader(const struct brw_compiler *compiler,
 711                                void *log_data,
 712                                void *mem_ctx,
 713                                const nir_shader *shader,
 714                                struct brw_stage_prog_data *stage_prog_data)
 715    : compiler(compiler),
 716      log_data(log_data),
 717      devinfo(compiler->devinfo),
 718      nir(shader),
 719      stage_prog_data(stage_prog_data),
 720      mem_ctx(mem_ctx),
 721      cfg(NULL),
 722      stage(shader->stage)
 723 {
 724    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 725    stage_name = _mesa_shader_stage_to_string(stage);
 726    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 727 }
 728
 729 bool
 730 backend_reg::equals(const backend_reg &r) const
 731 {
 732    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 733           reg_offset == r.reg_offset;
 734 }
 735
 736 bool
 737 backend_reg::is_zero() const
 738 {
 739    if (file != IMM)
 740       return false;
 741
 742    return d == 0;
 743 }
 744
 745 bool
 746 backend_reg::is_one() const
 747 {
 748    if (file != IMM)
 749       return false;
 750
 751    return type == BRW_REGISTER_TYPE_F
 752           ? f == 1.0
 753           : d == 1;
 754 }
 755
 756 bool
 757 backend_reg::is_negative_one() const
 758 {
 759    if (file != IMM)
 760       return false;
 761
 762    switch (type) {
 763    case BRW_REGISTER_TYPE_F:
 764       return f == -1.0;
 765    case BRW_REGISTER_TYPE_D:
 766       return d == -1;
 767    default:
 768       return false;
 769    }
 770 }
 771
 772 bool
 773 backend_reg::is_null() const
 774 {
 775    return file == ARF && nr == BRW_ARF_NULL;
 776 }
 777
 778
 779 bool
 780 backend_reg::is_accumulator() const
 781 {
 782    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 783 }
 784
 785 bool
 786 backend_reg::in_range(const backend_reg &r, unsigned n) const
 787 {
 788    return (file == r.file &&
 789            nr == r.nr &&
 790            reg_offset >= r.reg_offset &&
 791            reg_offset < r.reg_offset + n);
 792 }
 793
 794 bool
 795 backend_instruction::is_commutative() const
 796 {
 797    switch (opcode) {
 798    case BRW_OPCODE_AND:
 799    case BRW_OPCODE_OR:
 800    case BRW_OPCODE_XOR:
 801    case BRW_OPCODE_ADD:
 802    case BRW_OPCODE_MUL:
 803    case SHADER_OPCODE_MULH:
 804       return true;
 805    case BRW_OPCODE_SEL:
 806       /* MIN and MAX are commutative. */
 807       if (conditional_mod == BRW_CONDITIONAL_GE ||
 808           conditional_mod == BRW_CONDITIONAL_L) {
 809          return true;
 810       }
 811       /* fallthrough */
 812    default:
 813       return false;
 814    }
 815 }
 816
 817 bool
 818 backend_instruction::is_3src() const
 819 {
 820    return ::is_3src(opcode);
 821 }
 822
 823 bool
 824 backend_instruction::is_tex() const
 825 {
 826    return (opcode == SHADER_OPCODE_TEX ||
 827            opcode == FS_OPCODE_TXB ||
 828            opcode == SHADER_OPCODE_TXD ||
 829            opcode == SHADER_OPCODE_TXF ||
 830            opcode == SHADER_OPCODE_TXF_CMS ||
 831            opcode == SHADER_OPCODE_TXF_CMS_W ||
 832            opcode == SHADER_OPCODE_TXF_UMS ||
 833            opcode == SHADER_OPCODE_TXF_MCS ||
 834            opcode == SHADER_OPCODE_TXL ||
 835            opcode == SHADER_OPCODE_TXS ||
 836            opcode == SHADER_OPCODE_LOD ||
 837            opcode == SHADER_OPCODE_TG4 ||
 838            opcode == SHADER_OPCODE_TG4_OFFSET);
 839 }
 840
 841 bool
 842 backend_instruction::is_math() const
 843 {
 844    return (opcode == SHADER_OPCODE_RCP ||
 845            opcode == SHADER_OPCODE_RSQ ||
 846            opcode == SHADER_OPCODE_SQRT ||
 847            opcode == SHADER_OPCODE_EXP2 ||
 848            opcode == SHADER_OPCODE_LOG2 ||
 849            opcode == SHADER_OPCODE_SIN ||
 850            opcode == SHADER_OPCODE_COS ||
 851            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 852            opcode == SHADER_OPCODE_INT_REMAINDER ||
 853            opcode == SHADER_OPCODE_POW);
 854 }
 855
 856 bool
 857 backend_instruction::is_control_flow() const
 858 {
 859    switch (opcode) {
 860    case BRW_OPCODE_DO:
 861    case BRW_OPCODE_WHILE:
 862    case BRW_OPCODE_IF:
 863    case BRW_OPCODE_ELSE:
 864    case BRW_OPCODE_ENDIF:
 865    case BRW_OPCODE_BREAK:
 866    case BRW_OPCODE_CONTINUE:
 867       return true;
 868    default:
 869       return false;
 870    }
 871 }
 872
 873 bool
 874 backend_instruction::can_do_source_mods() const
 875 {
 876    switch (opcode) {
 877    case BRW_OPCODE_ADDC:
 878    case BRW_OPCODE_BFE:
 879    case BRW_OPCODE_BFI1:
 880    case BRW_OPCODE_BFI2:
 881    case BRW_OPCODE_BFREV:
 882    case BRW_OPCODE_CBIT:
 883    case BRW_OPCODE_FBH:
 884    case BRW_OPCODE_FBL:
 885    case BRW_OPCODE_SUBB:
 886       return false;
 887    default:
 888       return true;
 889    }
 890 }
 891
 892 bool
 893 backend_instruction::can_do_saturate() const
 894 {
 895    switch (opcode) {
 896    case BRW_OPCODE_ADD:
 897    case BRW_OPCODE_ASR:
 898    case BRW_OPCODE_AVG:
 899    case BRW_OPCODE_DP2:
 900    case BRW_OPCODE_DP3:
 901    case BRW_OPCODE_DP4:
 902    case BRW_OPCODE_DPH:
 903    case BRW_OPCODE_F16TO32:
 904    case BRW_OPCODE_F32TO16:
 905    case BRW_OPCODE_LINE:
 906    case BRW_OPCODE_LRP:
 907    case BRW_OPCODE_MAC:
 908    case BRW_OPCODE_MAD:
 909    case BRW_OPCODE_MATH:
 910    case BRW_OPCODE_MOV:
 911    case BRW_OPCODE_MUL:
 912    case SHADER_OPCODE_MULH:
 913    case BRW_OPCODE_PLN:
 914    case BRW_OPCODE_RNDD:
 915    case BRW_OPCODE_RNDE:
 916    case BRW_OPCODE_RNDU:
 917    case BRW_OPCODE_RNDZ:
 918    case BRW_OPCODE_SEL:
 919    case BRW_OPCODE_SHL:
 920    case BRW_OPCODE_SHR:
 921    case FS_OPCODE_LINTERP:
 922    case SHADER_OPCODE_COS:
 923    case SHADER_OPCODE_EXP2:
 924    case SHADER_OPCODE_LOG2:
 925    case SHADER_OPCODE_POW:
 926    case SHADER_OPCODE_RCP:
 927    case SHADER_OPCODE_RSQ:
 928    case SHADER_OPCODE_SIN:
 929    case SHADER_OPCODE_SQRT:
 930       return true;
 931    default:
 932       return false;
 933    }
 934 }
 935
 936 bool
 937 backend_instruction::can_do_cmod() const
 938 {
 939    switch (opcode) {
 940    case BRW_OPCODE_ADD:
 941    case BRW_OPCODE_ADDC:
 942    case BRW_OPCODE_AND:
 943    case BRW_OPCODE_ASR:
 944    case BRW_OPCODE_AVG:
 945    case BRW_OPCODE_CMP:
 946    case BRW_OPCODE_CMPN:
 947    case BRW_OPCODE_DP2:
 948    case BRW_OPCODE_DP3:
 949    case BRW_OPCODE_DP4:
 950    case BRW_OPCODE_DPH:
 951    case BRW_OPCODE_F16TO32:
 952    case BRW_OPCODE_F32TO16:
 953    case BRW_OPCODE_FRC:
 954    case BRW_OPCODE_LINE:
 955    case BRW_OPCODE_LRP:
 956    case BRW_OPCODE_LZD:
 957    case BRW_OPCODE_MAC:
 958    case BRW_OPCODE_MACH:
 959    case BRW_OPCODE_MAD:
 960    case BRW_OPCODE_MOV:
 961    case BRW_OPCODE_MUL:
 962    case BRW_OPCODE_NOT:
 963    case BRW_OPCODE_OR:
 964    case BRW_OPCODE_PLN:
 965    case BRW_OPCODE_RNDD:
 966    case BRW_OPCODE_RNDE:
 967    case BRW_OPCODE_RNDU:
 968    case BRW_OPCODE_RNDZ:
 969    case BRW_OPCODE_SAD2:
 970    case BRW_OPCODE_SADA2:
 971    case BRW_OPCODE_SHL:
 972    case BRW_OPCODE_SHR:
 973    case BRW_OPCODE_SUBB:
 974    case BRW_OPCODE_XOR:
 975    case FS_OPCODE_CINTERP:
 976    case FS_OPCODE_LINTERP:
 977       return true;
 978    default:
 979       return false;
 980    }
 981 }
 982
 983 bool
 984 backend_instruction::reads_accumulator_implicitly() const
 985 {
 986    switch (opcode) {
 987    case BRW_OPCODE_MAC:
 988    case BRW_OPCODE_MACH:
 989    case BRW_OPCODE_SADA2:
 990       return true;
 991    default:
 992       return false;
 993    }
 994 }
 995
 996 bool
 997 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 998 {
 999    return writes_accumulator ||
1000           (devinfo->gen < 6 &&
1001            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1002             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1003              opcode != FS_OPCODE_CINTERP)));
1004 }
1005
1006 bool
1007 backend_instruction::has_side_effects() const
1008 {
1009    switch (opcode) {
1010    case SHADER_OPCODE_UNTYPED_ATOMIC:
1011    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1012    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1013    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1014    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1015    case SHADER_OPCODE_TYPED_ATOMIC:
1016    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1017    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1018    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1019    case SHADER_OPCODE_MEMORY_FENCE:
1020    case SHADER_OPCODE_URB_WRITE_SIMD8:
1021    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1022    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1023    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1024    case FS_OPCODE_FB_WRITE:
1025    case SHADER_OPCODE_BARRIER:
1026    case TCS_OPCODE_RELEASE_INPUT:
1027       return true;
1028    default:
1029       return false;
1030    }
1031 }
1032
1033 bool
1034 backend_instruction::is_volatile() const
1035 {
1036    switch (opcode) {
1037    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1038    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1039    case SHADER_OPCODE_TYPED_SURFACE_READ:
1040    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1041       return true;
1042    default:
1043       return false;
1044    }
1045 }
1046
1047 #ifndef NDEBUG
1048 static bool
1049 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1050 {
1051    bool found = false;
1052    foreach_inst_in_block (backend_instruction, i, block) {
1053       if (inst == i) {
1054          found = true;
1055       }
1056    }
1057    return found;
1058 }
1059 #endif
1060
1061 static void
1062 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1063 {
1064    for (bblock_t *block_iter = start_block->next();
1065         !block_iter->link.is_tail_sentinel();
1066         block_iter = block_iter->next()) {
1067       block_iter->start_ip += ip_adjustment;
1068       block_iter->end_ip += ip_adjustment;
1069    }
1070 }
1071
1072 void
1073 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1074 {
1075    if (!this->is_head_sentinel())
1076       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1077
1078    block->end_ip++;
1079
1080    adjust_later_block_ips(block, 1);
1081
1082    exec_node::insert_after(inst);
1083 }
1084
1085 void
1086 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1087 {
1088    if (!this->is_tail_sentinel())
1089       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1090
1091    block->end_ip++;
1092
1093    adjust_later_block_ips(block, 1);
1094
1095    exec_node::insert_before(inst);
1096 }
1097
1098 void
1099 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1100 {
1101    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1102
1103    unsigned num_inst = list->length();
1104
1105    block->end_ip += num_inst;
1106
1107    adjust_later_block_ips(block, num_inst);
1108
1109    exec_node::insert_before(list);
1110 }
1111
1112 void
1113 backend_instruction::remove(bblock_t *block)
1114 {
1115    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1116
1117    adjust_later_block_ips(block, -1);
1118
1119    if (block->start_ip == block->end_ip) {
1120       block->cfg->remove_block(block);
1121    } else {
1122       block->end_ip--;
1123    }
1124
1125    exec_node::remove();
1126 }
1127
1128 void
1129 backend_shader::dump_instructions()
1130 {
1131    dump_instructions(NULL);
1132 }
1133
1134 void
1135 backend_shader::dump_instructions(const char *name)
1136 {
1137    FILE *file = stderr;
1138    if (name && geteuid() != 0) {
1139       file = fopen(name, "w");
1140       if (!file)
1141          file = stderr;
1142    }
1143
1144    if (cfg) {
1145       int ip = 0;
1146       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1147          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1148             fprintf(file, "%4d: ", ip++);
1149          dump_instruction(inst, file);
1150       }
1151    } else {
1152       int ip = 0;
1153       foreach_in_list(backend_instruction, inst, &instructions) {
1154          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1155             fprintf(file, "%4d: ", ip++);
1156          dump_instruction(inst, file);
1157       }
1158    }
1159
1160    if (file != stderr) {
1161       fclose(file);
1162    }
1163 }
1164
1165 void
1166 backend_shader::calculate_cfg()
1167 {
1168    if (this->cfg)
1169       return;
1170    cfg = new(mem_ctx) cfg_t(&this->instructions);
1171 }
1172
1173 void
1174 backend_shader::invalidate_cfg()
1175 {
1176    ralloc_free(this->cfg);
1177    this->cfg = NULL;
1178 }
1179
1180 /**
1181  * Sets up the starting offsets for the groups of binding table entries
1182  * commong to all pipeline stages.
1183  *
1184  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1185  * unused but also make sure that addition of small offsets to them will
1186  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1187  */
1188 void
1189 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1190                                         const struct brw_device_info *devinfo,
1191                                         const struct gl_shader_program *shader_prog,
1192                                         const struct gl_program *prog,
1193                                         struct brw_stage_prog_data *stage_prog_data,
1194                                         uint32_t next_binding_table_offset)
1195 {
1196    const struct gl_shader *shader = NULL;
1197    int num_textures = _mesa_fls(prog->SamplersUsed);
1198
1199    if (shader_prog)
1200       shader = shader_prog->_LinkedShaders[stage];
1201
1202    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1203    next_binding_table_offset += num_textures;
1204
1205    if (shader) {
1206       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1207       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1208       next_binding_table_offset += shader->NumUniformBlocks;
1209
1210       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1211       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1212       next_binding_table_offset += shader->NumShaderStorageBlocks;
1213    } else {
1214       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1215       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1216    }
1217
1218    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1219       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1220       next_binding_table_offset++;
1221    } else {
1222       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1223    }
1224
1225    if (prog->UsesGather) {
1226       if (devinfo->gen >= 8) {
1227          stage_prog_data->binding_table.gather_texture_start =
1228             stage_prog_data->binding_table.texture_start;
1229       } else {
1230          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1231          next_binding_table_offset += num_textures;
1232       }
1233    } else {
1234       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1235    }
1236
1237    if (shader && shader->NumAtomicBuffers) {
1238       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1239       next_binding_table_offset += shader->NumAtomicBuffers;
1240    } else {
1241       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1242    }
1243
1244    if (shader && shader->NumImages) {
1245       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1246       next_binding_table_offset += shader->NumImages;
1247    } else {
1248       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1249    }
1250
1251    /* This may or may not be used depending on how the compile goes. */
1252    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1253    next_binding_table_offset++;
1254
1255    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1256
1257    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1258 }
1259
1260 static void
1261 setup_vec4_uniform_value(const gl_constant_value **params,
1262                          const gl_constant_value *values,
1263                          unsigned n)
1264 {
1265    static const gl_constant_value zero = { 0 };
1266
1267    for (unsigned i = 0; i < n; ++i)
1268       params[i] = &values[i];
1269
1270    for (unsigned i = n; i < 4; ++i)
1271       params[i] = &zero;
1272 }
1273
1274 void
1275 brw_setup_image_uniform_values(gl_shader_stage stage,
1276                                struct brw_stage_prog_data *stage_prog_data,
1277                                unsigned param_start_index,
1278                                const gl_uniform_storage *storage)
1279 {
1280    const gl_constant_value **param =
1281       &stage_prog_data->param[param_start_index];
1282
1283    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1284       const unsigned image_idx = storage->opaque[stage].index + i;
1285       const brw_image_param *image_param =
1286          &stage_prog_data->image_param[image_idx];
1287
1288       /* Upload the brw_image_param structure.  The order is expected to match
1289        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1290        */
1291       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1292          (const gl_constant_value *)&image_param->surface_idx, 1);
1293       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1294          (const gl_constant_value *)image_param->offset, 2);
1295       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1296          (const gl_constant_value *)image_param->size, 3);
1297       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1298          (const gl_constant_value *)image_param->stride, 4);
1299       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1300          (const gl_constant_value *)image_param->tiling, 3);
1301       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1302          (const gl_constant_value *)image_param->swizzling, 2);
1303       param += BRW_IMAGE_PARAM_SIZE;
1304
1305       brw_mark_surface_used(
1306          stage_prog_data,
1307          stage_prog_data->binding_table.image_start + image_idx);
1308    }
1309 }
1310
1311 /**
1312  * Decide which set of clip planes should be used when clipping via
1313  * gl_Position or gl_ClipVertex.
1314  */
1315 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1316 {
1317    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1318       /* There is currently a GLSL vertex shader, so clip according to GLSL
1319        * rules, which means compare gl_ClipVertex (or gl_Position, if
1320        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1321        * that were stored in EyeUserPlane at the time the clip planes were
1322        * specified.
1323        */
1324       return ctx->Transform.EyeUserPlane;
1325    } else {
1326       /* Either we are using fixed function or an ARB vertex program.  In
1327        * either case the clip planes are going to be compared against
1328        * gl_Position (which is in clip coordinates) so we have to clip using
1329        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1330        * core.
1331        */
1332       return ctx->Transform._ClipUserPlane;
1333    }
1334 }
1335
1336 extern "C" const unsigned *
1337 brw_compile_tes(const struct brw_compiler *compiler,
1338                 void *log_data,
1339                 void *mem_ctx,
1340                 const struct brw_tes_prog_key *key,
1341                 struct brw_tes_prog_data *prog_data,
1342                 const nir_shader *src_shader,
1343                 struct gl_shader_program *shader_prog,
1344                 int shader_time_index,
1345                 unsigned *final_assembly_size,
1346                 char **error_str)
1347 {
1348    const struct brw_device_info *devinfo = compiler->devinfo;
1349    struct gl_shader *shader =
1350       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1351    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1352
1353    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1354    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1355    nir->info.inputs_read = key->inputs_read;
1356    nir->info.patch_inputs_read = key->patch_inputs_read;
1357    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
1358    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1359
1360    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1361                        nir->info.outputs_written,
1362                        nir->info.separate_shader);
1363
1364    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1365
1366    assert(output_size_bytes >= 1);
1367    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1368       if (error_str)
1369          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1370       return NULL;
1371    }
1372
1373    /* URB entry sizes are stored as a multiple of 64 bytes. */
1374    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1375
1376    struct brw_vue_map input_vue_map;
1377    brw_compute_tess_vue_map(&input_vue_map,
1378                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1379                             nir->info.patch_inputs_read);
1380
1381    bool need_patch_header = nir->info.system_values_read &
1382       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1383        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1384
1385    /* The TES will pull most inputs using URB read messages.
1386     *
1387     * However, we push the patch header for TessLevel factors when required,
1388     * as it's a tiny amount of extra data.
1389     */
1390    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1391
1392    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1393       fprintf(stderr, "TES Input ");
1394       brw_print_vue_map(stderr, &input_vue_map);
1395       fprintf(stderr, "TES Output ");
1396       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1397    }
1398
1399    if (is_scalar) {
1400       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1401                    &prog_data->base.base, shader->Program, nir, 8,
1402                    shader_time_index, &input_vue_map);
1403       if (!v.run_tes()) {
1404          if (error_str)
1405             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1406          return NULL;
1407       }
1408
1409       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1410
1411       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1412                      &prog_data->base.base, v.promoted_constants, false,
1413                      "TES");
1414       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1415          g.enable_debug(ralloc_asprintf(mem_ctx,
1416                                         "%s tessellation evaluation shader %s",
1417                                         nir->info.label ? nir->info.label
1418                                                         : "unnamed",
1419                                         nir->info.name));
1420       }
1421
1422       g.generate_code(v.cfg, 8);
1423
1424       return g.get_assembly(final_assembly_size);
1425    } else {
1426       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1427                               nir, mem_ctx, shader_time_index);
1428       if (!v.run()) {
1429          if (error_str)
1430             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1431          return NULL;
1432       }
1433
1434       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1435          v.dump_instructions();
1436
1437       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1438                                         &prog_data->base, v.cfg,
1439                                         final_assembly_size);
1440    }
1441 }