src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/uniforms.h"
  31
  32 extern "C" void
  33 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  34                       unsigned surf_index)
  35 {
  36    assert(surf_index < BRW_MAX_SURFACES);
  37
  38    prog_data->binding_table.size_bytes =
  39       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  40 }
  41
  42 enum brw_reg_type
  43 brw_type_for_base_type(const struct glsl_type *type)
  44 {
  45    switch (type->base_type) {
  46    case GLSL_TYPE_FLOAT:
  47       return BRW_REGISTER_TYPE_F;
  48    case GLSL_TYPE_INT:
  49    case GLSL_TYPE_BOOL:
  50    case GLSL_TYPE_SUBROUTINE:
  51       return BRW_REGISTER_TYPE_D;
  52    case GLSL_TYPE_UINT:
  53       return BRW_REGISTER_TYPE_UD;
  54    case GLSL_TYPE_ARRAY:
  55       return brw_type_for_base_type(type->fields.array);
  56    case GLSL_TYPE_STRUCT:
  57    case GLSL_TYPE_SAMPLER:
  58    case GLSL_TYPE_ATOMIC_UINT:
  59       /* These should be overridden with the type of the member when
  60        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  61        * way to trip up if we don't.
  62        */
  63       return BRW_REGISTER_TYPE_UD;
  64    case GLSL_TYPE_IMAGE:
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_DOUBLE:
  67       return BRW_REGISTER_TYPE_DF;
  68    case GLSL_TYPE_VOID:
  69    case GLSL_TYPE_ERROR:
  70    case GLSL_TYPE_INTERFACE:
  71    case GLSL_TYPE_FUNCTION:
  72       unreachable("not reached");
  73    }
  74
  75    return BRW_REGISTER_TYPE_F;
  76 }
  77
  78 enum brw_conditional_mod
  79 brw_conditional_for_comparison(unsigned int op)
  80 {
  81    switch (op) {
  82    case ir_binop_less:
  83       return BRW_CONDITIONAL_L;
  84    case ir_binop_greater:
  85       return BRW_CONDITIONAL_G;
  86    case ir_binop_lequal:
  87       return BRW_CONDITIONAL_LE;
  88    case ir_binop_gequal:
  89       return BRW_CONDITIONAL_GE;
  90    case ir_binop_equal:
  91    case ir_binop_all_equal: /* same as equal for scalars */
  92       return BRW_CONDITIONAL_Z;
  93    case ir_binop_nequal:
  94    case ir_binop_any_nequal: /* same as nequal for scalars */
  95       return BRW_CONDITIONAL_NZ;
  96    default:
  97       unreachable("not reached: bad operation for comparison");
  98    }
  99 }
 100
 101 uint32_t
 102 brw_math_function(enum opcode op)
 103 {
 104    switch (op) {
 105    case SHADER_OPCODE_RCP:
 106       return BRW_MATH_FUNCTION_INV;
 107    case SHADER_OPCODE_RSQ:
 108       return BRW_MATH_FUNCTION_RSQ;
 109    case SHADER_OPCODE_SQRT:
 110       return BRW_MATH_FUNCTION_SQRT;
 111    case SHADER_OPCODE_EXP2:
 112       return BRW_MATH_FUNCTION_EXP;
 113    case SHADER_OPCODE_LOG2:
 114       return BRW_MATH_FUNCTION_LOG;
 115    case SHADER_OPCODE_POW:
 116       return BRW_MATH_FUNCTION_POW;
 117    case SHADER_OPCODE_SIN:
 118       return BRW_MATH_FUNCTION_SIN;
 119    case SHADER_OPCODE_COS:
 120       return BRW_MATH_FUNCTION_COS;
 121    case SHADER_OPCODE_INT_QUOTIENT:
 122       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 123    case SHADER_OPCODE_INT_REMAINDER:
 124       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 125    default:
 126       unreachable("not reached: unknown math function");
 127    }
 128 }
 129
 130 uint32_t
 131 brw_texture_offset(int *offsets, unsigned num_components)
 132 {
 133    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 134
 135    /* Combine all three offsets into a single unsigned dword:
 136     *
 137     *    bits 11:8 - U Offset (X component)
 138     *    bits  7:4 - V Offset (Y component)
 139     *    bits  3:0 - R Offset (Z component)
 140     */
 141    unsigned offset_bits = 0;
 142    for (unsigned i = 0; i < num_components; i++) {
 143       const unsigned shift = 4 * (2 - i);
 144       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 145    }
 146    return offset_bits;
 147 }
 148
 149 const char *
 150 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
 151 {
 152    switch (op) {
 153    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 154       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 155        * start of a loop in the IR.
 156        */
 157       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 158          return "do";
 159
 160       assert(brw_opcode_desc(devinfo, op)->name);
 161       return brw_opcode_desc(devinfo, op)->name;
 162    case FS_OPCODE_FB_WRITE:
 163       return "fb_write";
 164    case FS_OPCODE_FB_WRITE_LOGICAL:
 165       return "fb_write_logical";
 166    case FS_OPCODE_REP_FB_WRITE:
 167       return "rep_fb_write";
 168
 169    case SHADER_OPCODE_RCP:
 170       return "rcp";
 171    case SHADER_OPCODE_RSQ:
 172       return "rsq";
 173    case SHADER_OPCODE_SQRT:
 174       return "sqrt";
 175    case SHADER_OPCODE_EXP2:
 176       return "exp2";
 177    case SHADER_OPCODE_LOG2:
 178       return "log2";
 179    case SHADER_OPCODE_POW:
 180       return "pow";
 181    case SHADER_OPCODE_INT_QUOTIENT:
 182       return "int_quot";
 183    case SHADER_OPCODE_INT_REMAINDER:
 184       return "int_rem";
 185    case SHADER_OPCODE_SIN:
 186       return "sin";
 187    case SHADER_OPCODE_COS:
 188       return "cos";
 189
 190    case SHADER_OPCODE_TEX:
 191       return "tex";
 192    case SHADER_OPCODE_TEX_LOGICAL:
 193       return "tex_logical";
 194    case SHADER_OPCODE_TXD:
 195       return "txd";
 196    case SHADER_OPCODE_TXD_LOGICAL:
 197       return "txd_logical";
 198    case SHADER_OPCODE_TXF:
 199       return "txf";
 200    case SHADER_OPCODE_TXF_LOGICAL:
 201       return "txf_logical";
 202    case SHADER_OPCODE_TXF_LZ:
 203       return "txf_lz";
 204    case SHADER_OPCODE_TXL:
 205       return "txl";
 206    case SHADER_OPCODE_TXL_LOGICAL:
 207       return "txl_logical";
 208    case SHADER_OPCODE_TXL_LZ:
 209       return "txl_lz";
 210    case SHADER_OPCODE_TXS:
 211       return "txs";
 212    case SHADER_OPCODE_TXS_LOGICAL:
 213       return "txs_logical";
 214    case FS_OPCODE_TXB:
 215       return "txb";
 216    case FS_OPCODE_TXB_LOGICAL:
 217       return "txb_logical";
 218    case SHADER_OPCODE_TXF_CMS:
 219       return "txf_cms";
 220    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 221       return "txf_cms_logical";
 222    case SHADER_OPCODE_TXF_CMS_W:
 223       return "txf_cms_w";
 224    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 225       return "txf_cms_w_logical";
 226    case SHADER_OPCODE_TXF_UMS:
 227       return "txf_ums";
 228    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 229       return "txf_ums_logical";
 230    case SHADER_OPCODE_TXF_MCS:
 231       return "txf_mcs";
 232    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 233       return "txf_mcs_logical";
 234    case SHADER_OPCODE_LOD:
 235       return "lod";
 236    case SHADER_OPCODE_LOD_LOGICAL:
 237       return "lod_logical";
 238    case SHADER_OPCODE_TG4:
 239       return "tg4";
 240    case SHADER_OPCODE_TG4_LOGICAL:
 241       return "tg4_logical";
 242    case SHADER_OPCODE_TG4_OFFSET:
 243       return "tg4_offset";
 244    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 245       return "tg4_offset_logical";
 246    case SHADER_OPCODE_SAMPLEINFO:
 247       return "sampleinfo";
 248    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 249       return "sampleinfo_logical";
 250
 251    case SHADER_OPCODE_SHADER_TIME_ADD:
 252       return "shader_time_add";
 253
 254    case SHADER_OPCODE_UNTYPED_ATOMIC:
 255       return "untyped_atomic";
 256    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 257       return "untyped_atomic_logical";
 258    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 259       return "untyped_surface_read";
 260    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 261       return "untyped_surface_read_logical";
 262    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 263       return "untyped_surface_write";
 264    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 265       return "untyped_surface_write_logical";
 266    case SHADER_OPCODE_TYPED_ATOMIC:
 267       return "typed_atomic";
 268    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 269       return "typed_atomic_logical";
 270    case SHADER_OPCODE_TYPED_SURFACE_READ:
 271       return "typed_surface_read";
 272    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 273       return "typed_surface_read_logical";
 274    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 275       return "typed_surface_write";
 276    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 277       return "typed_surface_write_logical";
 278    case SHADER_OPCODE_MEMORY_FENCE:
 279       return "memory_fence";
 280
 281    case SHADER_OPCODE_LOAD_PAYLOAD:
 282       return "load_payload";
 283    case FS_OPCODE_PACK:
 284       return "pack";
 285
 286    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 287       return "gen4_scratch_read";
 288    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 289       return "gen4_scratch_write";
 290    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 291       return "gen7_scratch_read";
 292    case SHADER_OPCODE_URB_WRITE_SIMD8:
 293       return "gen8_urb_write_simd8";
 294    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 295       return "gen8_urb_write_simd8_per_slot";
 296    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 297       return "gen8_urb_write_simd8_masked";
 298    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 299       return "gen8_urb_write_simd8_masked_per_slot";
 300    case SHADER_OPCODE_URB_READ_SIMD8:
 301       return "urb_read_simd8";
 302    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 303       return "urb_read_simd8_per_slot";
 304
 305    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 306       return "find_live_channel";
 307    case SHADER_OPCODE_BROADCAST:
 308       return "broadcast";
 309
 310    case VEC4_OPCODE_MOV_BYTES:
 311       return "mov_bytes";
 312    case VEC4_OPCODE_PACK_BYTES:
 313       return "pack_bytes";
 314    case VEC4_OPCODE_UNPACK_UNIFORM:
 315       return "unpack_uniform";
 316
 317    case FS_OPCODE_DDX_COARSE:
 318       return "ddx_coarse";
 319    case FS_OPCODE_DDX_FINE:
 320       return "ddx_fine";
 321    case FS_OPCODE_DDY_COARSE:
 322       return "ddy_coarse";
 323    case FS_OPCODE_DDY_FINE:
 324       return "ddy_fine";
 325
 326    case FS_OPCODE_CINTERP:
 327       return "cinterp";
 328    case FS_OPCODE_LINTERP:
 329       return "linterp";
 330
 331    case FS_OPCODE_PIXEL_X:
 332       return "pixel_x";
 333    case FS_OPCODE_PIXEL_Y:
 334       return "pixel_y";
 335
 336    case FS_OPCODE_GET_BUFFER_SIZE:
 337       return "fs_get_buffer_size";
 338
 339    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 340       return "uniform_pull_const";
 341    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 342       return "uniform_pull_const_gen7";
 343    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 344       return "varying_pull_const_gen4";
 345    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 346       return "varying_pull_const_gen7";
 347    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 348       return "varying_pull_const_logical";
 349
 350    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 351       return "mov_dispatch_to_flags";
 352    case FS_OPCODE_DISCARD_JUMP:
 353       return "discard_jump";
 354
 355    case FS_OPCODE_SET_SAMPLE_ID:
 356       return "set_sample_id";
 357    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 358       return "set_simd4x2_offset";
 359
 360    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 361       return "pack_half_2x16_split";
 362    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 363       return "unpack_half_2x16_split_x";
 364    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 365       return "unpack_half_2x16_split_y";
 366
 367    case FS_OPCODE_PLACEHOLDER_HALT:
 368       return "placeholder_halt";
 369
 370    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 371       return "interp_centroid";
 372    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 373       return "interp_sample";
 374    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 375       return "interp_shared_offset";
 376    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 377       return "interp_per_slot_offset";
 378
 379    case VS_OPCODE_URB_WRITE:
 380       return "vs_urb_write";
 381    case VS_OPCODE_PULL_CONSTANT_LOAD:
 382       return "pull_constant_load";
 383    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 384       return "pull_constant_load_gen7";
 385
 386    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 387       return "set_simd4x2_header_gen9";
 388
 389    case VS_OPCODE_GET_BUFFER_SIZE:
 390       return "vs_get_buffer_size";
 391
 392    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 393       return "unpack_flags_simd4x2";
 394
 395    case GS_OPCODE_URB_WRITE:
 396       return "gs_urb_write";
 397    case GS_OPCODE_URB_WRITE_ALLOCATE:
 398       return "gs_urb_write_allocate";
 399    case GS_OPCODE_THREAD_END:
 400       return "gs_thread_end";
 401    case GS_OPCODE_SET_WRITE_OFFSET:
 402       return "set_write_offset";
 403    case GS_OPCODE_SET_VERTEX_COUNT:
 404       return "set_vertex_count";
 405    case GS_OPCODE_SET_DWORD_2:
 406       return "set_dword_2";
 407    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 408       return "prepare_channel_masks";
 409    case GS_OPCODE_SET_CHANNEL_MASKS:
 410       return "set_channel_masks";
 411    case GS_OPCODE_GET_INSTANCE_ID:
 412       return "get_instance_id";
 413    case GS_OPCODE_FF_SYNC:
 414       return "ff_sync";
 415    case GS_OPCODE_SET_PRIMITIVE_ID:
 416       return "set_primitive_id";
 417    case GS_OPCODE_SVB_WRITE:
 418       return "gs_svb_write";
 419    case GS_OPCODE_SVB_SET_DST_INDEX:
 420       return "gs_svb_set_dst_index";
 421    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 422       return "gs_ff_sync_set_primitives";
 423    case CS_OPCODE_CS_TERMINATE:
 424       return "cs_terminate";
 425    case SHADER_OPCODE_BARRIER:
 426       return "barrier";
 427    case SHADER_OPCODE_MULH:
 428       return "mulh";
 429    case SHADER_OPCODE_MOV_INDIRECT:
 430       return "mov_indirect";
 431
 432    case VEC4_OPCODE_URB_READ:
 433       return "urb_read";
 434    case TCS_OPCODE_GET_INSTANCE_ID:
 435       return "tcs_get_instance_id";
 436    case TCS_OPCODE_URB_WRITE:
 437       return "tcs_urb_write";
 438    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 439       return "tcs_set_input_urb_offsets";
 440    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 441       return "tcs_set_output_urb_offsets";
 442    case TCS_OPCODE_GET_PRIMITIVE_ID:
 443       return "tcs_get_primitive_id";
 444    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 445       return "tcs_create_barrier_header";
 446    case TCS_OPCODE_SRC0_010_IS_ZERO:
 447       return "tcs_src0<0,1,0>_is_zero";
 448    case TCS_OPCODE_RELEASE_INPUT:
 449       return "tcs_release_input";
 450    case TCS_OPCODE_THREAD_END:
 451       return "tcs_thread_end";
 452    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 453       return "tes_create_input_read_header";
 454    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 455       return "tes_add_indirect_urb_offset";
 456    case TES_OPCODE_GET_PRIMITIVE_ID:
 457       return "tes_get_primitive_id";
 458    }
 459
 460    unreachable("not reached");
 461 }
 462
 463 bool
 464 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 465 {
 466    union {
 467       unsigned ud;
 468       int d;
 469       float f;
 470       double df;
 471    } imm, sat_imm = { 0 };
 472
 473    const unsigned size = type_sz(type);
 474
 475    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 476     * irrelevant, so just check the size of the type and copy from/to an
 477     * appropriately sized field.
 478     */
 479    if (size < 8)
 480       imm.ud = reg->ud;
 481    else
 482       imm.df = reg->df;
 483
 484    switch (type) {
 485    case BRW_REGISTER_TYPE_UD:
 486    case BRW_REGISTER_TYPE_D:
 487    case BRW_REGISTER_TYPE_UW:
 488    case BRW_REGISTER_TYPE_W:
 489    case BRW_REGISTER_TYPE_UQ:
 490    case BRW_REGISTER_TYPE_Q:
 491       /* Nothing to do. */
 492       return false;
 493    case BRW_REGISTER_TYPE_F:
 494       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 495       break;
 496    case BRW_REGISTER_TYPE_DF:
 497       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 498       break;
 499    case BRW_REGISTER_TYPE_UB:
 500    case BRW_REGISTER_TYPE_B:
 501       unreachable("no UB/B immediates");
 502    case BRW_REGISTER_TYPE_V:
 503    case BRW_REGISTER_TYPE_UV:
 504    case BRW_REGISTER_TYPE_VF:
 505       unreachable("unimplemented: saturate vector immediate");
 506    case BRW_REGISTER_TYPE_HF:
 507       unreachable("unimplemented: saturate HF immediate");
 508    }
 509
 510    if (size < 8) {
 511       if (imm.ud != sat_imm.ud) {
 512          reg->ud = sat_imm.ud;
 513          return true;
 514       }
 515    } else {
 516       if (imm.df != sat_imm.df) {
 517          reg->df = sat_imm.df;
 518          return true;
 519       }
 520    }
 521    return false;
 522 }
 523
 524 bool
 525 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 526 {
 527    switch (type) {
 528    case BRW_REGISTER_TYPE_D:
 529    case BRW_REGISTER_TYPE_UD:
 530       reg->d = -reg->d;
 531       return true;
 532    case BRW_REGISTER_TYPE_W:
 533    case BRW_REGISTER_TYPE_UW:
 534       reg->d = -(int16_t)reg->ud;
 535       return true;
 536    case BRW_REGISTER_TYPE_F:
 537       reg->f = -reg->f;
 538       return true;
 539    case BRW_REGISTER_TYPE_VF:
 540       reg->ud ^= 0x80808080;
 541       return true;
 542    case BRW_REGISTER_TYPE_DF:
 543       reg->df = -reg->df;
 544       return true;
 545    case BRW_REGISTER_TYPE_UB:
 546    case BRW_REGISTER_TYPE_B:
 547       unreachable("no UB/B immediates");
 548    case BRW_REGISTER_TYPE_UV:
 549    case BRW_REGISTER_TYPE_V:
 550       assert(!"unimplemented: negate UV/V immediate");
 551    case BRW_REGISTER_TYPE_UQ:
 552    case BRW_REGISTER_TYPE_Q:
 553       assert(!"unimplemented: negate UQ/Q immediate");
 554    case BRW_REGISTER_TYPE_HF:
 555       assert(!"unimplemented: negate HF immediate");
 556    }
 557
 558    return false;
 559 }
 560
 561 bool
 562 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 563 {
 564    switch (type) {
 565    case BRW_REGISTER_TYPE_D:
 566       reg->d = abs(reg->d);
 567       return true;
 568    case BRW_REGISTER_TYPE_W:
 569       reg->d = abs((int16_t)reg->ud);
 570       return true;
 571    case BRW_REGISTER_TYPE_F:
 572       reg->f = fabsf(reg->f);
 573       return true;
 574    case BRW_REGISTER_TYPE_DF:
 575       reg->df = fabs(reg->df);
 576       return true;
 577    case BRW_REGISTER_TYPE_VF:
 578       reg->ud &= ~0x80808080;
 579       return true;
 580    case BRW_REGISTER_TYPE_UB:
 581    case BRW_REGISTER_TYPE_B:
 582       unreachable("no UB/B immediates");
 583    case BRW_REGISTER_TYPE_UQ:
 584    case BRW_REGISTER_TYPE_UD:
 585    case BRW_REGISTER_TYPE_UW:
 586    case BRW_REGISTER_TYPE_UV:
 587       /* Presumably the absolute value modifier on an unsigned source is a
 588        * nop, but it would be nice to confirm.
 589        */
 590       assert(!"unimplemented: abs unsigned immediate");
 591    case BRW_REGISTER_TYPE_V:
 592       assert(!"unimplemented: abs V immediate");
 593    case BRW_REGISTER_TYPE_Q:
 594       assert(!"unimplemented: abs Q immediate");
 595    case BRW_REGISTER_TYPE_HF:
 596       assert(!"unimplemented: abs HF immediate");
 597    }
 598
 599    return false;
 600 }
 601
 602 unsigned
 603 tesslevel_outer_components(GLenum tes_primitive_mode)
 604 {
 605    switch (tes_primitive_mode) {
 606    case GL_QUADS:
 607       return 4;
 608    case GL_TRIANGLES:
 609       return 3;
 610    case GL_ISOLINES:
 611       return 2;
 612    default:
 613       unreachable("Bogus tessellation domain");
 614    }
 615    return 0;
 616 }
 617
 618 unsigned
 619 tesslevel_inner_components(GLenum tes_primitive_mode)
 620 {
 621    switch (tes_primitive_mode) {
 622    case GL_QUADS:
 623       return 2;
 624    case GL_TRIANGLES:
 625       return 1;
 626    case GL_ISOLINES:
 627       return 0;
 628    default:
 629       unreachable("Bogus tessellation domain");
 630    }
 631    return 0;
 632 }
 633
 634 /**
 635  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 636  * that's stored backwards, i.e. .wzyx.
 637  */
 638 unsigned
 639 writemask_for_backwards_vector(unsigned mask)
 640 {
 641    unsigned new_mask = 0;
 642
 643    for (int i = 0; i < 4; i++)
 644       new_mask |= ((mask >> i) & 1) << (3 - i);
 645
 646    return new_mask;
 647 }
 648
 649 backend_shader::backend_shader(const struct brw_compiler *compiler,
 650                                void *log_data,
 651                                void *mem_ctx,
 652                                const nir_shader *shader,
 653                                struct brw_stage_prog_data *stage_prog_data)
 654    : compiler(compiler),
 655      log_data(log_data),
 656      devinfo(compiler->devinfo),
 657      nir(shader),
 658      stage_prog_data(stage_prog_data),
 659      mem_ctx(mem_ctx),
 660      cfg(NULL),
 661      stage(shader->stage)
 662 {
 663    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 664    stage_name = _mesa_shader_stage_to_string(stage);
 665    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 666    is_passthrough_shader =
 667       nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
 668 }
 669
 670 bool
 671 backend_reg::equals(const backend_reg &r) const
 672 {
 673    return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
 674 }
 675
 676 bool
 677 backend_reg::is_zero() const
 678 {
 679    if (file != IMM)
 680       return false;
 681
 682    switch (type) {
 683    case BRW_REGISTER_TYPE_F:
 684       return f == 0;
 685    case BRW_REGISTER_TYPE_DF:
 686       return df == 0;
 687    case BRW_REGISTER_TYPE_D:
 688    case BRW_REGISTER_TYPE_UD:
 689       return d == 0;
 690    default:
 691       return false;
 692    }
 693 }
 694
 695 bool
 696 backend_reg::is_one() const
 697 {
 698    if (file != IMM)
 699       return false;
 700
 701    switch (type) {
 702    case BRW_REGISTER_TYPE_F:
 703       return f == 1.0f;
 704    case BRW_REGISTER_TYPE_DF:
 705       return df == 1.0;
 706    case BRW_REGISTER_TYPE_D:
 707    case BRW_REGISTER_TYPE_UD:
 708       return d == 1;
 709    default:
 710       return false;
 711    }
 712 }
 713
 714 bool
 715 backend_reg::is_negative_one() const
 716 {
 717    if (file != IMM)
 718       return false;
 719
 720    switch (type) {
 721    case BRW_REGISTER_TYPE_F:
 722       return f == -1.0;
 723    case BRW_REGISTER_TYPE_DF:
 724       return df == -1.0;
 725    case BRW_REGISTER_TYPE_D:
 726       return d == -1;
 727    default:
 728       return false;
 729    }
 730 }
 731
 732 bool
 733 backend_reg::is_null() const
 734 {
 735    return file == ARF && nr == BRW_ARF_NULL;
 736 }
 737
 738
 739 bool
 740 backend_reg::is_accumulator() const
 741 {
 742    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 743 }
 744
 745 bool
 746 backend_reg::in_range(const backend_reg &r, unsigned n) const
 747 {
 748    return (file == r.file &&
 749            nr == r.nr &&
 750            reg_offset >= r.reg_offset &&
 751            reg_offset < r.reg_offset + n);
 752 }
 753
 754 bool
 755 backend_instruction::is_commutative() const
 756 {
 757    switch (opcode) {
 758    case BRW_OPCODE_AND:
 759    case BRW_OPCODE_OR:
 760    case BRW_OPCODE_XOR:
 761    case BRW_OPCODE_ADD:
 762    case BRW_OPCODE_MUL:
 763    case SHADER_OPCODE_MULH:
 764       return true;
 765    case BRW_OPCODE_SEL:
 766       /* MIN and MAX are commutative. */
 767       if (conditional_mod == BRW_CONDITIONAL_GE ||
 768           conditional_mod == BRW_CONDITIONAL_L) {
 769          return true;
 770       }
 771       /* fallthrough */
 772    default:
 773       return false;
 774    }
 775 }
 776
 777 bool
 778 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
 779 {
 780    return ::is_3src(devinfo, opcode);
 781 }
 782
 783 bool
 784 backend_instruction::is_tex() const
 785 {
 786    return (opcode == SHADER_OPCODE_TEX ||
 787            opcode == FS_OPCODE_TXB ||
 788            opcode == SHADER_OPCODE_TXD ||
 789            opcode == SHADER_OPCODE_TXF ||
 790            opcode == SHADER_OPCODE_TXF_LZ ||
 791            opcode == SHADER_OPCODE_TXF_CMS ||
 792            opcode == SHADER_OPCODE_TXF_CMS_W ||
 793            opcode == SHADER_OPCODE_TXF_UMS ||
 794            opcode == SHADER_OPCODE_TXF_MCS ||
 795            opcode == SHADER_OPCODE_TXL ||
 796            opcode == SHADER_OPCODE_TXL_LZ ||
 797            opcode == SHADER_OPCODE_TXS ||
 798            opcode == SHADER_OPCODE_LOD ||
 799            opcode == SHADER_OPCODE_TG4 ||
 800            opcode == SHADER_OPCODE_TG4_OFFSET ||
 801            opcode == SHADER_OPCODE_SAMPLEINFO);
 802 }
 803
 804 bool
 805 backend_instruction::is_math() const
 806 {
 807    return (opcode == SHADER_OPCODE_RCP ||
 808            opcode == SHADER_OPCODE_RSQ ||
 809            opcode == SHADER_OPCODE_SQRT ||
 810            opcode == SHADER_OPCODE_EXP2 ||
 811            opcode == SHADER_OPCODE_LOG2 ||
 812            opcode == SHADER_OPCODE_SIN ||
 813            opcode == SHADER_OPCODE_COS ||
 814            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 815            opcode == SHADER_OPCODE_INT_REMAINDER ||
 816            opcode == SHADER_OPCODE_POW);
 817 }
 818
 819 bool
 820 backend_instruction::is_control_flow() const
 821 {
 822    switch (opcode) {
 823    case BRW_OPCODE_DO:
 824    case BRW_OPCODE_WHILE:
 825    case BRW_OPCODE_IF:
 826    case BRW_OPCODE_ELSE:
 827    case BRW_OPCODE_ENDIF:
 828    case BRW_OPCODE_BREAK:
 829    case BRW_OPCODE_CONTINUE:
 830       return true;
 831    default:
 832       return false;
 833    }
 834 }
 835
 836 bool
 837 backend_instruction::can_do_source_mods() const
 838 {
 839    switch (opcode) {
 840    case BRW_OPCODE_ADDC:
 841    case BRW_OPCODE_BFE:
 842    case BRW_OPCODE_BFI1:
 843    case BRW_OPCODE_BFI2:
 844    case BRW_OPCODE_BFREV:
 845    case BRW_OPCODE_CBIT:
 846    case BRW_OPCODE_FBH:
 847    case BRW_OPCODE_FBL:
 848    case BRW_OPCODE_SUBB:
 849       return false;
 850    default:
 851       return true;
 852    }
 853 }
 854
 855 bool
 856 backend_instruction::can_do_saturate() const
 857 {
 858    switch (opcode) {
 859    case BRW_OPCODE_ADD:
 860    case BRW_OPCODE_ASR:
 861    case BRW_OPCODE_AVG:
 862    case BRW_OPCODE_DP2:
 863    case BRW_OPCODE_DP3:
 864    case BRW_OPCODE_DP4:
 865    case BRW_OPCODE_DPH:
 866    case BRW_OPCODE_F16TO32:
 867    case BRW_OPCODE_F32TO16:
 868    case BRW_OPCODE_LINE:
 869    case BRW_OPCODE_LRP:
 870    case BRW_OPCODE_MAC:
 871    case BRW_OPCODE_MAD:
 872    case BRW_OPCODE_MATH:
 873    case BRW_OPCODE_MOV:
 874    case BRW_OPCODE_MUL:
 875    case SHADER_OPCODE_MULH:
 876    case BRW_OPCODE_PLN:
 877    case BRW_OPCODE_RNDD:
 878    case BRW_OPCODE_RNDE:
 879    case BRW_OPCODE_RNDU:
 880    case BRW_OPCODE_RNDZ:
 881    case BRW_OPCODE_SEL:
 882    case BRW_OPCODE_SHL:
 883    case BRW_OPCODE_SHR:
 884    case FS_OPCODE_LINTERP:
 885    case SHADER_OPCODE_COS:
 886    case SHADER_OPCODE_EXP2:
 887    case SHADER_OPCODE_LOG2:
 888    case SHADER_OPCODE_POW:
 889    case SHADER_OPCODE_RCP:
 890    case SHADER_OPCODE_RSQ:
 891    case SHADER_OPCODE_SIN:
 892    case SHADER_OPCODE_SQRT:
 893       return true;
 894    default:
 895       return false;
 896    }
 897 }
 898
 899 bool
 900 backend_instruction::can_do_cmod() const
 901 {
 902    switch (opcode) {
 903    case BRW_OPCODE_ADD:
 904    case BRW_OPCODE_ADDC:
 905    case BRW_OPCODE_AND:
 906    case BRW_OPCODE_ASR:
 907    case BRW_OPCODE_AVG:
 908    case BRW_OPCODE_CMP:
 909    case BRW_OPCODE_CMPN:
 910    case BRW_OPCODE_DP2:
 911    case BRW_OPCODE_DP3:
 912    case BRW_OPCODE_DP4:
 913    case BRW_OPCODE_DPH:
 914    case BRW_OPCODE_F16TO32:
 915    case BRW_OPCODE_F32TO16:
 916    case BRW_OPCODE_FRC:
 917    case BRW_OPCODE_LINE:
 918    case BRW_OPCODE_LRP:
 919    case BRW_OPCODE_LZD:
 920    case BRW_OPCODE_MAC:
 921    case BRW_OPCODE_MACH:
 922    case BRW_OPCODE_MAD:
 923    case BRW_OPCODE_MOV:
 924    case BRW_OPCODE_MUL:
 925    case BRW_OPCODE_NOT:
 926    case BRW_OPCODE_OR:
 927    case BRW_OPCODE_PLN:
 928    case BRW_OPCODE_RNDD:
 929    case BRW_OPCODE_RNDE:
 930    case BRW_OPCODE_RNDU:
 931    case BRW_OPCODE_RNDZ:
 932    case BRW_OPCODE_SAD2:
 933    case BRW_OPCODE_SADA2:
 934    case BRW_OPCODE_SHL:
 935    case BRW_OPCODE_SHR:
 936    case BRW_OPCODE_SUBB:
 937    case BRW_OPCODE_XOR:
 938    case FS_OPCODE_CINTERP:
 939    case FS_OPCODE_LINTERP:
 940       return true;
 941    default:
 942       return false;
 943    }
 944 }
 945
 946 bool
 947 backend_instruction::reads_accumulator_implicitly() const
 948 {
 949    switch (opcode) {
 950    case BRW_OPCODE_MAC:
 951    case BRW_OPCODE_MACH:
 952    case BRW_OPCODE_SADA2:
 953       return true;
 954    default:
 955       return false;
 956    }
 957 }
 958
 959 bool
 960 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 961 {
 962    return writes_accumulator ||
 963           (devinfo->gen < 6 &&
 964            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 965             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 966              opcode != FS_OPCODE_CINTERP)));
 967 }
 968
 969 bool
 970 backend_instruction::has_side_effects() const
 971 {
 972    switch (opcode) {
 973    case SHADER_OPCODE_UNTYPED_ATOMIC:
 974    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 975    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 976    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 977    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 978    case SHADER_OPCODE_TYPED_ATOMIC:
 979    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 980    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 981    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 982    case SHADER_OPCODE_MEMORY_FENCE:
 983    case SHADER_OPCODE_URB_WRITE_SIMD8:
 984    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 985    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 986    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 987    case FS_OPCODE_FB_WRITE:
 988    case SHADER_OPCODE_BARRIER:
 989    case TCS_OPCODE_URB_WRITE:
 990    case TCS_OPCODE_RELEASE_INPUT:
 991       return true;
 992    default:
 993       return false;
 994    }
 995 }
 996
 997 bool
 998 backend_instruction::is_volatile() const
 999 {
1000    switch (opcode) {
1001    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1002    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1003    case SHADER_OPCODE_TYPED_SURFACE_READ:
1004    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1005    case SHADER_OPCODE_URB_READ_SIMD8:
1006    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1007    case VEC4_OPCODE_URB_READ:
1008       return true;
1009    default:
1010       return false;
1011    }
1012 }
1013
1014 #ifndef NDEBUG
1015 static bool
1016 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1017 {
1018    bool found = false;
1019    foreach_inst_in_block (backend_instruction, i, block) {
1020       if (inst == i) {
1021          found = true;
1022       }
1023    }
1024    return found;
1025 }
1026 #endif
1027
1028 static void
1029 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1030 {
1031    for (bblock_t *block_iter = start_block->next();
1032         block_iter;
1033         block_iter = block_iter->next()) {
1034       block_iter->start_ip += ip_adjustment;
1035       block_iter->end_ip += ip_adjustment;
1036    }
1037 }
1038
1039 void
1040 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1041 {
1042    assert(this != inst);
1043
1044    if (!this->is_head_sentinel())
1045       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1046
1047    block->end_ip++;
1048
1049    adjust_later_block_ips(block, 1);
1050
1051    exec_node::insert_after(inst);
1052 }
1053
1054 void
1055 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1056 {
1057    assert(this != inst);
1058
1059    if (!this->is_tail_sentinel())
1060       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1061
1062    block->end_ip++;
1063
1064    adjust_later_block_ips(block, 1);
1065
1066    exec_node::insert_before(inst);
1067 }
1068
1069 void
1070 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1071 {
1072    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1073
1074    unsigned num_inst = list->length();
1075
1076    block->end_ip += num_inst;
1077
1078    adjust_later_block_ips(block, num_inst);
1079
1080    exec_node::insert_before(list);
1081 }
1082
1083 void
1084 backend_instruction::remove(bblock_t *block)
1085 {
1086    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1087
1088    adjust_later_block_ips(block, -1);
1089
1090    if (block->start_ip == block->end_ip) {
1091       block->cfg->remove_block(block);
1092    } else {
1093       block->end_ip--;
1094    }
1095
1096    exec_node::remove();
1097 }
1098
1099 void
1100 backend_shader::dump_instructions()
1101 {
1102    dump_instructions(NULL);
1103 }
1104
1105 void
1106 backend_shader::dump_instructions(const char *name)
1107 {
1108    FILE *file = stderr;
1109    if (name && geteuid() != 0) {
1110       file = fopen(name, "w");
1111       if (!file)
1112          file = stderr;
1113    }
1114
1115    if (cfg) {
1116       int ip = 0;
1117       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1118          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1119             fprintf(file, "%4d: ", ip++);
1120          dump_instruction(inst, file);
1121       }
1122    } else {
1123       int ip = 0;
1124       foreach_in_list(backend_instruction, inst, &instructions) {
1125          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1126             fprintf(file, "%4d: ", ip++);
1127          dump_instruction(inst, file);
1128       }
1129    }
1130
1131    if (file != stderr) {
1132       fclose(file);
1133    }
1134 }
1135
1136 void
1137 backend_shader::calculate_cfg()
1138 {
1139    if (this->cfg)
1140       return;
1141    cfg = new(mem_ctx) cfg_t(&this->instructions);
1142 }
1143
1144 /**
1145  * Sets up the starting offsets for the groups of binding table entries
1146  * commong to all pipeline stages.
1147  *
1148  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1149  * unused but also make sure that addition of small offsets to them will
1150  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1151  */
1152 void
1153 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1154                                         const struct brw_device_info *devinfo,
1155                                         const struct gl_shader_program *shader_prog,
1156                                         const struct gl_program *prog,
1157                                         struct brw_stage_prog_data *stage_prog_data,
1158                                         uint32_t next_binding_table_offset)
1159 {
1160    const struct gl_shader *shader = NULL;
1161    int num_textures = _mesa_fls(prog->SamplersUsed);
1162
1163    if (shader_prog)
1164       shader = shader_prog->_LinkedShaders[stage];
1165
1166    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1167    next_binding_table_offset += num_textures;
1168
1169    if (shader) {
1170       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1171       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1172       next_binding_table_offset += shader->NumUniformBlocks;
1173
1174       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1175       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1176       next_binding_table_offset += shader->NumShaderStorageBlocks;
1177    } else {
1178       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1179       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1180    }
1181
1182    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1183       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1184       next_binding_table_offset++;
1185    } else {
1186       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1187    }
1188
1189    if (prog->UsesGather) {
1190       if (devinfo->gen >= 8) {
1191          stage_prog_data->binding_table.gather_texture_start =
1192             stage_prog_data->binding_table.texture_start;
1193       } else {
1194          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1195          next_binding_table_offset += num_textures;
1196       }
1197    } else {
1198       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1199    }
1200
1201    if (shader && shader->NumAtomicBuffers) {
1202       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1203       next_binding_table_offset += shader->NumAtomicBuffers;
1204    } else {
1205       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1206    }
1207
1208    if (shader && shader->NumImages) {
1209       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1210       next_binding_table_offset += shader->NumImages;
1211    } else {
1212       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1213    }
1214
1215    /* This may or may not be used depending on how the compile goes. */
1216    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1217    next_binding_table_offset++;
1218
1219    /* Plane 0 is just the regular texture section */
1220    stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
1221
1222    stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
1223    next_binding_table_offset += num_textures;
1224
1225    stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
1226    next_binding_table_offset += num_textures;
1227
1228    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1229
1230    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1231 }
1232
1233 static void
1234 setup_vec4_uniform_value(const gl_constant_value **params,
1235                          const gl_constant_value *values,
1236                          unsigned n)
1237 {
1238    static const gl_constant_value zero = { 0 };
1239
1240    for (unsigned i = 0; i < n; ++i)
1241       params[i] = &values[i];
1242
1243    for (unsigned i = n; i < 4; ++i)
1244       params[i] = &zero;
1245 }
1246
1247 void
1248 brw_setup_image_uniform_values(gl_shader_stage stage,
1249                                struct brw_stage_prog_data *stage_prog_data,
1250                                unsigned param_start_index,
1251                                const gl_uniform_storage *storage)
1252 {
1253    const gl_constant_value **param =
1254       &stage_prog_data->param[param_start_index];
1255
1256    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1257       const unsigned image_idx = storage->opaque[stage].index + i;
1258       const brw_image_param *image_param =
1259          &stage_prog_data->image_param[image_idx];
1260
1261       /* Upload the brw_image_param structure.  The order is expected to match
1262        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1263        */
1264       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1265          (const gl_constant_value *)&image_param->surface_idx, 1);
1266       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1267          (const gl_constant_value *)image_param->offset, 2);
1268       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1269          (const gl_constant_value *)image_param->size, 3);
1270       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1271          (const gl_constant_value *)image_param->stride, 4);
1272       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1273          (const gl_constant_value *)image_param->tiling, 3);
1274       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1275          (const gl_constant_value *)image_param->swizzling, 2);
1276       param += BRW_IMAGE_PARAM_SIZE;
1277
1278       brw_mark_surface_used(
1279          stage_prog_data,
1280          stage_prog_data->binding_table.image_start + image_idx);
1281    }
1282 }
1283
1284 /**
1285  * Decide which set of clip planes should be used when clipping via
1286  * gl_Position or gl_ClipVertex.
1287  */
1288 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1289 {
1290    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1291       /* There is currently a GLSL vertex shader, so clip according to GLSL
1292        * rules, which means compare gl_ClipVertex (or gl_Position, if
1293        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1294        * that were stored in EyeUserPlane at the time the clip planes were
1295        * specified.
1296        */
1297       return ctx->Transform.EyeUserPlane;
1298    } else {
1299       /* Either we are using fixed function or an ARB vertex program.  In
1300        * either case the clip planes are going to be compared against
1301        * gl_Position (which is in clip coordinates) so we have to clip using
1302        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1303        * core.
1304        */
1305       return ctx->Transform._ClipUserPlane;
1306    }
1307 }
1308
1309 extern "C" const unsigned *
1310 brw_compile_tes(const struct brw_compiler *compiler,
1311                 void *log_data,
1312                 void *mem_ctx,
1313                 const struct brw_tes_prog_key *key,
1314                 struct brw_tes_prog_data *prog_data,
1315                 const nir_shader *src_shader,
1316                 struct gl_shader_program *shader_prog,
1317                 int shader_time_index,
1318                 unsigned *final_assembly_size,
1319                 char **error_str)
1320 {
1321    const struct brw_device_info *devinfo = compiler->devinfo;
1322    struct gl_shader *shader =
1323       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1324    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1325
1326    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1327    nir->info.inputs_read = key->inputs_read;
1328    nir->info.patch_inputs_read = key->patch_inputs_read;
1329
1330    struct brw_vue_map input_vue_map;
1331    brw_compute_tess_vue_map(&input_vue_map,
1332                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1333                             nir->info.patch_inputs_read);
1334
1335    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1336    brw_nir_lower_tes_inputs(nir, &input_vue_map);
1337    brw_nir_lower_vue_outputs(nir, is_scalar);
1338    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1339
1340    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1341                        nir->info.outputs_written,
1342                        nir->info.separate_shader);
1343
1344    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1345
1346    assert(output_size_bytes >= 1);
1347    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1348       if (error_str)
1349          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1350       return NULL;
1351    }
1352
1353    /* URB entry sizes are stored as a multiple of 64 bytes. */
1354    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1355
1356    bool need_patch_header = nir->info.system_values_read &
1357       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1358        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1359
1360    /* The TES will pull most inputs using URB read messages.
1361     *
1362     * However, we push the patch header for TessLevel factors when required,
1363     * as it's a tiny amount of extra data.
1364     */
1365    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1366
1367    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1368       fprintf(stderr, "TES Input ");
1369       brw_print_vue_map(stderr, &input_vue_map);
1370       fprintf(stderr, "TES Output ");
1371       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1372    }
1373
1374    if (is_scalar) {
1375       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1376                    &prog_data->base.base, shader->Program, nir, 8,
1377                    shader_time_index, &input_vue_map);
1378       if (!v.run_tes()) {
1379          if (error_str)
1380             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1381          return NULL;
1382       }
1383
1384       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1385       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1386
1387       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1388                      &prog_data->base.base, v.promoted_constants, false,
1389                      MESA_SHADER_TESS_EVAL);
1390       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1391          g.enable_debug(ralloc_asprintf(mem_ctx,
1392                                         "%s tessellation evaluation shader %s",
1393                                         nir->info.label ? nir->info.label
1394                                                         : "unnamed",
1395                                         nir->info.name));
1396       }
1397
1398       g.generate_code(v.cfg, 8);
1399
1400       return g.get_assembly(final_assembly_size);
1401    } else {
1402       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1403                               nir, mem_ctx, shader_time_index);
1404       if (!v.run()) {
1405          if (error_str)
1406             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1407          return NULL;
1408       }
1409
1410       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1411          v.dump_instructions();
1412
1413       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1414                                         &prog_data->base, v.cfg,
1415                                         final_assembly_size);
1416    }
1417 }