2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/macros.h"
25 #include "brw_context.h"
31 #include "glsl/ir_optimization.h"
32 #include "glsl/glsl_parser_extras.h"
33 #include "main/shaderapi.h"
34 #include "util/debug.h"
37 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
39 struct brw_context
*brw
= (struct brw_context
*)data
;
44 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
45 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
46 MESA_DEBUG_TYPE_OTHER
,
47 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
52 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
54 struct brw_context
*brw
= (struct brw_context
*)data
;
59 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
61 va_copy(args_copy
, args
);
62 vfprintf(stderr
, fmt
, args_copy
);
66 if (brw
->perf_debug
) {
68 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
69 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
70 MESA_DEBUG_TYPE_PERFORMANCE
,
71 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
77 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
79 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
81 compiler
->devinfo
= devinfo
;
82 compiler
->shader_debug_log
= shader_debug_log_mesa
;
83 compiler
->shader_perf_log
= shader_perf_log_mesa
;
85 brw_fs_alloc_reg_sets(compiler
);
86 brw_vec4_alloc_reg_set(compiler
);
88 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
89 devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
);
90 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
91 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
92 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
93 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
95 nir_shader_compiler_options
*nir_options
=
96 rzalloc(compiler
, nir_shader_compiler_options
);
97 nir_options
->native_integers
= true;
98 /* In order to help allow for better CSE at the NIR level we tell NIR
99 * to split all ffma instructions during opt_algebraic and we then
100 * re-combine them as a later step.
102 nir_options
->lower_ffma
= true;
103 nir_options
->lower_sub
= true;
104 /* In the vec4 backend, our dpN instruction replicates its result to all
105 * the components of a vec4. We would like NIR to give us replicated fdot
106 * instructions because it can optimize better for us.
108 * For the FS backend, it should be lowered away by the scalarizing pass so
109 * we should never see fdot anyway.
111 nir_options
->fdot_replicates
= true;
113 /* We want the GLSL compiler to emit code that uses condition codes */
114 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
115 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
116 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
117 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
119 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
120 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
121 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
122 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
123 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
124 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
126 bool is_scalar
= compiler
->scalar_stage
[i
];
128 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
129 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
130 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
132 /* !ARB_gpu_shader5 */
133 if (devinfo
->gen
< 7)
134 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
136 compiler
->glsl_compiler_options
[i
].NirOptions
= nir_options
;
138 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
141 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
142 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;
147 extern "C" struct gl_shader
*
148 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
150 struct brw_shader
*shader
;
152 shader
= rzalloc(NULL
, struct brw_shader
);
154 shader
->base
.Type
= type
;
155 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
156 shader
->base
.Name
= name
;
157 _mesa_init_shader(ctx
, &shader
->base
);
160 return &shader
->base
;
164 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
167 assert(surf_index
< BRW_MAX_SURFACES
);
169 prog_data
->binding_table
.size_bytes
=
170 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
174 brw_type_for_base_type(const struct glsl_type
*type
)
176 switch (type
->base_type
) {
177 case GLSL_TYPE_FLOAT
:
178 return BRW_REGISTER_TYPE_F
;
181 case GLSL_TYPE_SUBROUTINE
:
182 return BRW_REGISTER_TYPE_D
;
184 return BRW_REGISTER_TYPE_UD
;
185 case GLSL_TYPE_ARRAY
:
186 return brw_type_for_base_type(type
->fields
.array
);
187 case GLSL_TYPE_STRUCT
:
188 case GLSL_TYPE_SAMPLER
:
189 case GLSL_TYPE_ATOMIC_UINT
:
190 /* These should be overridden with the type of the member when
191 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
192 * way to trip up if we don't.
194 return BRW_REGISTER_TYPE_UD
;
195 case GLSL_TYPE_IMAGE
:
196 return BRW_REGISTER_TYPE_UD
;
198 case GLSL_TYPE_ERROR
:
199 case GLSL_TYPE_INTERFACE
:
200 case GLSL_TYPE_DOUBLE
:
201 unreachable("not reached");
204 return BRW_REGISTER_TYPE_F
;
207 enum brw_conditional_mod
208 brw_conditional_for_comparison(unsigned int op
)
212 return BRW_CONDITIONAL_L
;
213 case ir_binop_greater
:
214 return BRW_CONDITIONAL_G
;
215 case ir_binop_lequal
:
216 return BRW_CONDITIONAL_LE
;
217 case ir_binop_gequal
:
218 return BRW_CONDITIONAL_GE
;
220 case ir_binop_all_equal
: /* same as equal for scalars */
221 return BRW_CONDITIONAL_Z
;
222 case ir_binop_nequal
:
223 case ir_binop_any_nequal
: /* same as nequal for scalars */
224 return BRW_CONDITIONAL_NZ
;
226 unreachable("not reached: bad operation for comparison");
231 brw_math_function(enum opcode op
)
234 case SHADER_OPCODE_RCP
:
235 return BRW_MATH_FUNCTION_INV
;
236 case SHADER_OPCODE_RSQ
:
237 return BRW_MATH_FUNCTION_RSQ
;
238 case SHADER_OPCODE_SQRT
:
239 return BRW_MATH_FUNCTION_SQRT
;
240 case SHADER_OPCODE_EXP2
:
241 return BRW_MATH_FUNCTION_EXP
;
242 case SHADER_OPCODE_LOG2
:
243 return BRW_MATH_FUNCTION_LOG
;
244 case SHADER_OPCODE_POW
:
245 return BRW_MATH_FUNCTION_POW
;
246 case SHADER_OPCODE_SIN
:
247 return BRW_MATH_FUNCTION_SIN
;
248 case SHADER_OPCODE_COS
:
249 return BRW_MATH_FUNCTION_COS
;
250 case SHADER_OPCODE_INT_QUOTIENT
:
251 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
252 case SHADER_OPCODE_INT_REMAINDER
:
253 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
255 unreachable("not reached: unknown math function");
260 brw_texture_offset(int *offsets
, unsigned num_components
)
262 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
264 /* Combine all three offsets into a single unsigned dword:
266 * bits 11:8 - U Offset (X component)
267 * bits 7:4 - V Offset (Y component)
268 * bits 3:0 - R Offset (Z component)
270 unsigned offset_bits
= 0;
271 for (unsigned i
= 0; i
< num_components
; i
++) {
272 const unsigned shift
= 4 * (2 - i
);
273 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
279 brw_instruction_name(enum opcode op
)
282 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
283 assert(opcode_descs
[op
].name
);
284 return opcode_descs
[op
].name
;
285 case FS_OPCODE_FB_WRITE
:
287 case FS_OPCODE_FB_WRITE_LOGICAL
:
288 return "fb_write_logical";
289 case FS_OPCODE_PACK_STENCIL_REF
:
290 return "pack_stencil_ref";
291 case FS_OPCODE_BLORP_FB_WRITE
:
292 return "blorp_fb_write";
293 case FS_OPCODE_REP_FB_WRITE
:
294 return "rep_fb_write";
296 case SHADER_OPCODE_RCP
:
298 case SHADER_OPCODE_RSQ
:
300 case SHADER_OPCODE_SQRT
:
302 case SHADER_OPCODE_EXP2
:
304 case SHADER_OPCODE_LOG2
:
306 case SHADER_OPCODE_POW
:
308 case SHADER_OPCODE_INT_QUOTIENT
:
310 case SHADER_OPCODE_INT_REMAINDER
:
312 case SHADER_OPCODE_SIN
:
314 case SHADER_OPCODE_COS
:
317 case SHADER_OPCODE_TEX
:
319 case SHADER_OPCODE_TEX_LOGICAL
:
320 return "tex_logical";
321 case SHADER_OPCODE_TXD
:
323 case SHADER_OPCODE_TXD_LOGICAL
:
324 return "txd_logical";
325 case SHADER_OPCODE_TXF
:
327 case SHADER_OPCODE_TXF_LOGICAL
:
328 return "txf_logical";
329 case SHADER_OPCODE_TXL
:
331 case SHADER_OPCODE_TXL_LOGICAL
:
332 return "txl_logical";
333 case SHADER_OPCODE_TXS
:
335 case SHADER_OPCODE_TXS_LOGICAL
:
336 return "txs_logical";
339 case FS_OPCODE_TXB_LOGICAL
:
340 return "txb_logical";
341 case SHADER_OPCODE_TXF_CMS
:
343 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
344 return "txf_cms_logical";
345 case SHADER_OPCODE_TXF_CMS_W
:
347 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
348 return "txf_cms_w_logical";
349 case SHADER_OPCODE_TXF_UMS
:
351 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
352 return "txf_ums_logical";
353 case SHADER_OPCODE_TXF_MCS
:
355 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
356 return "txf_mcs_logical";
357 case SHADER_OPCODE_LOD
:
359 case SHADER_OPCODE_LOD_LOGICAL
:
360 return "lod_logical";
361 case SHADER_OPCODE_TG4
:
363 case SHADER_OPCODE_TG4_LOGICAL
:
364 return "tg4_logical";
365 case SHADER_OPCODE_TG4_OFFSET
:
367 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
368 return "tg4_offset_logical";
369 case SHADER_OPCODE_SAMPLEINFO
:
372 case SHADER_OPCODE_SHADER_TIME_ADD
:
373 return "shader_time_add";
375 case SHADER_OPCODE_UNTYPED_ATOMIC
:
376 return "untyped_atomic";
377 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
378 return "untyped_atomic_logical";
379 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
380 return "untyped_surface_read";
381 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
382 return "untyped_surface_read_logical";
383 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
384 return "untyped_surface_write";
385 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
386 return "untyped_surface_write_logical";
387 case SHADER_OPCODE_TYPED_ATOMIC
:
388 return "typed_atomic";
389 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
390 return "typed_atomic_logical";
391 case SHADER_OPCODE_TYPED_SURFACE_READ
:
392 return "typed_surface_read";
393 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
394 return "typed_surface_read_logical";
395 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
396 return "typed_surface_write";
397 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
398 return "typed_surface_write_logical";
399 case SHADER_OPCODE_MEMORY_FENCE
:
400 return "memory_fence";
402 case SHADER_OPCODE_LOAD_PAYLOAD
:
403 return "load_payload";
405 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
406 return "gen4_scratch_read";
407 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
408 return "gen4_scratch_write";
409 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
410 return "gen7_scratch_read";
411 case SHADER_OPCODE_URB_WRITE_SIMD8
:
412 return "gen8_urb_write_simd8";
413 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
414 return "gen8_urb_write_simd8_per_slot";
415 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
416 return "gen8_urb_write_simd8_masked";
417 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
418 return "gen8_urb_write_simd8_masked_per_slot";
419 case SHADER_OPCODE_URB_READ_SIMD8
:
420 return "urb_read_simd8";
421 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
422 return "urb_read_simd8_per_slot";
424 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
425 return "find_live_channel";
426 case SHADER_OPCODE_BROADCAST
:
429 case VEC4_OPCODE_MOV_BYTES
:
431 case VEC4_OPCODE_PACK_BYTES
:
433 case VEC4_OPCODE_UNPACK_UNIFORM
:
434 return "unpack_uniform";
436 case FS_OPCODE_DDX_COARSE
:
438 case FS_OPCODE_DDX_FINE
:
440 case FS_OPCODE_DDY_COARSE
:
442 case FS_OPCODE_DDY_FINE
:
445 case FS_OPCODE_CINTERP
:
447 case FS_OPCODE_LINTERP
:
450 case FS_OPCODE_PIXEL_X
:
452 case FS_OPCODE_PIXEL_Y
:
455 case FS_OPCODE_GET_BUFFER_SIZE
:
456 return "fs_get_buffer_size";
458 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
459 return "uniform_pull_const";
460 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
461 return "uniform_pull_const_gen7";
462 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
463 return "varying_pull_const";
464 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
465 return "varying_pull_const_gen7";
467 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
468 return "mov_dispatch_to_flags";
469 case FS_OPCODE_DISCARD_JUMP
:
470 return "discard_jump";
472 case FS_OPCODE_SET_SAMPLE_ID
:
473 return "set_sample_id";
474 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
475 return "set_simd4x2_offset";
477 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
478 return "pack_half_2x16_split";
479 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
480 return "unpack_half_2x16_split_x";
481 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
482 return "unpack_half_2x16_split_y";
484 case FS_OPCODE_PLACEHOLDER_HALT
:
485 return "placeholder_halt";
487 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
488 return "interp_centroid";
489 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
490 return "interp_sample";
491 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
492 return "interp_shared_offset";
493 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
494 return "interp_per_slot_offset";
496 case VS_OPCODE_URB_WRITE
:
497 return "vs_urb_write";
498 case VS_OPCODE_PULL_CONSTANT_LOAD
:
499 return "pull_constant_load";
500 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
501 return "pull_constant_load_gen7";
503 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
504 return "set_simd4x2_header_gen9";
506 case VS_OPCODE_GET_BUFFER_SIZE
:
507 return "vs_get_buffer_size";
509 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
510 return "unpack_flags_simd4x2";
512 case GS_OPCODE_URB_WRITE
:
513 return "gs_urb_write";
514 case GS_OPCODE_URB_WRITE_ALLOCATE
:
515 return "gs_urb_write_allocate";
516 case GS_OPCODE_THREAD_END
:
517 return "gs_thread_end";
518 case GS_OPCODE_SET_WRITE_OFFSET
:
519 return "set_write_offset";
520 case GS_OPCODE_SET_VERTEX_COUNT
:
521 return "set_vertex_count";
522 case GS_OPCODE_SET_DWORD_2
:
523 return "set_dword_2";
524 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
525 return "prepare_channel_masks";
526 case GS_OPCODE_SET_CHANNEL_MASKS
:
527 return "set_channel_masks";
528 case GS_OPCODE_GET_INSTANCE_ID
:
529 return "get_instance_id";
530 case GS_OPCODE_FF_SYNC
:
532 case GS_OPCODE_SET_PRIMITIVE_ID
:
533 return "set_primitive_id";
534 case GS_OPCODE_SVB_WRITE
:
535 return "gs_svb_write";
536 case GS_OPCODE_SVB_SET_DST_INDEX
:
537 return "gs_svb_set_dst_index";
538 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
539 return "gs_ff_sync_set_primitives";
540 case CS_OPCODE_CS_TERMINATE
:
541 return "cs_terminate";
542 case SHADER_OPCODE_BARRIER
:
544 case SHADER_OPCODE_MULH
:
546 case SHADER_OPCODE_MOV_INDIRECT
:
547 return "mov_indirect";
550 unreachable("not reached");
554 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
560 } imm
= { reg
->ud
}, sat_imm
= { 0 };
563 case BRW_REGISTER_TYPE_UD
:
564 case BRW_REGISTER_TYPE_D
:
565 case BRW_REGISTER_TYPE_UW
:
566 case BRW_REGISTER_TYPE_W
:
567 case BRW_REGISTER_TYPE_UQ
:
568 case BRW_REGISTER_TYPE_Q
:
571 case BRW_REGISTER_TYPE_F
:
572 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
574 case BRW_REGISTER_TYPE_UB
:
575 case BRW_REGISTER_TYPE_B
:
576 unreachable("no UB/B immediates");
577 case BRW_REGISTER_TYPE_V
:
578 case BRW_REGISTER_TYPE_UV
:
579 case BRW_REGISTER_TYPE_VF
:
580 unreachable("unimplemented: saturate vector immediate");
581 case BRW_REGISTER_TYPE_DF
:
582 case BRW_REGISTER_TYPE_HF
:
583 unreachable("unimplemented: saturate DF/HF immediate");
586 if (imm
.ud
!= sat_imm
.ud
) {
587 reg
->ud
= sat_imm
.ud
;
594 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
597 case BRW_REGISTER_TYPE_D
:
598 case BRW_REGISTER_TYPE_UD
:
601 case BRW_REGISTER_TYPE_W
:
602 case BRW_REGISTER_TYPE_UW
:
603 reg
->d
= -(int16_t)reg
->ud
;
605 case BRW_REGISTER_TYPE_F
:
608 case BRW_REGISTER_TYPE_VF
:
609 reg
->ud
^= 0x80808080;
611 case BRW_REGISTER_TYPE_UB
:
612 case BRW_REGISTER_TYPE_B
:
613 unreachable("no UB/B immediates");
614 case BRW_REGISTER_TYPE_UV
:
615 case BRW_REGISTER_TYPE_V
:
616 assert(!"unimplemented: negate UV/V immediate");
617 case BRW_REGISTER_TYPE_UQ
:
618 case BRW_REGISTER_TYPE_Q
:
619 assert(!"unimplemented: negate UQ/Q immediate");
620 case BRW_REGISTER_TYPE_DF
:
621 case BRW_REGISTER_TYPE_HF
:
622 assert(!"unimplemented: negate DF/HF immediate");
629 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
632 case BRW_REGISTER_TYPE_D
:
633 reg
->d
= abs(reg
->d
);
635 case BRW_REGISTER_TYPE_W
:
636 reg
->d
= abs((int16_t)reg
->ud
);
638 case BRW_REGISTER_TYPE_F
:
639 reg
->f
= fabsf(reg
->f
);
641 case BRW_REGISTER_TYPE_VF
:
642 reg
->ud
&= ~0x80808080;
644 case BRW_REGISTER_TYPE_UB
:
645 case BRW_REGISTER_TYPE_B
:
646 unreachable("no UB/B immediates");
647 case BRW_REGISTER_TYPE_UQ
:
648 case BRW_REGISTER_TYPE_UD
:
649 case BRW_REGISTER_TYPE_UW
:
650 case BRW_REGISTER_TYPE_UV
:
651 /* Presumably the absolute value modifier on an unsigned source is a
652 * nop, but it would be nice to confirm.
654 assert(!"unimplemented: abs unsigned immediate");
655 case BRW_REGISTER_TYPE_V
:
656 assert(!"unimplemented: abs V immediate");
657 case BRW_REGISTER_TYPE_Q
:
658 assert(!"unimplemented: abs Q immediate");
659 case BRW_REGISTER_TYPE_DF
:
660 case BRW_REGISTER_TYPE_HF
:
661 assert(!"unimplemented: abs DF/HF immediate");
667 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
670 const nir_shader
*shader
,
671 struct brw_stage_prog_data
*stage_prog_data
)
672 : compiler(compiler
),
674 devinfo(compiler
->devinfo
),
676 stage_prog_data(stage_prog_data
),
681 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
682 stage_name
= _mesa_shader_stage_to_string(stage
);
683 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
687 backend_reg::equals(const backend_reg
&r
) const
689 return memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
690 reg_offset
== r
.reg_offset
;
694 backend_reg::is_zero() const
703 backend_reg::is_one() const
708 return type
== BRW_REGISTER_TYPE_F
714 backend_reg::is_negative_one() const
720 case BRW_REGISTER_TYPE_F
:
722 case BRW_REGISTER_TYPE_D
:
730 backend_reg::is_null() const
732 return file
== ARF
&& nr
== BRW_ARF_NULL
;
737 backend_reg::is_accumulator() const
739 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
743 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
745 return (file
== r
.file
&&
747 reg_offset
>= r
.reg_offset
&&
748 reg_offset
< r
.reg_offset
+ n
);
752 backend_instruction::is_commutative() const
760 case SHADER_OPCODE_MULH
:
763 /* MIN and MAX are commutative. */
764 if (conditional_mod
== BRW_CONDITIONAL_GE
||
765 conditional_mod
== BRW_CONDITIONAL_L
) {
775 backend_instruction::is_3src() const
777 return ::is_3src(opcode
);
781 backend_instruction::is_tex() const
783 return (opcode
== SHADER_OPCODE_TEX
||
784 opcode
== FS_OPCODE_TXB
||
785 opcode
== SHADER_OPCODE_TXD
||
786 opcode
== SHADER_OPCODE_TXF
||
787 opcode
== SHADER_OPCODE_TXF_CMS
||
788 opcode
== SHADER_OPCODE_TXF_CMS_W
||
789 opcode
== SHADER_OPCODE_TXF_UMS
||
790 opcode
== SHADER_OPCODE_TXF_MCS
||
791 opcode
== SHADER_OPCODE_TXL
||
792 opcode
== SHADER_OPCODE_TXS
||
793 opcode
== SHADER_OPCODE_LOD
||
794 opcode
== SHADER_OPCODE_TG4
||
795 opcode
== SHADER_OPCODE_TG4_OFFSET
);
799 backend_instruction::is_math() const
801 return (opcode
== SHADER_OPCODE_RCP
||
802 opcode
== SHADER_OPCODE_RSQ
||
803 opcode
== SHADER_OPCODE_SQRT
||
804 opcode
== SHADER_OPCODE_EXP2
||
805 opcode
== SHADER_OPCODE_LOG2
||
806 opcode
== SHADER_OPCODE_SIN
||
807 opcode
== SHADER_OPCODE_COS
||
808 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
809 opcode
== SHADER_OPCODE_INT_REMAINDER
||
810 opcode
== SHADER_OPCODE_POW
);
814 backend_instruction::is_control_flow() const
818 case BRW_OPCODE_WHILE
:
820 case BRW_OPCODE_ELSE
:
821 case BRW_OPCODE_ENDIF
:
822 case BRW_OPCODE_BREAK
:
823 case BRW_OPCODE_CONTINUE
:
831 backend_instruction::can_do_source_mods() const
834 case BRW_OPCODE_ADDC
:
836 case BRW_OPCODE_BFI1
:
837 case BRW_OPCODE_BFI2
:
838 case BRW_OPCODE_BFREV
:
839 case BRW_OPCODE_CBIT
:
842 case BRW_OPCODE_SUBB
:
850 backend_instruction::can_do_saturate() const
860 case BRW_OPCODE_F16TO32
:
861 case BRW_OPCODE_F32TO16
:
862 case BRW_OPCODE_LINE
:
866 case BRW_OPCODE_MATH
:
869 case SHADER_OPCODE_MULH
:
871 case BRW_OPCODE_RNDD
:
872 case BRW_OPCODE_RNDE
:
873 case BRW_OPCODE_RNDU
:
874 case BRW_OPCODE_RNDZ
:
878 case FS_OPCODE_LINTERP
:
879 case SHADER_OPCODE_COS
:
880 case SHADER_OPCODE_EXP2
:
881 case SHADER_OPCODE_LOG2
:
882 case SHADER_OPCODE_POW
:
883 case SHADER_OPCODE_RCP
:
884 case SHADER_OPCODE_RSQ
:
885 case SHADER_OPCODE_SIN
:
886 case SHADER_OPCODE_SQRT
:
894 backend_instruction::can_do_cmod() const
898 case BRW_OPCODE_ADDC
:
903 case BRW_OPCODE_CMPN
:
908 case BRW_OPCODE_F16TO32
:
909 case BRW_OPCODE_F32TO16
:
911 case BRW_OPCODE_LINE
:
915 case BRW_OPCODE_MACH
:
922 case BRW_OPCODE_RNDD
:
923 case BRW_OPCODE_RNDE
:
924 case BRW_OPCODE_RNDU
:
925 case BRW_OPCODE_RNDZ
:
926 case BRW_OPCODE_SAD2
:
927 case BRW_OPCODE_SADA2
:
930 case BRW_OPCODE_SUBB
:
932 case FS_OPCODE_CINTERP
:
933 case FS_OPCODE_LINTERP
:
941 backend_instruction::reads_accumulator_implicitly() const
945 case BRW_OPCODE_MACH
:
946 case BRW_OPCODE_SADA2
:
954 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
956 return writes_accumulator
||
958 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
959 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
960 opcode
!= FS_OPCODE_CINTERP
)));
964 backend_instruction::has_side_effects() const
967 case SHADER_OPCODE_UNTYPED_ATOMIC
:
968 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
969 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
970 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
971 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
972 case SHADER_OPCODE_TYPED_ATOMIC
:
973 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
974 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
975 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
976 case SHADER_OPCODE_MEMORY_FENCE
:
977 case SHADER_OPCODE_URB_WRITE_SIMD8
:
978 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
979 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
980 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
981 case FS_OPCODE_FB_WRITE
:
982 case SHADER_OPCODE_BARRIER
:
990 backend_instruction::is_volatile() const
993 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
994 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
995 case SHADER_OPCODE_TYPED_SURFACE_READ
:
996 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1005 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1008 foreach_inst_in_block (backend_instruction
, i
, block
) {
1018 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1020 for (bblock_t
*block_iter
= start_block
->next();
1021 !block_iter
->link
.is_tail_sentinel();
1022 block_iter
= block_iter
->next()) {
1023 block_iter
->start_ip
+= ip_adjustment
;
1024 block_iter
->end_ip
+= ip_adjustment
;
1029 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1031 if (!this->is_head_sentinel())
1032 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1036 adjust_later_block_ips(block
, 1);
1038 exec_node::insert_after(inst
);
1042 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1044 if (!this->is_tail_sentinel())
1045 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1049 adjust_later_block_ips(block
, 1);
1051 exec_node::insert_before(inst
);
1055 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1057 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1059 unsigned num_inst
= list
->length();
1061 block
->end_ip
+= num_inst
;
1063 adjust_later_block_ips(block
, num_inst
);
1065 exec_node::insert_before(list
);
1069 backend_instruction::remove(bblock_t
*block
)
1071 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1073 adjust_later_block_ips(block
, -1);
1075 if (block
->start_ip
== block
->end_ip
) {
1076 block
->cfg
->remove_block(block
);
1081 exec_node::remove();
1085 backend_shader::dump_instructions()
1087 dump_instructions(NULL
);
1091 backend_shader::dump_instructions(const char *name
)
1093 FILE *file
= stderr
;
1094 if (name
&& geteuid() != 0) {
1095 file
= fopen(name
, "w");
1102 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1103 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1104 fprintf(file
, "%4d: ", ip
++);
1105 dump_instruction(inst
, file
);
1109 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1110 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1111 fprintf(file
, "%4d: ", ip
++);
1112 dump_instruction(inst
, file
);
1116 if (file
!= stderr
) {
1122 backend_shader::calculate_cfg()
1126 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1130 backend_shader::invalidate_cfg()
1132 ralloc_free(this->cfg
);
1137 * Sets up the starting offsets for the groups of binding table entries
1138 * commong to all pipeline stages.
1140 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1141 * unused but also make sure that addition of small offsets to them will
1142 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1145 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1146 const struct brw_device_info
*devinfo
,
1147 const struct gl_shader_program
*shader_prog
,
1148 const struct gl_program
*prog
,
1149 struct brw_stage_prog_data
*stage_prog_data
,
1150 uint32_t next_binding_table_offset
)
1152 const struct gl_shader
*shader
= NULL
;
1153 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1156 shader
= shader_prog
->_LinkedShaders
[stage
];
1158 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1159 next_binding_table_offset
+= num_textures
;
1162 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1163 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1164 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1166 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1167 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1168 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1170 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1171 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1174 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1175 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1176 next_binding_table_offset
++;
1178 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1181 if (prog
->UsesGather
) {
1182 if (devinfo
->gen
>= 8) {
1183 stage_prog_data
->binding_table
.gather_texture_start
=
1184 stage_prog_data
->binding_table
.texture_start
;
1186 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1187 next_binding_table_offset
+= num_textures
;
1190 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1193 if (shader
&& shader
->NumAtomicBuffers
) {
1194 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1195 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1197 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1200 if (shader
&& shader
->NumImages
) {
1201 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1202 next_binding_table_offset
+= shader
->NumImages
;
1204 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1207 /* This may or may not be used depending on how the compile goes. */
1208 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1209 next_binding_table_offset
++;
1211 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1213 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1217 setup_vec4_uniform_value(const gl_constant_value
**params
,
1218 const gl_constant_value
*values
,
1221 static const gl_constant_value zero
= { 0 };
1223 for (unsigned i
= 0; i
< n
; ++i
)
1224 params
[i
] = &values
[i
];
1226 for (unsigned i
= n
; i
< 4; ++i
)
1231 brw_setup_image_uniform_values(gl_shader_stage stage
,
1232 struct brw_stage_prog_data
*stage_prog_data
,
1233 unsigned param_start_index
,
1234 const gl_uniform_storage
*storage
)
1236 const gl_constant_value
**param
=
1237 &stage_prog_data
->param
[param_start_index
];
1239 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1240 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1241 const brw_image_param
*image_param
=
1242 &stage_prog_data
->image_param
[image_idx
];
1244 /* Upload the brw_image_param structure. The order is expected to match
1245 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1247 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1248 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1249 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1250 (const gl_constant_value
*)image_param
->offset
, 2);
1251 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1252 (const gl_constant_value
*)image_param
->size
, 3);
1253 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1254 (const gl_constant_value
*)image_param
->stride
, 4);
1255 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1256 (const gl_constant_value
*)image_param
->tiling
, 3);
1257 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1258 (const gl_constant_value
*)image_param
->swizzling
, 2);
1259 param
+= BRW_IMAGE_PARAM_SIZE
;
1261 brw_mark_surface_used(
1263 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1268 * Decide which set of clip planes should be used when clipping via
1269 * gl_Position or gl_ClipVertex.
1271 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1273 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1274 /* There is currently a GLSL vertex shader, so clip according to GLSL
1275 * rules, which means compare gl_ClipVertex (or gl_Position, if
1276 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1277 * that were stored in EyeUserPlane at the time the clip planes were
1280 return ctx
->Transform
.EyeUserPlane
;
1282 /* Either we are using fixed function or an ARB vertex program. In
1283 * either case the clip planes are going to be compared against
1284 * gl_Position (which is in clip coordinates) so we have to clip using
1285 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1288 return ctx
->Transform
._ClipUserPlane
;