2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
29 #include "glsl/glsl_parser_extras.h"
30 #include "main/shaderobj.h"
31 #include "main/uniforms.h"
32 #include "util/debug.h"
35 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
37 struct brw_context
*brw
= (struct brw_context
*)data
;
42 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
43 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
44 MESA_DEBUG_TYPE_OTHER
,
45 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
50 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
52 struct brw_context
*brw
= (struct brw_context
*)data
;
57 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
59 va_copy(args_copy
, args
);
60 vfprintf(stderr
, fmt
, args_copy
);
64 if (brw
->perf_debug
) {
66 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
67 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
68 MESA_DEBUG_TYPE_PERFORMANCE
,
69 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
75 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
77 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
79 compiler
->devinfo
= devinfo
;
80 compiler
->shader_debug_log
= shader_debug_log_mesa
;
81 compiler
->shader_perf_log
= shader_perf_log_mesa
;
83 brw_fs_alloc_reg_sets(compiler
);
84 brw_vec4_alloc_reg_set(compiler
);
86 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
87 devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
);
88 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
] = false;
89 compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
] = true;
90 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
91 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
92 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
93 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
95 nir_shader_compiler_options
*nir_options
=
96 rzalloc(compiler
, nir_shader_compiler_options
);
97 nir_options
->native_integers
= true;
98 /* In order to help allow for better CSE at the NIR level we tell NIR
99 * to split all ffma instructions during opt_algebraic and we then
100 * re-combine them as a later step.
102 nir_options
->lower_ffma
= true;
103 nir_options
->lower_sub
= true;
104 /* In the vec4 backend, our dpN instruction replicates its result to all
105 * the components of a vec4. We would like NIR to give us replicated fdot
106 * instructions because it can optimize better for us.
108 * For the FS backend, it should be lowered away by the scalarizing pass so
109 * we should never see fdot anyway.
111 nir_options
->fdot_replicates
= true;
113 /* We want the GLSL compiler to emit code that uses condition codes */
114 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
115 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
116 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
117 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
119 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
120 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
121 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
122 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
123 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
124 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
126 bool is_scalar
= compiler
->scalar_stage
[i
];
128 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
129 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
130 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
132 /* !ARB_gpu_shader5 */
133 if (devinfo
->gen
< 7)
134 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
136 compiler
->glsl_compiler_options
[i
].NirOptions
= nir_options
;
138 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
141 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectInput
= false;
142 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_EVAL
].EmitNoIndirectInput
= false;
144 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
145 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;
147 compiler
->glsl_compiler_options
[MESA_SHADER_COMPUTE
]
148 .LowerShaderSharedVariables
= true;
153 extern "C" struct gl_shader
*
154 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
156 struct brw_shader
*shader
;
158 shader
= rzalloc(NULL
, struct brw_shader
);
160 shader
->base
.Type
= type
;
161 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
162 shader
->base
.Name
= name
;
163 _mesa_init_shader(ctx
, &shader
->base
);
166 return &shader
->base
;
170 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
173 assert(surf_index
< BRW_MAX_SURFACES
);
175 prog_data
->binding_table
.size_bytes
=
176 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
180 brw_type_for_base_type(const struct glsl_type
*type
)
182 switch (type
->base_type
) {
183 case GLSL_TYPE_FLOAT
:
184 return BRW_REGISTER_TYPE_F
;
187 case GLSL_TYPE_SUBROUTINE
:
188 return BRW_REGISTER_TYPE_D
;
190 return BRW_REGISTER_TYPE_UD
;
191 case GLSL_TYPE_ARRAY
:
192 return brw_type_for_base_type(type
->fields
.array
);
193 case GLSL_TYPE_STRUCT
:
194 case GLSL_TYPE_SAMPLER
:
195 case GLSL_TYPE_ATOMIC_UINT
:
196 /* These should be overridden with the type of the member when
197 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
198 * way to trip up if we don't.
200 return BRW_REGISTER_TYPE_UD
;
201 case GLSL_TYPE_IMAGE
:
202 return BRW_REGISTER_TYPE_UD
;
204 case GLSL_TYPE_ERROR
:
205 case GLSL_TYPE_INTERFACE
:
206 case GLSL_TYPE_DOUBLE
:
207 unreachable("not reached");
210 return BRW_REGISTER_TYPE_F
;
213 enum brw_conditional_mod
214 brw_conditional_for_comparison(unsigned int op
)
218 return BRW_CONDITIONAL_L
;
219 case ir_binop_greater
:
220 return BRW_CONDITIONAL_G
;
221 case ir_binop_lequal
:
222 return BRW_CONDITIONAL_LE
;
223 case ir_binop_gequal
:
224 return BRW_CONDITIONAL_GE
;
226 case ir_binop_all_equal
: /* same as equal for scalars */
227 return BRW_CONDITIONAL_Z
;
228 case ir_binop_nequal
:
229 case ir_binop_any_nequal
: /* same as nequal for scalars */
230 return BRW_CONDITIONAL_NZ
;
232 unreachable("not reached: bad operation for comparison");
237 brw_math_function(enum opcode op
)
240 case SHADER_OPCODE_RCP
:
241 return BRW_MATH_FUNCTION_INV
;
242 case SHADER_OPCODE_RSQ
:
243 return BRW_MATH_FUNCTION_RSQ
;
244 case SHADER_OPCODE_SQRT
:
245 return BRW_MATH_FUNCTION_SQRT
;
246 case SHADER_OPCODE_EXP2
:
247 return BRW_MATH_FUNCTION_EXP
;
248 case SHADER_OPCODE_LOG2
:
249 return BRW_MATH_FUNCTION_LOG
;
250 case SHADER_OPCODE_POW
:
251 return BRW_MATH_FUNCTION_POW
;
252 case SHADER_OPCODE_SIN
:
253 return BRW_MATH_FUNCTION_SIN
;
254 case SHADER_OPCODE_COS
:
255 return BRW_MATH_FUNCTION_COS
;
256 case SHADER_OPCODE_INT_QUOTIENT
:
257 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
258 case SHADER_OPCODE_INT_REMAINDER
:
259 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
261 unreachable("not reached: unknown math function");
266 brw_texture_offset(int *offsets
, unsigned num_components
)
268 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
270 /* Combine all three offsets into a single unsigned dword:
272 * bits 11:8 - U Offset (X component)
273 * bits 7:4 - V Offset (Y component)
274 * bits 3:0 - R Offset (Z component)
276 unsigned offset_bits
= 0;
277 for (unsigned i
= 0; i
< num_components
; i
++) {
278 const unsigned shift
= 4 * (2 - i
);
279 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
285 brw_instruction_name(enum opcode op
)
288 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
289 assert(opcode_descs
[op
].name
);
290 return opcode_descs
[op
].name
;
291 case FS_OPCODE_FB_WRITE
:
293 case FS_OPCODE_FB_WRITE_LOGICAL
:
294 return "fb_write_logical";
295 case FS_OPCODE_PACK_STENCIL_REF
:
296 return "pack_stencil_ref";
297 case FS_OPCODE_BLORP_FB_WRITE
:
298 return "blorp_fb_write";
299 case FS_OPCODE_REP_FB_WRITE
:
300 return "rep_fb_write";
302 case SHADER_OPCODE_RCP
:
304 case SHADER_OPCODE_RSQ
:
306 case SHADER_OPCODE_SQRT
:
308 case SHADER_OPCODE_EXP2
:
310 case SHADER_OPCODE_LOG2
:
312 case SHADER_OPCODE_POW
:
314 case SHADER_OPCODE_INT_QUOTIENT
:
316 case SHADER_OPCODE_INT_REMAINDER
:
318 case SHADER_OPCODE_SIN
:
320 case SHADER_OPCODE_COS
:
323 case SHADER_OPCODE_TEX
:
325 case SHADER_OPCODE_TEX_LOGICAL
:
326 return "tex_logical";
327 case SHADER_OPCODE_TXD
:
329 case SHADER_OPCODE_TXD_LOGICAL
:
330 return "txd_logical";
331 case SHADER_OPCODE_TXF
:
333 case SHADER_OPCODE_TXF_LOGICAL
:
334 return "txf_logical";
335 case SHADER_OPCODE_TXL
:
337 case SHADER_OPCODE_TXL_LOGICAL
:
338 return "txl_logical";
339 case SHADER_OPCODE_TXS
:
341 case SHADER_OPCODE_TXS_LOGICAL
:
342 return "txs_logical";
345 case FS_OPCODE_TXB_LOGICAL
:
346 return "txb_logical";
347 case SHADER_OPCODE_TXF_CMS
:
349 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
350 return "txf_cms_logical";
351 case SHADER_OPCODE_TXF_CMS_W
:
353 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
354 return "txf_cms_w_logical";
355 case SHADER_OPCODE_TXF_UMS
:
357 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
358 return "txf_ums_logical";
359 case SHADER_OPCODE_TXF_MCS
:
361 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
362 return "txf_mcs_logical";
363 case SHADER_OPCODE_LOD
:
365 case SHADER_OPCODE_LOD_LOGICAL
:
366 return "lod_logical";
367 case SHADER_OPCODE_TG4
:
369 case SHADER_OPCODE_TG4_LOGICAL
:
370 return "tg4_logical";
371 case SHADER_OPCODE_TG4_OFFSET
:
373 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
374 return "tg4_offset_logical";
375 case SHADER_OPCODE_SAMPLEINFO
:
378 case SHADER_OPCODE_SHADER_TIME_ADD
:
379 return "shader_time_add";
381 case SHADER_OPCODE_UNTYPED_ATOMIC
:
382 return "untyped_atomic";
383 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
384 return "untyped_atomic_logical";
385 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
386 return "untyped_surface_read";
387 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
388 return "untyped_surface_read_logical";
389 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
390 return "untyped_surface_write";
391 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
392 return "untyped_surface_write_logical";
393 case SHADER_OPCODE_TYPED_ATOMIC
:
394 return "typed_atomic";
395 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
396 return "typed_atomic_logical";
397 case SHADER_OPCODE_TYPED_SURFACE_READ
:
398 return "typed_surface_read";
399 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
400 return "typed_surface_read_logical";
401 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
402 return "typed_surface_write";
403 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
404 return "typed_surface_write_logical";
405 case SHADER_OPCODE_MEMORY_FENCE
:
406 return "memory_fence";
408 case SHADER_OPCODE_LOAD_PAYLOAD
:
409 return "load_payload";
411 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
412 return "gen4_scratch_read";
413 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
414 return "gen4_scratch_write";
415 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
416 return "gen7_scratch_read";
417 case SHADER_OPCODE_URB_WRITE_SIMD8
:
418 return "gen8_urb_write_simd8";
419 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
420 return "gen8_urb_write_simd8_per_slot";
421 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
422 return "gen8_urb_write_simd8_masked";
423 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
424 return "gen8_urb_write_simd8_masked_per_slot";
425 case SHADER_OPCODE_URB_READ_SIMD8
:
426 return "urb_read_simd8";
427 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
428 return "urb_read_simd8_per_slot";
430 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
431 return "find_live_channel";
432 case SHADER_OPCODE_BROADCAST
:
435 case VEC4_OPCODE_MOV_BYTES
:
437 case VEC4_OPCODE_PACK_BYTES
:
439 case VEC4_OPCODE_UNPACK_UNIFORM
:
440 return "unpack_uniform";
442 case FS_OPCODE_DDX_COARSE
:
444 case FS_OPCODE_DDX_FINE
:
446 case FS_OPCODE_DDY_COARSE
:
448 case FS_OPCODE_DDY_FINE
:
451 case FS_OPCODE_CINTERP
:
453 case FS_OPCODE_LINTERP
:
456 case FS_OPCODE_PIXEL_X
:
458 case FS_OPCODE_PIXEL_Y
:
461 case FS_OPCODE_GET_BUFFER_SIZE
:
462 return "fs_get_buffer_size";
464 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
465 return "uniform_pull_const";
466 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
467 return "uniform_pull_const_gen7";
468 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
469 return "varying_pull_const";
470 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
471 return "varying_pull_const_gen7";
473 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
474 return "mov_dispatch_to_flags";
475 case FS_OPCODE_DISCARD_JUMP
:
476 return "discard_jump";
478 case FS_OPCODE_SET_SAMPLE_ID
:
479 return "set_sample_id";
480 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
481 return "set_simd4x2_offset";
483 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
484 return "pack_half_2x16_split";
485 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
486 return "unpack_half_2x16_split_x";
487 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
488 return "unpack_half_2x16_split_y";
490 case FS_OPCODE_PLACEHOLDER_HALT
:
491 return "placeholder_halt";
493 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
494 return "interp_centroid";
495 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
496 return "interp_sample";
497 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
498 return "interp_shared_offset";
499 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
500 return "interp_per_slot_offset";
502 case VS_OPCODE_URB_WRITE
:
503 return "vs_urb_write";
504 case VS_OPCODE_PULL_CONSTANT_LOAD
:
505 return "pull_constant_load";
506 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
507 return "pull_constant_load_gen7";
509 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
510 return "set_simd4x2_header_gen9";
512 case VS_OPCODE_GET_BUFFER_SIZE
:
513 return "vs_get_buffer_size";
515 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
516 return "unpack_flags_simd4x2";
518 case GS_OPCODE_URB_WRITE
:
519 return "gs_urb_write";
520 case GS_OPCODE_URB_WRITE_ALLOCATE
:
521 return "gs_urb_write_allocate";
522 case GS_OPCODE_THREAD_END
:
523 return "gs_thread_end";
524 case GS_OPCODE_SET_WRITE_OFFSET
:
525 return "set_write_offset";
526 case GS_OPCODE_SET_VERTEX_COUNT
:
527 return "set_vertex_count";
528 case GS_OPCODE_SET_DWORD_2
:
529 return "set_dword_2";
530 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
531 return "prepare_channel_masks";
532 case GS_OPCODE_SET_CHANNEL_MASKS
:
533 return "set_channel_masks";
534 case GS_OPCODE_GET_INSTANCE_ID
:
535 return "get_instance_id";
536 case GS_OPCODE_FF_SYNC
:
538 case GS_OPCODE_SET_PRIMITIVE_ID
:
539 return "set_primitive_id";
540 case GS_OPCODE_SVB_WRITE
:
541 return "gs_svb_write";
542 case GS_OPCODE_SVB_SET_DST_INDEX
:
543 return "gs_svb_set_dst_index";
544 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
545 return "gs_ff_sync_set_primitives";
546 case CS_OPCODE_CS_TERMINATE
:
547 return "cs_terminate";
548 case SHADER_OPCODE_BARRIER
:
550 case SHADER_OPCODE_MULH
:
552 case SHADER_OPCODE_MOV_INDIRECT
:
553 return "mov_indirect";
555 case VEC4_OPCODE_URB_READ
:
557 case TCS_OPCODE_GET_INSTANCE_ID
:
558 return "tcs_get_instance_id";
559 case TCS_OPCODE_URB_WRITE
:
560 return "tcs_urb_write";
561 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
562 return "tcs_set_input_urb_offsets";
563 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
564 return "tcs_set_output_urb_offsets";
565 case TCS_OPCODE_GET_PRIMITIVE_ID
:
566 return "tcs_get_primitive_id";
567 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
568 return "tcs_create_barrier_header";
571 unreachable("not reached");
575 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
581 } imm
= { reg
->ud
}, sat_imm
= { 0 };
584 case BRW_REGISTER_TYPE_UD
:
585 case BRW_REGISTER_TYPE_D
:
586 case BRW_REGISTER_TYPE_UW
:
587 case BRW_REGISTER_TYPE_W
:
588 case BRW_REGISTER_TYPE_UQ
:
589 case BRW_REGISTER_TYPE_Q
:
592 case BRW_REGISTER_TYPE_F
:
593 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
595 case BRW_REGISTER_TYPE_UB
:
596 case BRW_REGISTER_TYPE_B
:
597 unreachable("no UB/B immediates");
598 case BRW_REGISTER_TYPE_V
:
599 case BRW_REGISTER_TYPE_UV
:
600 case BRW_REGISTER_TYPE_VF
:
601 unreachable("unimplemented: saturate vector immediate");
602 case BRW_REGISTER_TYPE_DF
:
603 case BRW_REGISTER_TYPE_HF
:
604 unreachable("unimplemented: saturate DF/HF immediate");
607 if (imm
.ud
!= sat_imm
.ud
) {
608 reg
->ud
= sat_imm
.ud
;
615 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
618 case BRW_REGISTER_TYPE_D
:
619 case BRW_REGISTER_TYPE_UD
:
622 case BRW_REGISTER_TYPE_W
:
623 case BRW_REGISTER_TYPE_UW
:
624 reg
->d
= -(int16_t)reg
->ud
;
626 case BRW_REGISTER_TYPE_F
:
629 case BRW_REGISTER_TYPE_VF
:
630 reg
->ud
^= 0x80808080;
632 case BRW_REGISTER_TYPE_UB
:
633 case BRW_REGISTER_TYPE_B
:
634 unreachable("no UB/B immediates");
635 case BRW_REGISTER_TYPE_UV
:
636 case BRW_REGISTER_TYPE_V
:
637 assert(!"unimplemented: negate UV/V immediate");
638 case BRW_REGISTER_TYPE_UQ
:
639 case BRW_REGISTER_TYPE_Q
:
640 assert(!"unimplemented: negate UQ/Q immediate");
641 case BRW_REGISTER_TYPE_DF
:
642 case BRW_REGISTER_TYPE_HF
:
643 assert(!"unimplemented: negate DF/HF immediate");
650 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
653 case BRW_REGISTER_TYPE_D
:
654 reg
->d
= abs(reg
->d
);
656 case BRW_REGISTER_TYPE_W
:
657 reg
->d
= abs((int16_t)reg
->ud
);
659 case BRW_REGISTER_TYPE_F
:
660 reg
->f
= fabsf(reg
->f
);
662 case BRW_REGISTER_TYPE_VF
:
663 reg
->ud
&= ~0x80808080;
665 case BRW_REGISTER_TYPE_UB
:
666 case BRW_REGISTER_TYPE_B
:
667 unreachable("no UB/B immediates");
668 case BRW_REGISTER_TYPE_UQ
:
669 case BRW_REGISTER_TYPE_UD
:
670 case BRW_REGISTER_TYPE_UW
:
671 case BRW_REGISTER_TYPE_UV
:
672 /* Presumably the absolute value modifier on an unsigned source is a
673 * nop, but it would be nice to confirm.
675 assert(!"unimplemented: abs unsigned immediate");
676 case BRW_REGISTER_TYPE_V
:
677 assert(!"unimplemented: abs V immediate");
678 case BRW_REGISTER_TYPE_Q
:
679 assert(!"unimplemented: abs Q immediate");
680 case BRW_REGISTER_TYPE_DF
:
681 case BRW_REGISTER_TYPE_HF
:
682 assert(!"unimplemented: abs DF/HF immediate");
688 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
691 const nir_shader
*shader
,
692 struct brw_stage_prog_data
*stage_prog_data
)
693 : compiler(compiler
),
695 devinfo(compiler
->devinfo
),
697 stage_prog_data(stage_prog_data
),
702 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
703 stage_name
= _mesa_shader_stage_to_string(stage
);
704 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
708 backend_reg::equals(const backend_reg
&r
) const
710 return memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
711 reg_offset
== r
.reg_offset
;
715 backend_reg::is_zero() const
724 backend_reg::is_one() const
729 return type
== BRW_REGISTER_TYPE_F
735 backend_reg::is_negative_one() const
741 case BRW_REGISTER_TYPE_F
:
743 case BRW_REGISTER_TYPE_D
:
751 backend_reg::is_null() const
753 return file
== ARF
&& nr
== BRW_ARF_NULL
;
758 backend_reg::is_accumulator() const
760 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
764 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
766 return (file
== r
.file
&&
768 reg_offset
>= r
.reg_offset
&&
769 reg_offset
< r
.reg_offset
+ n
);
773 backend_instruction::is_commutative() const
781 case SHADER_OPCODE_MULH
:
784 /* MIN and MAX are commutative. */
785 if (conditional_mod
== BRW_CONDITIONAL_GE
||
786 conditional_mod
== BRW_CONDITIONAL_L
) {
796 backend_instruction::is_3src() const
798 return ::is_3src(opcode
);
802 backend_instruction::is_tex() const
804 return (opcode
== SHADER_OPCODE_TEX
||
805 opcode
== FS_OPCODE_TXB
||
806 opcode
== SHADER_OPCODE_TXD
||
807 opcode
== SHADER_OPCODE_TXF
||
808 opcode
== SHADER_OPCODE_TXF_CMS
||
809 opcode
== SHADER_OPCODE_TXF_CMS_W
||
810 opcode
== SHADER_OPCODE_TXF_UMS
||
811 opcode
== SHADER_OPCODE_TXF_MCS
||
812 opcode
== SHADER_OPCODE_TXL
||
813 opcode
== SHADER_OPCODE_TXS
||
814 opcode
== SHADER_OPCODE_LOD
||
815 opcode
== SHADER_OPCODE_TG4
||
816 opcode
== SHADER_OPCODE_TG4_OFFSET
);
820 backend_instruction::is_math() const
822 return (opcode
== SHADER_OPCODE_RCP
||
823 opcode
== SHADER_OPCODE_RSQ
||
824 opcode
== SHADER_OPCODE_SQRT
||
825 opcode
== SHADER_OPCODE_EXP2
||
826 opcode
== SHADER_OPCODE_LOG2
||
827 opcode
== SHADER_OPCODE_SIN
||
828 opcode
== SHADER_OPCODE_COS
||
829 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
830 opcode
== SHADER_OPCODE_INT_REMAINDER
||
831 opcode
== SHADER_OPCODE_POW
);
835 backend_instruction::is_control_flow() const
839 case BRW_OPCODE_WHILE
:
841 case BRW_OPCODE_ELSE
:
842 case BRW_OPCODE_ENDIF
:
843 case BRW_OPCODE_BREAK
:
844 case BRW_OPCODE_CONTINUE
:
852 backend_instruction::can_do_source_mods() const
855 case BRW_OPCODE_ADDC
:
857 case BRW_OPCODE_BFI1
:
858 case BRW_OPCODE_BFI2
:
859 case BRW_OPCODE_BFREV
:
860 case BRW_OPCODE_CBIT
:
863 case BRW_OPCODE_SUBB
:
871 backend_instruction::can_do_saturate() const
881 case BRW_OPCODE_F16TO32
:
882 case BRW_OPCODE_F32TO16
:
883 case BRW_OPCODE_LINE
:
887 case BRW_OPCODE_MATH
:
890 case SHADER_OPCODE_MULH
:
892 case BRW_OPCODE_RNDD
:
893 case BRW_OPCODE_RNDE
:
894 case BRW_OPCODE_RNDU
:
895 case BRW_OPCODE_RNDZ
:
899 case FS_OPCODE_LINTERP
:
900 case SHADER_OPCODE_COS
:
901 case SHADER_OPCODE_EXP2
:
902 case SHADER_OPCODE_LOG2
:
903 case SHADER_OPCODE_POW
:
904 case SHADER_OPCODE_RCP
:
905 case SHADER_OPCODE_RSQ
:
906 case SHADER_OPCODE_SIN
:
907 case SHADER_OPCODE_SQRT
:
915 backend_instruction::can_do_cmod() const
919 case BRW_OPCODE_ADDC
:
924 case BRW_OPCODE_CMPN
:
929 case BRW_OPCODE_F16TO32
:
930 case BRW_OPCODE_F32TO16
:
932 case BRW_OPCODE_LINE
:
936 case BRW_OPCODE_MACH
:
943 case BRW_OPCODE_RNDD
:
944 case BRW_OPCODE_RNDE
:
945 case BRW_OPCODE_RNDU
:
946 case BRW_OPCODE_RNDZ
:
947 case BRW_OPCODE_SAD2
:
948 case BRW_OPCODE_SADA2
:
951 case BRW_OPCODE_SUBB
:
953 case FS_OPCODE_CINTERP
:
954 case FS_OPCODE_LINTERP
:
962 backend_instruction::reads_accumulator_implicitly() const
966 case BRW_OPCODE_MACH
:
967 case BRW_OPCODE_SADA2
:
975 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
977 return writes_accumulator
||
979 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
980 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
981 opcode
!= FS_OPCODE_CINTERP
)));
985 backend_instruction::has_side_effects() const
988 case SHADER_OPCODE_UNTYPED_ATOMIC
:
989 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
990 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
991 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
992 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
993 case SHADER_OPCODE_TYPED_ATOMIC
:
994 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
995 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
996 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
997 case SHADER_OPCODE_MEMORY_FENCE
:
998 case SHADER_OPCODE_URB_WRITE_SIMD8
:
999 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1000 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1001 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1002 case FS_OPCODE_FB_WRITE
:
1003 case SHADER_OPCODE_BARRIER
:
1011 backend_instruction::is_volatile() const
1014 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1015 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1016 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1017 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1026 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1029 foreach_inst_in_block (backend_instruction
, i
, block
) {
1039 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1041 for (bblock_t
*block_iter
= start_block
->next();
1042 !block_iter
->link
.is_tail_sentinel();
1043 block_iter
= block_iter
->next()) {
1044 block_iter
->start_ip
+= ip_adjustment
;
1045 block_iter
->end_ip
+= ip_adjustment
;
1050 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1052 if (!this->is_head_sentinel())
1053 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1057 adjust_later_block_ips(block
, 1);
1059 exec_node::insert_after(inst
);
1063 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1065 if (!this->is_tail_sentinel())
1066 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1070 adjust_later_block_ips(block
, 1);
1072 exec_node::insert_before(inst
);
1076 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1078 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1080 unsigned num_inst
= list
->length();
1082 block
->end_ip
+= num_inst
;
1084 adjust_later_block_ips(block
, num_inst
);
1086 exec_node::insert_before(list
);
1090 backend_instruction::remove(bblock_t
*block
)
1092 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1094 adjust_later_block_ips(block
, -1);
1096 if (block
->start_ip
== block
->end_ip
) {
1097 block
->cfg
->remove_block(block
);
1102 exec_node::remove();
1106 backend_shader::dump_instructions()
1108 dump_instructions(NULL
);
1112 backend_shader::dump_instructions(const char *name
)
1114 FILE *file
= stderr
;
1115 if (name
&& geteuid() != 0) {
1116 file
= fopen(name
, "w");
1123 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1124 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1125 fprintf(file
, "%4d: ", ip
++);
1126 dump_instruction(inst
, file
);
1130 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1131 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1132 fprintf(file
, "%4d: ", ip
++);
1133 dump_instruction(inst
, file
);
1137 if (file
!= stderr
) {
1143 backend_shader::calculate_cfg()
1147 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1151 backend_shader::invalidate_cfg()
1153 ralloc_free(this->cfg
);
1158 * Sets up the starting offsets for the groups of binding table entries
1159 * commong to all pipeline stages.
1161 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1162 * unused but also make sure that addition of small offsets to them will
1163 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1166 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1167 const struct brw_device_info
*devinfo
,
1168 const struct gl_shader_program
*shader_prog
,
1169 const struct gl_program
*prog
,
1170 struct brw_stage_prog_data
*stage_prog_data
,
1171 uint32_t next_binding_table_offset
)
1173 const struct gl_shader
*shader
= NULL
;
1174 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1177 shader
= shader_prog
->_LinkedShaders
[stage
];
1179 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1180 next_binding_table_offset
+= num_textures
;
1183 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1184 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1185 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1187 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1188 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1189 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1191 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1192 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1195 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1196 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1197 next_binding_table_offset
++;
1199 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1202 if (prog
->UsesGather
) {
1203 if (devinfo
->gen
>= 8) {
1204 stage_prog_data
->binding_table
.gather_texture_start
=
1205 stage_prog_data
->binding_table
.texture_start
;
1207 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1208 next_binding_table_offset
+= num_textures
;
1211 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1214 if (shader
&& shader
->NumAtomicBuffers
) {
1215 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1216 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1218 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1221 if (shader
&& shader
->NumImages
) {
1222 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1223 next_binding_table_offset
+= shader
->NumImages
;
1225 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1228 /* This may or may not be used depending on how the compile goes. */
1229 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1230 next_binding_table_offset
++;
1232 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1234 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1238 setup_vec4_uniform_value(const gl_constant_value
**params
,
1239 const gl_constant_value
*values
,
1242 static const gl_constant_value zero
= { 0 };
1244 for (unsigned i
= 0; i
< n
; ++i
)
1245 params
[i
] = &values
[i
];
1247 for (unsigned i
= n
; i
< 4; ++i
)
1252 brw_setup_image_uniform_values(gl_shader_stage stage
,
1253 struct brw_stage_prog_data
*stage_prog_data
,
1254 unsigned param_start_index
,
1255 const gl_uniform_storage
*storage
)
1257 const gl_constant_value
**param
=
1258 &stage_prog_data
->param
[param_start_index
];
1260 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1261 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1262 const brw_image_param
*image_param
=
1263 &stage_prog_data
->image_param
[image_idx
];
1265 /* Upload the brw_image_param structure. The order is expected to match
1266 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1268 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1269 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1270 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1271 (const gl_constant_value
*)image_param
->offset
, 2);
1272 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1273 (const gl_constant_value
*)image_param
->size
, 3);
1274 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1275 (const gl_constant_value
*)image_param
->stride
, 4);
1276 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1277 (const gl_constant_value
*)image_param
->tiling
, 3);
1278 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1279 (const gl_constant_value
*)image_param
->swizzling
, 2);
1280 param
+= BRW_IMAGE_PARAM_SIZE
;
1282 brw_mark_surface_used(
1284 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1289 * Decide which set of clip planes should be used when clipping via
1290 * gl_Position or gl_ClipVertex.
1292 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1294 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1295 /* There is currently a GLSL vertex shader, so clip according to GLSL
1296 * rules, which means compare gl_ClipVertex (or gl_Position, if
1297 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1298 * that were stored in EyeUserPlane at the time the clip planes were
1301 return ctx
->Transform
.EyeUserPlane
;
1303 /* Either we are using fixed function or an ARB vertex program. In
1304 * either case the clip planes are going to be compared against
1305 * gl_Position (which is in clip coordinates) so we have to clip using
1306 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1309 return ctx
->Transform
._ClipUserPlane
;
1313 extern "C" const unsigned *
1314 brw_compile_tes(const struct brw_compiler
*compiler
,
1317 const struct brw_tes_prog_key
*key
,
1318 struct brw_tes_prog_data
*prog_data
,
1319 const nir_shader
*src_shader
,
1320 struct gl_shader_program
*shader_prog
,
1321 int shader_time_index
,
1322 unsigned *final_assembly_size
,
1325 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
1326 struct gl_shader
*shader
=
1327 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
];
1328 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1330 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1331 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
1332 nir
->info
.inputs_read
= key
->inputs_read
;
1333 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1334 nir
= brw_nir_lower_io(nir
, compiler
->devinfo
, is_scalar
);
1335 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
1337 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1338 nir
->info
.outputs_written
,
1339 nir
->info
.separate_shader
);
1341 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1343 assert(output_size_bytes
>= 1);
1344 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1346 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1350 /* URB entry sizes are stored as a multiple of 64 bytes. */
1351 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1353 struct brw_vue_map input_vue_map
;
1354 brw_compute_tess_vue_map(&input_vue_map
,
1355 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
1356 nir
->info
.patch_inputs_read
);
1358 bool need_patch_header
= nir
->info
.system_values_read
&
1359 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER
) |
1360 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER
));
1362 /* The TES will pull most inputs using URB read messages.
1364 * However, we push the patch header for TessLevel factors when required,
1365 * as it's a tiny amount of extra data.
1367 prog_data
->base
.urb_read_length
= need_patch_header
? 1 : 0;
1369 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1370 fprintf(stderr
, "TES Input ");
1371 brw_print_vue_map(stderr
, &input_vue_map
);
1372 fprintf(stderr
, "TES Output ");
1373 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1377 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1378 &prog_data
->base
.base
, shader
->Program
, nir
, 8,
1379 shader_time_index
, &input_vue_map
);
1382 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1386 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1388 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1389 &prog_data
->base
.base
, v
.promoted_constants
, false,
1391 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1392 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1393 "%s tessellation evaluation shader %s",
1394 nir
->info
.label
? nir
->info
.label
1399 g
.generate_code(v
.cfg
, 8);
1401 return g
.get_assembly(final_assembly_size
);
1403 unreachable("XXX: vec4 tessellation evalation shaders not merged yet.");