2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
29 #include "brw_vec4_tes.h"
30 #include "main/shaderobj.h"
31 #include "main/uniforms.h"
33 extern "C" struct gl_shader
*
34 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
36 struct brw_shader
*shader
;
38 shader
= rzalloc(NULL
, struct brw_shader
);
40 shader
->base
.Type
= type
;
41 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
42 shader
->base
.Name
= name
;
43 _mesa_init_shader(ctx
, &shader
->base
);
50 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
53 assert(surf_index
< BRW_MAX_SURFACES
);
55 prog_data
->binding_table
.size_bytes
=
56 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
60 brw_type_for_base_type(const struct glsl_type
*type
)
62 switch (type
->base_type
) {
64 return BRW_REGISTER_TYPE_F
;
67 case GLSL_TYPE_SUBROUTINE
:
68 return BRW_REGISTER_TYPE_D
;
70 return BRW_REGISTER_TYPE_UD
;
72 return brw_type_for_base_type(type
->fields
.array
);
73 case GLSL_TYPE_STRUCT
:
74 case GLSL_TYPE_SAMPLER
:
75 case GLSL_TYPE_ATOMIC_UINT
:
76 /* These should be overridden with the type of the member when
77 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
78 * way to trip up if we don't.
80 return BRW_REGISTER_TYPE_UD
;
82 return BRW_REGISTER_TYPE_UD
;
83 case GLSL_TYPE_DOUBLE
:
84 return BRW_REGISTER_TYPE_DF
;
87 case GLSL_TYPE_INTERFACE
:
88 case GLSL_TYPE_FUNCTION
:
89 unreachable("not reached");
92 return BRW_REGISTER_TYPE_F
;
95 enum brw_conditional_mod
96 brw_conditional_for_comparison(unsigned int op
)
100 return BRW_CONDITIONAL_L
;
101 case ir_binop_greater
:
102 return BRW_CONDITIONAL_G
;
103 case ir_binop_lequal
:
104 return BRW_CONDITIONAL_LE
;
105 case ir_binop_gequal
:
106 return BRW_CONDITIONAL_GE
;
108 case ir_binop_all_equal
: /* same as equal for scalars */
109 return BRW_CONDITIONAL_Z
;
110 case ir_binop_nequal
:
111 case ir_binop_any_nequal
: /* same as nequal for scalars */
112 return BRW_CONDITIONAL_NZ
;
114 unreachable("not reached: bad operation for comparison");
119 brw_math_function(enum opcode op
)
122 case SHADER_OPCODE_RCP
:
123 return BRW_MATH_FUNCTION_INV
;
124 case SHADER_OPCODE_RSQ
:
125 return BRW_MATH_FUNCTION_RSQ
;
126 case SHADER_OPCODE_SQRT
:
127 return BRW_MATH_FUNCTION_SQRT
;
128 case SHADER_OPCODE_EXP2
:
129 return BRW_MATH_FUNCTION_EXP
;
130 case SHADER_OPCODE_LOG2
:
131 return BRW_MATH_FUNCTION_LOG
;
132 case SHADER_OPCODE_POW
:
133 return BRW_MATH_FUNCTION_POW
;
134 case SHADER_OPCODE_SIN
:
135 return BRW_MATH_FUNCTION_SIN
;
136 case SHADER_OPCODE_COS
:
137 return BRW_MATH_FUNCTION_COS
;
138 case SHADER_OPCODE_INT_QUOTIENT
:
139 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
140 case SHADER_OPCODE_INT_REMAINDER
:
141 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
143 unreachable("not reached: unknown math function");
148 brw_texture_offset(int *offsets
, unsigned num_components
)
150 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
152 /* Combine all three offsets into a single unsigned dword:
154 * bits 11:8 - U Offset (X component)
155 * bits 7:4 - V Offset (Y component)
156 * bits 3:0 - R Offset (Z component)
158 unsigned offset_bits
= 0;
159 for (unsigned i
= 0; i
< num_components
; i
++) {
160 const unsigned shift
= 4 * (2 - i
);
161 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
167 brw_instruction_name(const struct brw_device_info
*devinfo
, enum opcode op
)
170 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
171 assert(brw_opcode_desc(devinfo
, op
)->name
);
172 return brw_opcode_desc(devinfo
, op
)->name
;
173 case FS_OPCODE_FB_WRITE
:
175 case FS_OPCODE_FB_WRITE_LOGICAL
:
176 return "fb_write_logical";
177 case FS_OPCODE_PACK_STENCIL_REF
:
178 return "pack_stencil_ref";
179 case FS_OPCODE_BLORP_FB_WRITE
:
180 return "blorp_fb_write";
181 case FS_OPCODE_REP_FB_WRITE
:
182 return "rep_fb_write";
184 case SHADER_OPCODE_RCP
:
186 case SHADER_OPCODE_RSQ
:
188 case SHADER_OPCODE_SQRT
:
190 case SHADER_OPCODE_EXP2
:
192 case SHADER_OPCODE_LOG2
:
194 case SHADER_OPCODE_POW
:
196 case SHADER_OPCODE_INT_QUOTIENT
:
198 case SHADER_OPCODE_INT_REMAINDER
:
200 case SHADER_OPCODE_SIN
:
202 case SHADER_OPCODE_COS
:
205 case SHADER_OPCODE_TEX
:
207 case SHADER_OPCODE_TEX_LOGICAL
:
208 return "tex_logical";
209 case SHADER_OPCODE_TXD
:
211 case SHADER_OPCODE_TXD_LOGICAL
:
212 return "txd_logical";
213 case SHADER_OPCODE_TXF
:
215 case SHADER_OPCODE_TXF_LOGICAL
:
216 return "txf_logical";
217 case SHADER_OPCODE_TXL
:
219 case SHADER_OPCODE_TXL_LOGICAL
:
220 return "txl_logical";
221 case SHADER_OPCODE_TXS
:
223 case SHADER_OPCODE_TXS_LOGICAL
:
224 return "txs_logical";
227 case FS_OPCODE_TXB_LOGICAL
:
228 return "txb_logical";
229 case SHADER_OPCODE_TXF_CMS
:
231 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
232 return "txf_cms_logical";
233 case SHADER_OPCODE_TXF_CMS_W
:
235 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
236 return "txf_cms_w_logical";
237 case SHADER_OPCODE_TXF_UMS
:
239 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
240 return "txf_ums_logical";
241 case SHADER_OPCODE_TXF_MCS
:
243 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
244 return "txf_mcs_logical";
245 case SHADER_OPCODE_LOD
:
247 case SHADER_OPCODE_LOD_LOGICAL
:
248 return "lod_logical";
249 case SHADER_OPCODE_TG4
:
251 case SHADER_OPCODE_TG4_LOGICAL
:
252 return "tg4_logical";
253 case SHADER_OPCODE_TG4_OFFSET
:
255 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
256 return "tg4_offset_logical";
257 case SHADER_OPCODE_SAMPLEINFO
:
260 case SHADER_OPCODE_SHADER_TIME_ADD
:
261 return "shader_time_add";
263 case SHADER_OPCODE_UNTYPED_ATOMIC
:
264 return "untyped_atomic";
265 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
266 return "untyped_atomic_logical";
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 return "untyped_surface_read";
269 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
270 return "untyped_surface_read_logical";
271 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
272 return "untyped_surface_write";
273 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
274 return "untyped_surface_write_logical";
275 case SHADER_OPCODE_TYPED_ATOMIC
:
276 return "typed_atomic";
277 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
278 return "typed_atomic_logical";
279 case SHADER_OPCODE_TYPED_SURFACE_READ
:
280 return "typed_surface_read";
281 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
282 return "typed_surface_read_logical";
283 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
284 return "typed_surface_write";
285 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
286 return "typed_surface_write_logical";
287 case SHADER_OPCODE_MEMORY_FENCE
:
288 return "memory_fence";
290 case SHADER_OPCODE_LOAD_PAYLOAD
:
291 return "load_payload";
293 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
294 return "gen4_scratch_read";
295 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
296 return "gen4_scratch_write";
297 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
298 return "gen7_scratch_read";
299 case SHADER_OPCODE_URB_WRITE_SIMD8
:
300 return "gen8_urb_write_simd8";
301 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
302 return "gen8_urb_write_simd8_per_slot";
303 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
304 return "gen8_urb_write_simd8_masked";
305 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
306 return "gen8_urb_write_simd8_masked_per_slot";
307 case SHADER_OPCODE_URB_READ_SIMD8
:
308 return "urb_read_simd8";
309 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
310 return "urb_read_simd8_per_slot";
312 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
313 return "find_live_channel";
314 case SHADER_OPCODE_BROADCAST
:
317 case SHADER_OPCODE_EXTRACT_BYTE
:
318 return "extract_byte";
319 case SHADER_OPCODE_EXTRACT_WORD
:
320 return "extract_word";
321 case VEC4_OPCODE_MOV_BYTES
:
323 case VEC4_OPCODE_PACK_BYTES
:
325 case VEC4_OPCODE_UNPACK_UNIFORM
:
326 return "unpack_uniform";
328 case FS_OPCODE_DDX_COARSE
:
330 case FS_OPCODE_DDX_FINE
:
332 case FS_OPCODE_DDY_COARSE
:
334 case FS_OPCODE_DDY_FINE
:
337 case FS_OPCODE_CINTERP
:
339 case FS_OPCODE_LINTERP
:
342 case FS_OPCODE_PIXEL_X
:
344 case FS_OPCODE_PIXEL_Y
:
347 case FS_OPCODE_GET_BUFFER_SIZE
:
348 return "fs_get_buffer_size";
350 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
351 return "uniform_pull_const";
352 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
353 return "uniform_pull_const_gen7";
354 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
355 return "varying_pull_const";
356 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
357 return "varying_pull_const_gen7";
359 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
360 return "mov_dispatch_to_flags";
361 case FS_OPCODE_DISCARD_JUMP
:
362 return "discard_jump";
364 case FS_OPCODE_SET_SAMPLE_ID
:
365 return "set_sample_id";
366 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
367 return "set_simd4x2_offset";
369 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
370 return "pack_half_2x16_split";
371 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
372 return "unpack_half_2x16_split_x";
373 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
374 return "unpack_half_2x16_split_y";
376 case FS_OPCODE_PLACEHOLDER_HALT
:
377 return "placeholder_halt";
379 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
380 return "interp_centroid";
381 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
382 return "interp_sample";
383 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
384 return "interp_shared_offset";
385 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
386 return "interp_per_slot_offset";
388 case VS_OPCODE_URB_WRITE
:
389 return "vs_urb_write";
390 case VS_OPCODE_PULL_CONSTANT_LOAD
:
391 return "pull_constant_load";
392 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
393 return "pull_constant_load_gen7";
395 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
396 return "set_simd4x2_header_gen9";
398 case VS_OPCODE_GET_BUFFER_SIZE
:
399 return "vs_get_buffer_size";
401 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
402 return "unpack_flags_simd4x2";
404 case GS_OPCODE_URB_WRITE
:
405 return "gs_urb_write";
406 case GS_OPCODE_URB_WRITE_ALLOCATE
:
407 return "gs_urb_write_allocate";
408 case GS_OPCODE_THREAD_END
:
409 return "gs_thread_end";
410 case GS_OPCODE_SET_WRITE_OFFSET
:
411 return "set_write_offset";
412 case GS_OPCODE_SET_VERTEX_COUNT
:
413 return "set_vertex_count";
414 case GS_OPCODE_SET_DWORD_2
:
415 return "set_dword_2";
416 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
417 return "prepare_channel_masks";
418 case GS_OPCODE_SET_CHANNEL_MASKS
:
419 return "set_channel_masks";
420 case GS_OPCODE_GET_INSTANCE_ID
:
421 return "get_instance_id";
422 case GS_OPCODE_FF_SYNC
:
424 case GS_OPCODE_SET_PRIMITIVE_ID
:
425 return "set_primitive_id";
426 case GS_OPCODE_SVB_WRITE
:
427 return "gs_svb_write";
428 case GS_OPCODE_SVB_SET_DST_INDEX
:
429 return "gs_svb_set_dst_index";
430 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
431 return "gs_ff_sync_set_primitives";
432 case CS_OPCODE_CS_TERMINATE
:
433 return "cs_terminate";
434 case SHADER_OPCODE_BARRIER
:
436 case SHADER_OPCODE_MULH
:
438 case SHADER_OPCODE_MOV_INDIRECT
:
439 return "mov_indirect";
441 case VEC4_OPCODE_URB_READ
:
443 case TCS_OPCODE_GET_INSTANCE_ID
:
444 return "tcs_get_instance_id";
445 case TCS_OPCODE_URB_WRITE
:
446 return "tcs_urb_write";
447 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
448 return "tcs_set_input_urb_offsets";
449 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
450 return "tcs_set_output_urb_offsets";
451 case TCS_OPCODE_GET_PRIMITIVE_ID
:
452 return "tcs_get_primitive_id";
453 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
454 return "tcs_create_barrier_header";
455 case TCS_OPCODE_SRC0_010_IS_ZERO
:
456 return "tcs_src0<0,1,0>_is_zero";
457 case TCS_OPCODE_RELEASE_INPUT
:
458 return "tcs_release_input";
459 case TCS_OPCODE_THREAD_END
:
460 return "tcs_thread_end";
461 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
462 return "tes_create_input_read_header";
463 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
464 return "tes_add_indirect_urb_offset";
465 case TES_OPCODE_GET_PRIMITIVE_ID
:
466 return "tes_get_primitive_id";
469 unreachable("not reached");
473 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
479 } imm
= { reg
->ud
}, sat_imm
= { 0 };
482 case BRW_REGISTER_TYPE_UD
:
483 case BRW_REGISTER_TYPE_D
:
484 case BRW_REGISTER_TYPE_UW
:
485 case BRW_REGISTER_TYPE_W
:
486 case BRW_REGISTER_TYPE_UQ
:
487 case BRW_REGISTER_TYPE_Q
:
490 case BRW_REGISTER_TYPE_F
:
491 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
493 case BRW_REGISTER_TYPE_UB
:
494 case BRW_REGISTER_TYPE_B
:
495 unreachable("no UB/B immediates");
496 case BRW_REGISTER_TYPE_V
:
497 case BRW_REGISTER_TYPE_UV
:
498 case BRW_REGISTER_TYPE_VF
:
499 unreachable("unimplemented: saturate vector immediate");
500 case BRW_REGISTER_TYPE_DF
:
501 case BRW_REGISTER_TYPE_HF
:
502 unreachable("unimplemented: saturate DF/HF immediate");
505 if (imm
.ud
!= sat_imm
.ud
) {
506 reg
->ud
= sat_imm
.ud
;
513 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
516 case BRW_REGISTER_TYPE_D
:
517 case BRW_REGISTER_TYPE_UD
:
520 case BRW_REGISTER_TYPE_W
:
521 case BRW_REGISTER_TYPE_UW
:
522 reg
->d
= -(int16_t)reg
->ud
;
524 case BRW_REGISTER_TYPE_F
:
527 case BRW_REGISTER_TYPE_VF
:
528 reg
->ud
^= 0x80808080;
530 case BRW_REGISTER_TYPE_DF
:
533 case BRW_REGISTER_TYPE_UB
:
534 case BRW_REGISTER_TYPE_B
:
535 unreachable("no UB/B immediates");
536 case BRW_REGISTER_TYPE_UV
:
537 case BRW_REGISTER_TYPE_V
:
538 assert(!"unimplemented: negate UV/V immediate");
539 case BRW_REGISTER_TYPE_UQ
:
540 case BRW_REGISTER_TYPE_Q
:
541 assert(!"unimplemented: negate UQ/Q immediate");
542 case BRW_REGISTER_TYPE_HF
:
543 assert(!"unimplemented: negate HF immediate");
550 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
553 case BRW_REGISTER_TYPE_D
:
554 reg
->d
= abs(reg
->d
);
556 case BRW_REGISTER_TYPE_W
:
557 reg
->d
= abs((int16_t)reg
->ud
);
559 case BRW_REGISTER_TYPE_F
:
560 reg
->f
= fabsf(reg
->f
);
562 case BRW_REGISTER_TYPE_VF
:
563 reg
->ud
&= ~0x80808080;
565 case BRW_REGISTER_TYPE_UB
:
566 case BRW_REGISTER_TYPE_B
:
567 unreachable("no UB/B immediates");
568 case BRW_REGISTER_TYPE_UQ
:
569 case BRW_REGISTER_TYPE_UD
:
570 case BRW_REGISTER_TYPE_UW
:
571 case BRW_REGISTER_TYPE_UV
:
572 /* Presumably the absolute value modifier on an unsigned source is a
573 * nop, but it would be nice to confirm.
575 assert(!"unimplemented: abs unsigned immediate");
576 case BRW_REGISTER_TYPE_V
:
577 assert(!"unimplemented: abs V immediate");
578 case BRW_REGISTER_TYPE_Q
:
579 assert(!"unimplemented: abs Q immediate");
580 case BRW_REGISTER_TYPE_DF
:
581 case BRW_REGISTER_TYPE_HF
:
582 assert(!"unimplemented: abs DF/HF immediate");
589 tesslevel_outer_components(GLenum tes_primitive_mode
)
591 switch (tes_primitive_mode
) {
599 unreachable("Bogus tessellation domain");
605 tesslevel_inner_components(GLenum tes_primitive_mode
)
607 switch (tes_primitive_mode
) {
615 unreachable("Bogus tessellation domain");
621 * Given a normal .xyzw writemask, convert it to a writemask for a vector
622 * that's stored backwards, i.e. .wzyx.
625 writemask_for_backwards_vector(unsigned mask
)
627 unsigned new_mask
= 0;
629 for (int i
= 0; i
< 4; i
++)
630 new_mask
|= ((mask
>> i
) & 1) << (3 - i
);
635 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
638 const nir_shader
*shader
,
639 struct brw_stage_prog_data
*stage_prog_data
)
640 : compiler(compiler
),
642 devinfo(compiler
->devinfo
),
644 stage_prog_data(stage_prog_data
),
649 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
650 stage_name
= _mesa_shader_stage_to_string(stage
);
651 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
652 is_passthrough_shader
=
653 nir
->info
.name
&& strcmp(nir
->info
.name
, "passthrough") == 0;
657 backend_reg::equals(const backend_reg
&r
) const
659 return memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
660 reg_offset
== r
.reg_offset
;
664 backend_reg::is_zero() const
670 case BRW_REGISTER_TYPE_F
:
672 case BRW_REGISTER_TYPE_DF
:
674 case BRW_REGISTER_TYPE_D
:
675 case BRW_REGISTER_TYPE_UD
:
683 backend_reg::is_one() const
689 case BRW_REGISTER_TYPE_F
:
691 case BRW_REGISTER_TYPE_DF
:
693 case BRW_REGISTER_TYPE_D
:
694 case BRW_REGISTER_TYPE_UD
:
702 backend_reg::is_negative_one() const
708 case BRW_REGISTER_TYPE_F
:
710 case BRW_REGISTER_TYPE_DF
:
712 case BRW_REGISTER_TYPE_D
:
720 backend_reg::is_null() const
722 return file
== ARF
&& nr
== BRW_ARF_NULL
;
727 backend_reg::is_accumulator() const
729 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
733 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
735 return (file
== r
.file
&&
737 reg_offset
>= r
.reg_offset
&&
738 reg_offset
< r
.reg_offset
+ n
);
742 backend_instruction::is_commutative() const
750 case SHADER_OPCODE_MULH
:
753 /* MIN and MAX are commutative. */
754 if (conditional_mod
== BRW_CONDITIONAL_GE
||
755 conditional_mod
== BRW_CONDITIONAL_L
) {
765 backend_instruction::is_3src(const struct brw_device_info
*devinfo
) const
767 return ::is_3src(devinfo
, opcode
);
771 backend_instruction::is_tex() const
773 return (opcode
== SHADER_OPCODE_TEX
||
774 opcode
== FS_OPCODE_TXB
||
775 opcode
== SHADER_OPCODE_TXD
||
776 opcode
== SHADER_OPCODE_TXF
||
777 opcode
== SHADER_OPCODE_TXF_CMS
||
778 opcode
== SHADER_OPCODE_TXF_CMS_W
||
779 opcode
== SHADER_OPCODE_TXF_UMS
||
780 opcode
== SHADER_OPCODE_TXF_MCS
||
781 opcode
== SHADER_OPCODE_TXL
||
782 opcode
== SHADER_OPCODE_TXS
||
783 opcode
== SHADER_OPCODE_LOD
||
784 opcode
== SHADER_OPCODE_TG4
||
785 opcode
== SHADER_OPCODE_TG4_OFFSET
||
786 opcode
== SHADER_OPCODE_SAMPLEINFO
);
790 backend_instruction::is_math() const
792 return (opcode
== SHADER_OPCODE_RCP
||
793 opcode
== SHADER_OPCODE_RSQ
||
794 opcode
== SHADER_OPCODE_SQRT
||
795 opcode
== SHADER_OPCODE_EXP2
||
796 opcode
== SHADER_OPCODE_LOG2
||
797 opcode
== SHADER_OPCODE_SIN
||
798 opcode
== SHADER_OPCODE_COS
||
799 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
800 opcode
== SHADER_OPCODE_INT_REMAINDER
||
801 opcode
== SHADER_OPCODE_POW
);
805 backend_instruction::is_control_flow() const
809 case BRW_OPCODE_WHILE
:
811 case BRW_OPCODE_ELSE
:
812 case BRW_OPCODE_ENDIF
:
813 case BRW_OPCODE_BREAK
:
814 case BRW_OPCODE_CONTINUE
:
822 backend_instruction::can_do_source_mods() const
825 case BRW_OPCODE_ADDC
:
827 case BRW_OPCODE_BFI1
:
828 case BRW_OPCODE_BFI2
:
829 case BRW_OPCODE_BFREV
:
830 case BRW_OPCODE_CBIT
:
833 case BRW_OPCODE_SUBB
:
841 backend_instruction::can_do_saturate() const
851 case BRW_OPCODE_F16TO32
:
852 case BRW_OPCODE_F32TO16
:
853 case BRW_OPCODE_LINE
:
857 case BRW_OPCODE_MATH
:
860 case SHADER_OPCODE_MULH
:
862 case BRW_OPCODE_RNDD
:
863 case BRW_OPCODE_RNDE
:
864 case BRW_OPCODE_RNDU
:
865 case BRW_OPCODE_RNDZ
:
869 case FS_OPCODE_LINTERP
:
870 case SHADER_OPCODE_COS
:
871 case SHADER_OPCODE_EXP2
:
872 case SHADER_OPCODE_LOG2
:
873 case SHADER_OPCODE_POW
:
874 case SHADER_OPCODE_RCP
:
875 case SHADER_OPCODE_RSQ
:
876 case SHADER_OPCODE_SIN
:
877 case SHADER_OPCODE_SQRT
:
885 backend_instruction::can_do_cmod() const
889 case BRW_OPCODE_ADDC
:
894 case BRW_OPCODE_CMPN
:
899 case BRW_OPCODE_F16TO32
:
900 case BRW_OPCODE_F32TO16
:
902 case BRW_OPCODE_LINE
:
906 case BRW_OPCODE_MACH
:
913 case BRW_OPCODE_RNDD
:
914 case BRW_OPCODE_RNDE
:
915 case BRW_OPCODE_RNDU
:
916 case BRW_OPCODE_RNDZ
:
917 case BRW_OPCODE_SAD2
:
918 case BRW_OPCODE_SADA2
:
921 case BRW_OPCODE_SUBB
:
923 case FS_OPCODE_CINTERP
:
924 case FS_OPCODE_LINTERP
:
932 backend_instruction::reads_accumulator_implicitly() const
936 case BRW_OPCODE_MACH
:
937 case BRW_OPCODE_SADA2
:
945 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
947 return writes_accumulator
||
949 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
950 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
951 opcode
!= FS_OPCODE_CINTERP
)));
955 backend_instruction::has_side_effects() const
958 case SHADER_OPCODE_UNTYPED_ATOMIC
:
959 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
960 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
961 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
962 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
963 case SHADER_OPCODE_TYPED_ATOMIC
:
964 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
965 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
966 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
967 case SHADER_OPCODE_MEMORY_FENCE
:
968 case SHADER_OPCODE_URB_WRITE_SIMD8
:
969 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
970 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
971 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
972 case FS_OPCODE_FB_WRITE
:
973 case SHADER_OPCODE_BARRIER
:
974 case TCS_OPCODE_URB_WRITE
:
975 case TCS_OPCODE_RELEASE_INPUT
:
983 backend_instruction::is_volatile() const
986 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
987 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
988 case SHADER_OPCODE_TYPED_SURFACE_READ
:
989 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
990 case SHADER_OPCODE_URB_READ_SIMD8
:
991 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
992 case VEC4_OPCODE_URB_READ
:
1001 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1004 foreach_inst_in_block (backend_instruction
, i
, block
) {
1014 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1016 for (bblock_t
*block_iter
= start_block
->next();
1018 block_iter
= block_iter
->next()) {
1019 block_iter
->start_ip
+= ip_adjustment
;
1020 block_iter
->end_ip
+= ip_adjustment
;
1025 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1027 assert(this != inst
);
1029 if (!this->is_head_sentinel())
1030 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1034 adjust_later_block_ips(block
, 1);
1036 exec_node::insert_after(inst
);
1040 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1042 assert(this != inst
);
1044 if (!this->is_tail_sentinel())
1045 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1049 adjust_later_block_ips(block
, 1);
1051 exec_node::insert_before(inst
);
1055 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1057 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1059 unsigned num_inst
= list
->length();
1061 block
->end_ip
+= num_inst
;
1063 adjust_later_block_ips(block
, num_inst
);
1065 exec_node::insert_before(list
);
1069 backend_instruction::remove(bblock_t
*block
)
1071 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1073 adjust_later_block_ips(block
, -1);
1075 if (block
->start_ip
== block
->end_ip
) {
1076 block
->cfg
->remove_block(block
);
1081 exec_node::remove();
1085 backend_shader::dump_instructions()
1087 dump_instructions(NULL
);
1091 backend_shader::dump_instructions(const char *name
)
1093 FILE *file
= stderr
;
1094 if (name
&& geteuid() != 0) {
1095 file
= fopen(name
, "w");
1102 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1103 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1104 fprintf(file
, "%4d: ", ip
++);
1105 dump_instruction(inst
, file
);
1109 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1110 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1111 fprintf(file
, "%4d: ", ip
++);
1112 dump_instruction(inst
, file
);
1116 if (file
!= stderr
) {
1122 backend_shader::calculate_cfg()
1126 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1130 * Sets up the starting offsets for the groups of binding table entries
1131 * commong to all pipeline stages.
1133 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1134 * unused but also make sure that addition of small offsets to them will
1135 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1138 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1139 const struct brw_device_info
*devinfo
,
1140 const struct gl_shader_program
*shader_prog
,
1141 const struct gl_program
*prog
,
1142 struct brw_stage_prog_data
*stage_prog_data
,
1143 uint32_t next_binding_table_offset
)
1145 const struct gl_shader
*shader
= NULL
;
1146 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1149 shader
= shader_prog
->_LinkedShaders
[stage
];
1151 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1152 next_binding_table_offset
+= num_textures
;
1155 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1156 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1157 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1159 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1160 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1161 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1163 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1164 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1167 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1168 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1169 next_binding_table_offset
++;
1171 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1174 if (prog
->UsesGather
) {
1175 if (devinfo
->gen
>= 8) {
1176 stage_prog_data
->binding_table
.gather_texture_start
=
1177 stage_prog_data
->binding_table
.texture_start
;
1179 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1180 next_binding_table_offset
+= num_textures
;
1183 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1186 if (shader
&& shader
->NumAtomicBuffers
) {
1187 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1188 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1190 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1193 if (shader
&& shader
->NumImages
) {
1194 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1195 next_binding_table_offset
+= shader
->NumImages
;
1197 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1200 /* This may or may not be used depending on how the compile goes. */
1201 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1202 next_binding_table_offset
++;
1204 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1206 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1210 setup_vec4_uniform_value(const gl_constant_value
**params
,
1211 const gl_constant_value
*values
,
1214 static const gl_constant_value zero
= { 0 };
1216 for (unsigned i
= 0; i
< n
; ++i
)
1217 params
[i
] = &values
[i
];
1219 for (unsigned i
= n
; i
< 4; ++i
)
1224 brw_setup_image_uniform_values(gl_shader_stage stage
,
1225 struct brw_stage_prog_data
*stage_prog_data
,
1226 unsigned param_start_index
,
1227 const gl_uniform_storage
*storage
)
1229 const gl_constant_value
**param
=
1230 &stage_prog_data
->param
[param_start_index
];
1232 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1233 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1234 const brw_image_param
*image_param
=
1235 &stage_prog_data
->image_param
[image_idx
];
1237 /* Upload the brw_image_param structure. The order is expected to match
1238 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1240 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1241 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1242 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1243 (const gl_constant_value
*)image_param
->offset
, 2);
1244 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1245 (const gl_constant_value
*)image_param
->size
, 3);
1246 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1247 (const gl_constant_value
*)image_param
->stride
, 4);
1248 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1249 (const gl_constant_value
*)image_param
->tiling
, 3);
1250 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1251 (const gl_constant_value
*)image_param
->swizzling
, 2);
1252 param
+= BRW_IMAGE_PARAM_SIZE
;
1254 brw_mark_surface_used(
1256 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1261 * Decide which set of clip planes should be used when clipping via
1262 * gl_Position or gl_ClipVertex.
1264 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1266 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1267 /* There is currently a GLSL vertex shader, so clip according to GLSL
1268 * rules, which means compare gl_ClipVertex (or gl_Position, if
1269 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1270 * that were stored in EyeUserPlane at the time the clip planes were
1273 return ctx
->Transform
.EyeUserPlane
;
1275 /* Either we are using fixed function or an ARB vertex program. In
1276 * either case the clip planes are going to be compared against
1277 * gl_Position (which is in clip coordinates) so we have to clip using
1278 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1281 return ctx
->Transform
._ClipUserPlane
;
1285 extern "C" const unsigned *
1286 brw_compile_tes(const struct brw_compiler
*compiler
,
1289 const struct brw_tes_prog_key
*key
,
1290 struct brw_tes_prog_data
*prog_data
,
1291 const nir_shader
*src_shader
,
1292 struct gl_shader_program
*shader_prog
,
1293 int shader_time_index
,
1294 unsigned *final_assembly_size
,
1297 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
1298 struct gl_shader
*shader
=
1299 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
];
1300 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1302 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1303 nir
->info
.inputs_read
= key
->inputs_read
;
1304 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1306 struct brw_vue_map input_vue_map
;
1307 brw_compute_tess_vue_map(&input_vue_map
,
1308 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
1309 nir
->info
.patch_inputs_read
);
1311 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
1312 brw_nir_lower_tes_inputs(nir
, &input_vue_map
);
1313 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1314 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
1316 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1317 nir
->info
.outputs_written
,
1318 nir
->info
.separate_shader
);
1320 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1322 assert(output_size_bytes
>= 1);
1323 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1325 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1329 /* URB entry sizes are stored as a multiple of 64 bytes. */
1330 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1332 bool need_patch_header
= nir
->info
.system_values_read
&
1333 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER
) |
1334 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER
));
1336 /* The TES will pull most inputs using URB read messages.
1338 * However, we push the patch header for TessLevel factors when required,
1339 * as it's a tiny amount of extra data.
1341 prog_data
->base
.urb_read_length
= need_patch_header
? 1 : 0;
1343 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1344 fprintf(stderr
, "TES Input ");
1345 brw_print_vue_map(stderr
, &input_vue_map
);
1346 fprintf(stderr
, "TES Output ");
1347 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1351 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1352 &prog_data
->base
.base
, shader
->Program
, nir
, 8,
1353 shader_time_index
, &input_vue_map
);
1356 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1360 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1362 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1363 &prog_data
->base
.base
, v
.promoted_constants
, false,
1364 MESA_SHADER_TESS_EVAL
);
1365 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1366 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1367 "%s tessellation evaluation shader %s",
1368 nir
->info
.label
? nir
->info
.label
1373 g
.generate_code(v
.cfg
, 8);
1375 return g
.get_assembly(final_assembly_size
);
1377 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1378 nir
, mem_ctx
, shader_time_index
);
1381 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1385 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1386 v
.dump_instructions();
1388 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1389 &prog_data
->base
, v
.cfg
,
1390 final_assembly_size
);