src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32
  33 extern "C" struct gl_shader *
  34 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  35 {
  36    struct brw_shader *shader;
  37
  38    shader = rzalloc(NULL, struct brw_shader);
  39    if (shader) {
  40       shader->base.Type = type;
  41       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  42       shader->base.Name = name;
  43       _mesa_init_shader(ctx, &shader->base);
  44    }
  45
  46    return &shader->base;
  47 }
  48
  49 extern "C" void
  50 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  51                       unsigned surf_index)
  52 {
  53    assert(surf_index < BRW_MAX_SURFACES);
  54
  55    prog_data->binding_table.size_bytes =
  56       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  57 }
  58
  59 enum brw_reg_type
  60 brw_type_for_base_type(const struct glsl_type *type)
  61 {
  62    switch (type->base_type) {
  63    case GLSL_TYPE_FLOAT:
  64       return BRW_REGISTER_TYPE_F;
  65    case GLSL_TYPE_INT:
  66    case GLSL_TYPE_BOOL:
  67    case GLSL_TYPE_SUBROUTINE:
  68       return BRW_REGISTER_TYPE_D;
  69    case GLSL_TYPE_UINT:
  70       return BRW_REGISTER_TYPE_UD;
  71    case GLSL_TYPE_ARRAY:
  72       return brw_type_for_base_type(type->fields.array);
  73    case GLSL_TYPE_STRUCT:
  74    case GLSL_TYPE_SAMPLER:
  75    case GLSL_TYPE_ATOMIC_UINT:
  76       /* These should be overridden with the type of the member when
  77        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  78        * way to trip up if we don't.
  79        */
  80       return BRW_REGISTER_TYPE_UD;
  81    case GLSL_TYPE_IMAGE:
  82       return BRW_REGISTER_TYPE_UD;
  83    case GLSL_TYPE_DOUBLE:
  84       return BRW_REGISTER_TYPE_DF;
  85    case GLSL_TYPE_VOID:
  86    case GLSL_TYPE_ERROR:
  87    case GLSL_TYPE_INTERFACE:
  88    case GLSL_TYPE_FUNCTION:
  89       unreachable("not reached");
  90    }
  91
  92    return BRW_REGISTER_TYPE_F;
  93 }
  94
  95 enum brw_conditional_mod
  96 brw_conditional_for_comparison(unsigned int op)
  97 {
  98    switch (op) {
  99    case ir_binop_less:
 100       return BRW_CONDITIONAL_L;
 101    case ir_binop_greater:
 102       return BRW_CONDITIONAL_G;
 103    case ir_binop_lequal:
 104       return BRW_CONDITIONAL_LE;
 105    case ir_binop_gequal:
 106       return BRW_CONDITIONAL_GE;
 107    case ir_binop_equal:
 108    case ir_binop_all_equal: /* same as equal for scalars */
 109       return BRW_CONDITIONAL_Z;
 110    case ir_binop_nequal:
 111    case ir_binop_any_nequal: /* same as nequal for scalars */
 112       return BRW_CONDITIONAL_NZ;
 113    default:
 114       unreachable("not reached: bad operation for comparison");
 115    }
 116 }
 117
 118 uint32_t
 119 brw_math_function(enum opcode op)
 120 {
 121    switch (op) {
 122    case SHADER_OPCODE_RCP:
 123       return BRW_MATH_FUNCTION_INV;
 124    case SHADER_OPCODE_RSQ:
 125       return BRW_MATH_FUNCTION_RSQ;
 126    case SHADER_OPCODE_SQRT:
 127       return BRW_MATH_FUNCTION_SQRT;
 128    case SHADER_OPCODE_EXP2:
 129       return BRW_MATH_FUNCTION_EXP;
 130    case SHADER_OPCODE_LOG2:
 131       return BRW_MATH_FUNCTION_LOG;
 132    case SHADER_OPCODE_POW:
 133       return BRW_MATH_FUNCTION_POW;
 134    case SHADER_OPCODE_SIN:
 135       return BRW_MATH_FUNCTION_SIN;
 136    case SHADER_OPCODE_COS:
 137       return BRW_MATH_FUNCTION_COS;
 138    case SHADER_OPCODE_INT_QUOTIENT:
 139       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 140    case SHADER_OPCODE_INT_REMAINDER:
 141       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 142    default:
 143       unreachable("not reached: unknown math function");
 144    }
 145 }
 146
 147 uint32_t
 148 brw_texture_offset(int *offsets, unsigned num_components)
 149 {
 150    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 151
 152    /* Combine all three offsets into a single unsigned dword:
 153     *
 154     *    bits 11:8 - U Offset (X component)
 155     *    bits  7:4 - V Offset (Y component)
 156     *    bits  3:0 - R Offset (Z component)
 157     */
 158    unsigned offset_bits = 0;
 159    for (unsigned i = 0; i < num_components; i++) {
 160       const unsigned shift = 4 * (2 - i);
 161       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 162    }
 163    return offset_bits;
 164 }
 165
 166 const char *
 167 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
 168 {
 169    switch (op) {
 170    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 171       assert(brw_opcode_desc(devinfo, op)->name);
 172       return brw_opcode_desc(devinfo, op)->name;
 173    case FS_OPCODE_FB_WRITE:
 174       return "fb_write";
 175    case FS_OPCODE_FB_WRITE_LOGICAL:
 176       return "fb_write_logical";
 177    case FS_OPCODE_PACK_STENCIL_REF:
 178       return "pack_stencil_ref";
 179    case FS_OPCODE_BLORP_FB_WRITE:
 180       return "blorp_fb_write";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183
 184    case SHADER_OPCODE_RCP:
 185       return "rcp";
 186    case SHADER_OPCODE_RSQ:
 187       return "rsq";
 188    case SHADER_OPCODE_SQRT:
 189       return "sqrt";
 190    case SHADER_OPCODE_EXP2:
 191       return "exp2";
 192    case SHADER_OPCODE_LOG2:
 193       return "log2";
 194    case SHADER_OPCODE_POW:
 195       return "pow";
 196    case SHADER_OPCODE_INT_QUOTIENT:
 197       return "int_quot";
 198    case SHADER_OPCODE_INT_REMAINDER:
 199       return "int_rem";
 200    case SHADER_OPCODE_SIN:
 201       return "sin";
 202    case SHADER_OPCODE_COS:
 203       return "cos";
 204
 205    case SHADER_OPCODE_TEX:
 206       return "tex";
 207    case SHADER_OPCODE_TEX_LOGICAL:
 208       return "tex_logical";
 209    case SHADER_OPCODE_TXD:
 210       return "txd";
 211    case SHADER_OPCODE_TXD_LOGICAL:
 212       return "txd_logical";
 213    case SHADER_OPCODE_TXF:
 214       return "txf";
 215    case SHADER_OPCODE_TXF_LOGICAL:
 216       return "txf_logical";
 217    case SHADER_OPCODE_TXL:
 218       return "txl";
 219    case SHADER_OPCODE_TXL_LOGICAL:
 220       return "txl_logical";
 221    case SHADER_OPCODE_TXS:
 222       return "txs";
 223    case SHADER_OPCODE_TXS_LOGICAL:
 224       return "txs_logical";
 225    case FS_OPCODE_TXB:
 226       return "txb";
 227    case FS_OPCODE_TXB_LOGICAL:
 228       return "txb_logical";
 229    case SHADER_OPCODE_TXF_CMS:
 230       return "txf_cms";
 231    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 232       return "txf_cms_logical";
 233    case SHADER_OPCODE_TXF_CMS_W:
 234       return "txf_cms_w";
 235    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 236       return "txf_cms_w_logical";
 237    case SHADER_OPCODE_TXF_UMS:
 238       return "txf_ums";
 239    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 240       return "txf_ums_logical";
 241    case SHADER_OPCODE_TXF_MCS:
 242       return "txf_mcs";
 243    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 244       return "txf_mcs_logical";
 245    case SHADER_OPCODE_LOD:
 246       return "lod";
 247    case SHADER_OPCODE_LOD_LOGICAL:
 248       return "lod_logical";
 249    case SHADER_OPCODE_TG4:
 250       return "tg4";
 251    case SHADER_OPCODE_TG4_LOGICAL:
 252       return "tg4_logical";
 253    case SHADER_OPCODE_TG4_OFFSET:
 254       return "tg4_offset";
 255    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 256       return "tg4_offset_logical";
 257    case SHADER_OPCODE_SAMPLEINFO:
 258       return "sampleinfo";
 259
 260    case SHADER_OPCODE_SHADER_TIME_ADD:
 261       return "shader_time_add";
 262
 263    case SHADER_OPCODE_UNTYPED_ATOMIC:
 264       return "untyped_atomic";
 265    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 266       return "untyped_atomic_logical";
 267    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 268       return "untyped_surface_read";
 269    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 270       return "untyped_surface_read_logical";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 272       return "untyped_surface_write";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 274       return "untyped_surface_write_logical";
 275    case SHADER_OPCODE_TYPED_ATOMIC:
 276       return "typed_atomic";
 277    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 278       return "typed_atomic_logical";
 279    case SHADER_OPCODE_TYPED_SURFACE_READ:
 280       return "typed_surface_read";
 281    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 282       return "typed_surface_read_logical";
 283    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 284       return "typed_surface_write";
 285    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 286       return "typed_surface_write_logical";
 287    case SHADER_OPCODE_MEMORY_FENCE:
 288       return "memory_fence";
 289
 290    case SHADER_OPCODE_LOAD_PAYLOAD:
 291       return "load_payload";
 292
 293    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 294       return "gen4_scratch_read";
 295    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 296       return "gen4_scratch_write";
 297    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 298       return "gen7_scratch_read";
 299    case SHADER_OPCODE_URB_WRITE_SIMD8:
 300       return "gen8_urb_write_simd8";
 301    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 302       return "gen8_urb_write_simd8_per_slot";
 303    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 304       return "gen8_urb_write_simd8_masked";
 305    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 306       return "gen8_urb_write_simd8_masked_per_slot";
 307    case SHADER_OPCODE_URB_READ_SIMD8:
 308       return "urb_read_simd8";
 309    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 310       return "urb_read_simd8_per_slot";
 311
 312    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 313       return "find_live_channel";
 314    case SHADER_OPCODE_BROADCAST:
 315       return "broadcast";
 316
 317    case SHADER_OPCODE_EXTRACT_BYTE:
 318       return "extract_byte";
 319    case SHADER_OPCODE_EXTRACT_WORD:
 320       return "extract_word";
 321    case VEC4_OPCODE_MOV_BYTES:
 322       return "mov_bytes";
 323    case VEC4_OPCODE_PACK_BYTES:
 324       return "pack_bytes";
 325    case VEC4_OPCODE_UNPACK_UNIFORM:
 326       return "unpack_uniform";
 327
 328    case FS_OPCODE_DDX_COARSE:
 329       return "ddx_coarse";
 330    case FS_OPCODE_DDX_FINE:
 331       return "ddx_fine";
 332    case FS_OPCODE_DDY_COARSE:
 333       return "ddy_coarse";
 334    case FS_OPCODE_DDY_FINE:
 335       return "ddy_fine";
 336
 337    case FS_OPCODE_CINTERP:
 338       return "cinterp";
 339    case FS_OPCODE_LINTERP:
 340       return "linterp";
 341
 342    case FS_OPCODE_PIXEL_X:
 343       return "pixel_x";
 344    case FS_OPCODE_PIXEL_Y:
 345       return "pixel_y";
 346
 347    case FS_OPCODE_GET_BUFFER_SIZE:
 348       return "fs_get_buffer_size";
 349
 350    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 351       return "uniform_pull_const";
 352    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 353       return "uniform_pull_const_gen7";
 354    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 355       return "varying_pull_const";
 356    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 357       return "varying_pull_const_gen7";
 358
 359    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 360       return "mov_dispatch_to_flags";
 361    case FS_OPCODE_DISCARD_JUMP:
 362       return "discard_jump";
 363
 364    case FS_OPCODE_SET_SAMPLE_ID:
 365       return "set_sample_id";
 366    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 367       return "set_simd4x2_offset";
 368
 369    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 370       return "pack_half_2x16_split";
 371    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 372       return "unpack_half_2x16_split_x";
 373    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 374       return "unpack_half_2x16_split_y";
 375
 376    case FS_OPCODE_PLACEHOLDER_HALT:
 377       return "placeholder_halt";
 378
 379    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 380       return "interp_centroid";
 381    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 382       return "interp_sample";
 383    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 384       return "interp_shared_offset";
 385    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 386       return "interp_per_slot_offset";
 387
 388    case VS_OPCODE_URB_WRITE:
 389       return "vs_urb_write";
 390    case VS_OPCODE_PULL_CONSTANT_LOAD:
 391       return "pull_constant_load";
 392    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 393       return "pull_constant_load_gen7";
 394
 395    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 396       return "set_simd4x2_header_gen9";
 397
 398    case VS_OPCODE_GET_BUFFER_SIZE:
 399       return "vs_get_buffer_size";
 400
 401    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 402       return "unpack_flags_simd4x2";
 403
 404    case GS_OPCODE_URB_WRITE:
 405       return "gs_urb_write";
 406    case GS_OPCODE_URB_WRITE_ALLOCATE:
 407       return "gs_urb_write_allocate";
 408    case GS_OPCODE_THREAD_END:
 409       return "gs_thread_end";
 410    case GS_OPCODE_SET_WRITE_OFFSET:
 411       return "set_write_offset";
 412    case GS_OPCODE_SET_VERTEX_COUNT:
 413       return "set_vertex_count";
 414    case GS_OPCODE_SET_DWORD_2:
 415       return "set_dword_2";
 416    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 417       return "prepare_channel_masks";
 418    case GS_OPCODE_SET_CHANNEL_MASKS:
 419       return "set_channel_masks";
 420    case GS_OPCODE_GET_INSTANCE_ID:
 421       return "get_instance_id";
 422    case GS_OPCODE_FF_SYNC:
 423       return "ff_sync";
 424    case GS_OPCODE_SET_PRIMITIVE_ID:
 425       return "set_primitive_id";
 426    case GS_OPCODE_SVB_WRITE:
 427       return "gs_svb_write";
 428    case GS_OPCODE_SVB_SET_DST_INDEX:
 429       return "gs_svb_set_dst_index";
 430    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 431       return "gs_ff_sync_set_primitives";
 432    case CS_OPCODE_CS_TERMINATE:
 433       return "cs_terminate";
 434    case SHADER_OPCODE_BARRIER:
 435       return "barrier";
 436    case SHADER_OPCODE_MULH:
 437       return "mulh";
 438    case SHADER_OPCODE_MOV_INDIRECT:
 439       return "mov_indirect";
 440
 441    case VEC4_OPCODE_URB_READ:
 442       return "urb_read";
 443    case TCS_OPCODE_GET_INSTANCE_ID:
 444       return "tcs_get_instance_id";
 445    case TCS_OPCODE_URB_WRITE:
 446       return "tcs_urb_write";
 447    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 448       return "tcs_set_input_urb_offsets";
 449    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 450       return "tcs_set_output_urb_offsets";
 451    case TCS_OPCODE_GET_PRIMITIVE_ID:
 452       return "tcs_get_primitive_id";
 453    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 454       return "tcs_create_barrier_header";
 455    case TCS_OPCODE_SRC0_010_IS_ZERO:
 456       return "tcs_src0<0,1,0>_is_zero";
 457    case TCS_OPCODE_RELEASE_INPUT:
 458       return "tcs_release_input";
 459    case TCS_OPCODE_THREAD_END:
 460       return "tcs_thread_end";
 461    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 462       return "tes_create_input_read_header";
 463    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 464       return "tes_add_indirect_urb_offset";
 465    case TES_OPCODE_GET_PRIMITIVE_ID:
 466       return "tes_get_primitive_id";
 467    }
 468
 469    unreachable("not reached");
 470 }
 471
 472 bool
 473 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 474 {
 475    union {
 476       unsigned ud;
 477       int d;
 478       float f;
 479       double df;
 480    } imm, sat_imm = { 0 };
 481
 482    const unsigned size = type_sz(type);
 483
 484    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 485     * irrelevant, so just check the size of the type and copy from/to an
 486     * appropriately sized field.
 487     */
 488    if (size < 8)
 489       imm.ud = reg->ud;
 490    else
 491       imm.df = reg->df;
 492
 493    switch (type) {
 494    case BRW_REGISTER_TYPE_UD:
 495    case BRW_REGISTER_TYPE_D:
 496    case BRW_REGISTER_TYPE_UW:
 497    case BRW_REGISTER_TYPE_W:
 498    case BRW_REGISTER_TYPE_UQ:
 499    case BRW_REGISTER_TYPE_Q:
 500       /* Nothing to do. */
 501       return false;
 502    case BRW_REGISTER_TYPE_F:
 503       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 504       break;
 505    case BRW_REGISTER_TYPE_DF:
 506       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 507       break;
 508    case BRW_REGISTER_TYPE_UB:
 509    case BRW_REGISTER_TYPE_B:
 510       unreachable("no UB/B immediates");
 511    case BRW_REGISTER_TYPE_V:
 512    case BRW_REGISTER_TYPE_UV:
 513    case BRW_REGISTER_TYPE_VF:
 514       unreachable("unimplemented: saturate vector immediate");
 515    case BRW_REGISTER_TYPE_HF:
 516       unreachable("unimplemented: saturate HF immediate");
 517    }
 518
 519    if (size < 8) {
 520       if (imm.ud != sat_imm.ud) {
 521          reg->ud = sat_imm.ud;
 522          return true;
 523       }
 524    } else {
 525       if (imm.df != sat_imm.df) {
 526          reg->df = sat_imm.df;
 527          return true;
 528       }
 529    }
 530    return false;
 531 }
 532
 533 bool
 534 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 535 {
 536    switch (type) {
 537    case BRW_REGISTER_TYPE_D:
 538    case BRW_REGISTER_TYPE_UD:
 539       reg->d = -reg->d;
 540       return true;
 541    case BRW_REGISTER_TYPE_W:
 542    case BRW_REGISTER_TYPE_UW:
 543       reg->d = -(int16_t)reg->ud;
 544       return true;
 545    case BRW_REGISTER_TYPE_F:
 546       reg->f = -reg->f;
 547       return true;
 548    case BRW_REGISTER_TYPE_VF:
 549       reg->ud ^= 0x80808080;
 550       return true;
 551    case BRW_REGISTER_TYPE_DF:
 552       reg->df = -reg->df;
 553       return true;
 554    case BRW_REGISTER_TYPE_UB:
 555    case BRW_REGISTER_TYPE_B:
 556       unreachable("no UB/B immediates");
 557    case BRW_REGISTER_TYPE_UV:
 558    case BRW_REGISTER_TYPE_V:
 559       assert(!"unimplemented: negate UV/V immediate");
 560    case BRW_REGISTER_TYPE_UQ:
 561    case BRW_REGISTER_TYPE_Q:
 562       assert(!"unimplemented: negate UQ/Q immediate");
 563    case BRW_REGISTER_TYPE_HF:
 564       assert(!"unimplemented: negate HF immediate");
 565    }
 566
 567    return false;
 568 }
 569
 570 bool
 571 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 572 {
 573    switch (type) {
 574    case BRW_REGISTER_TYPE_D:
 575       reg->d = abs(reg->d);
 576       return true;
 577    case BRW_REGISTER_TYPE_W:
 578       reg->d = abs((int16_t)reg->ud);
 579       return true;
 580    case BRW_REGISTER_TYPE_F:
 581       reg->f = fabsf(reg->f);
 582       return true;
 583    case BRW_REGISTER_TYPE_VF:
 584       reg->ud &= ~0x80808080;
 585       return true;
 586    case BRW_REGISTER_TYPE_UB:
 587    case BRW_REGISTER_TYPE_B:
 588       unreachable("no UB/B immediates");
 589    case BRW_REGISTER_TYPE_UQ:
 590    case BRW_REGISTER_TYPE_UD:
 591    case BRW_REGISTER_TYPE_UW:
 592    case BRW_REGISTER_TYPE_UV:
 593       /* Presumably the absolute value modifier on an unsigned source is a
 594        * nop, but it would be nice to confirm.
 595        */
 596       assert(!"unimplemented: abs unsigned immediate");
 597    case BRW_REGISTER_TYPE_V:
 598       assert(!"unimplemented: abs V immediate");
 599    case BRW_REGISTER_TYPE_Q:
 600       assert(!"unimplemented: abs Q immediate");
 601    case BRW_REGISTER_TYPE_DF:
 602    case BRW_REGISTER_TYPE_HF:
 603       assert(!"unimplemented: abs DF/HF immediate");
 604    }
 605
 606    return false;
 607 }
 608
 609 unsigned
 610 tesslevel_outer_components(GLenum tes_primitive_mode)
 611 {
 612    switch (tes_primitive_mode) {
 613    case GL_QUADS:
 614       return 4;
 615    case GL_TRIANGLES:
 616       return 3;
 617    case GL_ISOLINES:
 618       return 2;
 619    default:
 620       unreachable("Bogus tessellation domain");
 621    }
 622    return 0;
 623 }
 624
 625 unsigned
 626 tesslevel_inner_components(GLenum tes_primitive_mode)
 627 {
 628    switch (tes_primitive_mode) {
 629    case GL_QUADS:
 630       return 2;
 631    case GL_TRIANGLES:
 632       return 1;
 633    case GL_ISOLINES:
 634       return 0;
 635    default:
 636       unreachable("Bogus tessellation domain");
 637    }
 638    return 0;
 639 }
 640
 641 /**
 642  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 643  * that's stored backwards, i.e. .wzyx.
 644  */
 645 unsigned
 646 writemask_for_backwards_vector(unsigned mask)
 647 {
 648    unsigned new_mask = 0;
 649
 650    for (int i = 0; i < 4; i++)
 651       new_mask |= ((mask >> i) & 1) << (3 - i);
 652
 653    return new_mask;
 654 }
 655
 656 backend_shader::backend_shader(const struct brw_compiler *compiler,
 657                                void *log_data,
 658                                void *mem_ctx,
 659                                const nir_shader *shader,
 660                                struct brw_stage_prog_data *stage_prog_data)
 661    : compiler(compiler),
 662      log_data(log_data),
 663      devinfo(compiler->devinfo),
 664      nir(shader),
 665      stage_prog_data(stage_prog_data),
 666      mem_ctx(mem_ctx),
 667      cfg(NULL),
 668      stage(shader->stage)
 669 {
 670    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 671    stage_name = _mesa_shader_stage_to_string(stage);
 672    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 673    is_passthrough_shader =
 674       nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
 675 }
 676
 677 bool
 678 backend_reg::equals(const backend_reg &r) const
 679 {
 680    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 681           reg_offset == r.reg_offset;
 682 }
 683
 684 bool
 685 backend_reg::is_zero() const
 686 {
 687    if (file != IMM)
 688       return false;
 689
 690    switch (type) {
 691    case BRW_REGISTER_TYPE_F:
 692       return f == 0;
 693    case BRW_REGISTER_TYPE_DF:
 694       return df == 0;
 695    case BRW_REGISTER_TYPE_D:
 696    case BRW_REGISTER_TYPE_UD:
 697       return d == 0;
 698    default:
 699       return false;
 700    }
 701 }
 702
 703 bool
 704 backend_reg::is_one() const
 705 {
 706    if (file != IMM)
 707       return false;
 708
 709    switch (type) {
 710    case BRW_REGISTER_TYPE_F:
 711       return f == 1.0f;
 712    case BRW_REGISTER_TYPE_DF:
 713       return df == 1.0;
 714    case BRW_REGISTER_TYPE_D:
 715    case BRW_REGISTER_TYPE_UD:
 716       return d == 1;
 717    default:
 718       return false;
 719    }
 720 }
 721
 722 bool
 723 backend_reg::is_negative_one() const
 724 {
 725    if (file != IMM)
 726       return false;
 727
 728    switch (type) {
 729    case BRW_REGISTER_TYPE_F:
 730       return f == -1.0;
 731    case BRW_REGISTER_TYPE_DF:
 732       return df == -1.0;
 733    case BRW_REGISTER_TYPE_D:
 734       return d == -1;
 735    default:
 736       return false;
 737    }
 738 }
 739
 740 bool
 741 backend_reg::is_null() const
 742 {
 743    return file == ARF && nr == BRW_ARF_NULL;
 744 }
 745
 746
 747 bool
 748 backend_reg::is_accumulator() const
 749 {
 750    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 751 }
 752
 753 bool
 754 backend_reg::in_range(const backend_reg &r, unsigned n) const
 755 {
 756    return (file == r.file &&
 757            nr == r.nr &&
 758            reg_offset >= r.reg_offset &&
 759            reg_offset < r.reg_offset + n);
 760 }
 761
 762 bool
 763 backend_instruction::is_commutative() const
 764 {
 765    switch (opcode) {
 766    case BRW_OPCODE_AND:
 767    case BRW_OPCODE_OR:
 768    case BRW_OPCODE_XOR:
 769    case BRW_OPCODE_ADD:
 770    case BRW_OPCODE_MUL:
 771    case SHADER_OPCODE_MULH:
 772       return true;
 773    case BRW_OPCODE_SEL:
 774       /* MIN and MAX are commutative. */
 775       if (conditional_mod == BRW_CONDITIONAL_GE ||
 776           conditional_mod == BRW_CONDITIONAL_L) {
 777          return true;
 778       }
 779       /* fallthrough */
 780    default:
 781       return false;
 782    }
 783 }
 784
 785 bool
 786 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
 787 {
 788    return ::is_3src(devinfo, opcode);
 789 }
 790
 791 bool
 792 backend_instruction::is_tex() const
 793 {
 794    return (opcode == SHADER_OPCODE_TEX ||
 795            opcode == FS_OPCODE_TXB ||
 796            opcode == SHADER_OPCODE_TXD ||
 797            opcode == SHADER_OPCODE_TXF ||
 798            opcode == SHADER_OPCODE_TXF_CMS ||
 799            opcode == SHADER_OPCODE_TXF_CMS_W ||
 800            opcode == SHADER_OPCODE_TXF_UMS ||
 801            opcode == SHADER_OPCODE_TXF_MCS ||
 802            opcode == SHADER_OPCODE_TXL ||
 803            opcode == SHADER_OPCODE_TXS ||
 804            opcode == SHADER_OPCODE_LOD ||
 805            opcode == SHADER_OPCODE_TG4 ||
 806            opcode == SHADER_OPCODE_TG4_OFFSET ||
 807            opcode == SHADER_OPCODE_SAMPLEINFO);
 808 }
 809
 810 bool
 811 backend_instruction::is_math() const
 812 {
 813    return (opcode == SHADER_OPCODE_RCP ||
 814            opcode == SHADER_OPCODE_RSQ ||
 815            opcode == SHADER_OPCODE_SQRT ||
 816            opcode == SHADER_OPCODE_EXP2 ||
 817            opcode == SHADER_OPCODE_LOG2 ||
 818            opcode == SHADER_OPCODE_SIN ||
 819            opcode == SHADER_OPCODE_COS ||
 820            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 821            opcode == SHADER_OPCODE_INT_REMAINDER ||
 822            opcode == SHADER_OPCODE_POW);
 823 }
 824
 825 bool
 826 backend_instruction::is_control_flow() const
 827 {
 828    switch (opcode) {
 829    case BRW_OPCODE_DO:
 830    case BRW_OPCODE_WHILE:
 831    case BRW_OPCODE_IF:
 832    case BRW_OPCODE_ELSE:
 833    case BRW_OPCODE_ENDIF:
 834    case BRW_OPCODE_BREAK:
 835    case BRW_OPCODE_CONTINUE:
 836       return true;
 837    default:
 838       return false;
 839    }
 840 }
 841
 842 bool
 843 backend_instruction::can_do_source_mods() const
 844 {
 845    switch (opcode) {
 846    case BRW_OPCODE_ADDC:
 847    case BRW_OPCODE_BFE:
 848    case BRW_OPCODE_BFI1:
 849    case BRW_OPCODE_BFI2:
 850    case BRW_OPCODE_BFREV:
 851    case BRW_OPCODE_CBIT:
 852    case BRW_OPCODE_FBH:
 853    case BRW_OPCODE_FBL:
 854    case BRW_OPCODE_SUBB:
 855       return false;
 856    default:
 857       return true;
 858    }
 859 }
 860
 861 bool
 862 backend_instruction::can_do_saturate() const
 863 {
 864    switch (opcode) {
 865    case BRW_OPCODE_ADD:
 866    case BRW_OPCODE_ASR:
 867    case BRW_OPCODE_AVG:
 868    case BRW_OPCODE_DP2:
 869    case BRW_OPCODE_DP3:
 870    case BRW_OPCODE_DP4:
 871    case BRW_OPCODE_DPH:
 872    case BRW_OPCODE_F16TO32:
 873    case BRW_OPCODE_F32TO16:
 874    case BRW_OPCODE_LINE:
 875    case BRW_OPCODE_LRP:
 876    case BRW_OPCODE_MAC:
 877    case BRW_OPCODE_MAD:
 878    case BRW_OPCODE_MATH:
 879    case BRW_OPCODE_MOV:
 880    case BRW_OPCODE_MUL:
 881    case SHADER_OPCODE_MULH:
 882    case BRW_OPCODE_PLN:
 883    case BRW_OPCODE_RNDD:
 884    case BRW_OPCODE_RNDE:
 885    case BRW_OPCODE_RNDU:
 886    case BRW_OPCODE_RNDZ:
 887    case BRW_OPCODE_SEL:
 888    case BRW_OPCODE_SHL:
 889    case BRW_OPCODE_SHR:
 890    case FS_OPCODE_LINTERP:
 891    case SHADER_OPCODE_COS:
 892    case SHADER_OPCODE_EXP2:
 893    case SHADER_OPCODE_LOG2:
 894    case SHADER_OPCODE_POW:
 895    case SHADER_OPCODE_RCP:
 896    case SHADER_OPCODE_RSQ:
 897    case SHADER_OPCODE_SIN:
 898    case SHADER_OPCODE_SQRT:
 899       return true;
 900    default:
 901       return false;
 902    }
 903 }
 904
 905 bool
 906 backend_instruction::can_do_cmod() const
 907 {
 908    switch (opcode) {
 909    case BRW_OPCODE_ADD:
 910    case BRW_OPCODE_ADDC:
 911    case BRW_OPCODE_AND:
 912    case BRW_OPCODE_ASR:
 913    case BRW_OPCODE_AVG:
 914    case BRW_OPCODE_CMP:
 915    case BRW_OPCODE_CMPN:
 916    case BRW_OPCODE_DP2:
 917    case BRW_OPCODE_DP3:
 918    case BRW_OPCODE_DP4:
 919    case BRW_OPCODE_DPH:
 920    case BRW_OPCODE_F16TO32:
 921    case BRW_OPCODE_F32TO16:
 922    case BRW_OPCODE_FRC:
 923    case BRW_OPCODE_LINE:
 924    case BRW_OPCODE_LRP:
 925    case BRW_OPCODE_LZD:
 926    case BRW_OPCODE_MAC:
 927    case BRW_OPCODE_MACH:
 928    case BRW_OPCODE_MAD:
 929    case BRW_OPCODE_MOV:
 930    case BRW_OPCODE_MUL:
 931    case BRW_OPCODE_NOT:
 932    case BRW_OPCODE_OR:
 933    case BRW_OPCODE_PLN:
 934    case BRW_OPCODE_RNDD:
 935    case BRW_OPCODE_RNDE:
 936    case BRW_OPCODE_RNDU:
 937    case BRW_OPCODE_RNDZ:
 938    case BRW_OPCODE_SAD2:
 939    case BRW_OPCODE_SADA2:
 940    case BRW_OPCODE_SHL:
 941    case BRW_OPCODE_SHR:
 942    case BRW_OPCODE_SUBB:
 943    case BRW_OPCODE_XOR:
 944    case FS_OPCODE_CINTERP:
 945    case FS_OPCODE_LINTERP:
 946       return true;
 947    default:
 948       return false;
 949    }
 950 }
 951
 952 bool
 953 backend_instruction::reads_accumulator_implicitly() const
 954 {
 955    switch (opcode) {
 956    case BRW_OPCODE_MAC:
 957    case BRW_OPCODE_MACH:
 958    case BRW_OPCODE_SADA2:
 959       return true;
 960    default:
 961       return false;
 962    }
 963 }
 964
 965 bool
 966 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 967 {
 968    return writes_accumulator ||
 969           (devinfo->gen < 6 &&
 970            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 971             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 972              opcode != FS_OPCODE_CINTERP)));
 973 }
 974
 975 bool
 976 backend_instruction::has_side_effects() const
 977 {
 978    switch (opcode) {
 979    case SHADER_OPCODE_UNTYPED_ATOMIC:
 980    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 981    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 982    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 983    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 984    case SHADER_OPCODE_TYPED_ATOMIC:
 985    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 986    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 987    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 988    case SHADER_OPCODE_MEMORY_FENCE:
 989    case SHADER_OPCODE_URB_WRITE_SIMD8:
 990    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 991    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 992    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 993    case FS_OPCODE_FB_WRITE:
 994    case SHADER_OPCODE_BARRIER:
 995    case TCS_OPCODE_URB_WRITE:
 996    case TCS_OPCODE_RELEASE_INPUT:
 997       return true;
 998    default:
 999       return false;
1000    }
1001 }
1002
1003 bool
1004 backend_instruction::is_volatile() const
1005 {
1006    switch (opcode) {
1007    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1008    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1009    case SHADER_OPCODE_TYPED_SURFACE_READ:
1010    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1011    case SHADER_OPCODE_URB_READ_SIMD8:
1012    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1013    case VEC4_OPCODE_URB_READ:
1014       return true;
1015    default:
1016       return false;
1017    }
1018 }
1019
1020 #ifndef NDEBUG
1021 static bool
1022 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1023 {
1024    bool found = false;
1025    foreach_inst_in_block (backend_instruction, i, block) {
1026       if (inst == i) {
1027          found = true;
1028       }
1029    }
1030    return found;
1031 }
1032 #endif
1033
1034 static void
1035 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1036 {
1037    for (bblock_t *block_iter = start_block->next();
1038         block_iter;
1039         block_iter = block_iter->next()) {
1040       block_iter->start_ip += ip_adjustment;
1041       block_iter->end_ip += ip_adjustment;
1042    }
1043 }
1044
1045 void
1046 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1047 {
1048    assert(this != inst);
1049
1050    if (!this->is_head_sentinel())
1051       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1052
1053    block->end_ip++;
1054
1055    adjust_later_block_ips(block, 1);
1056
1057    exec_node::insert_after(inst);
1058 }
1059
1060 void
1061 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1062 {
1063    assert(this != inst);
1064
1065    if (!this->is_tail_sentinel())
1066       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1067
1068    block->end_ip++;
1069
1070    adjust_later_block_ips(block, 1);
1071
1072    exec_node::insert_before(inst);
1073 }
1074
1075 void
1076 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1077 {
1078    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1079
1080    unsigned num_inst = list->length();
1081
1082    block->end_ip += num_inst;
1083
1084    adjust_later_block_ips(block, num_inst);
1085
1086    exec_node::insert_before(list);
1087 }
1088
1089 void
1090 backend_instruction::remove(bblock_t *block)
1091 {
1092    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1093
1094    adjust_later_block_ips(block, -1);
1095
1096    if (block->start_ip == block->end_ip) {
1097       block->cfg->remove_block(block);
1098    } else {
1099       block->end_ip--;
1100    }
1101
1102    exec_node::remove();
1103 }
1104
1105 void
1106 backend_shader::dump_instructions()
1107 {
1108    dump_instructions(NULL);
1109 }
1110
1111 void
1112 backend_shader::dump_instructions(const char *name)
1113 {
1114    FILE *file = stderr;
1115    if (name && geteuid() != 0) {
1116       file = fopen(name, "w");
1117       if (!file)
1118          file = stderr;
1119    }
1120
1121    if (cfg) {
1122       int ip = 0;
1123       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1124          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1125             fprintf(file, "%4d: ", ip++);
1126          dump_instruction(inst, file);
1127       }
1128    } else {
1129       int ip = 0;
1130       foreach_in_list(backend_instruction, inst, &instructions) {
1131          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1132             fprintf(file, "%4d: ", ip++);
1133          dump_instruction(inst, file);
1134       }
1135    }
1136
1137    if (file != stderr) {
1138       fclose(file);
1139    }
1140 }
1141
1142 void
1143 backend_shader::calculate_cfg()
1144 {
1145    if (this->cfg)
1146       return;
1147    cfg = new(mem_ctx) cfg_t(&this->instructions);
1148 }
1149
1150 /**
1151  * Sets up the starting offsets for the groups of binding table entries
1152  * commong to all pipeline stages.
1153  *
1154  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1155  * unused but also make sure that addition of small offsets to them will
1156  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1157  */
1158 void
1159 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1160                                         const struct brw_device_info *devinfo,
1161                                         const struct gl_shader_program *shader_prog,
1162                                         const struct gl_program *prog,
1163                                         struct brw_stage_prog_data *stage_prog_data,
1164                                         uint32_t next_binding_table_offset)
1165 {
1166    const struct gl_shader *shader = NULL;
1167    int num_textures = _mesa_fls(prog->SamplersUsed);
1168
1169    if (shader_prog)
1170       shader = shader_prog->_LinkedShaders[stage];
1171
1172    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1173    next_binding_table_offset += num_textures;
1174
1175    if (shader) {
1176       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1177       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1178       next_binding_table_offset += shader->NumUniformBlocks;
1179
1180       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1181       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1182       next_binding_table_offset += shader->NumShaderStorageBlocks;
1183    } else {
1184       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1185       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1186    }
1187
1188    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1189       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1190       next_binding_table_offset++;
1191    } else {
1192       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1193    }
1194
1195    if (prog->UsesGather) {
1196       if (devinfo->gen >= 8) {
1197          stage_prog_data->binding_table.gather_texture_start =
1198             stage_prog_data->binding_table.texture_start;
1199       } else {
1200          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1201          next_binding_table_offset += num_textures;
1202       }
1203    } else {
1204       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1205    }
1206
1207    if (shader && shader->NumAtomicBuffers) {
1208       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1209       next_binding_table_offset += shader->NumAtomicBuffers;
1210    } else {
1211       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1212    }
1213
1214    if (shader && shader->NumImages) {
1215       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1216       next_binding_table_offset += shader->NumImages;
1217    } else {
1218       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1219    }
1220
1221    /* This may or may not be used depending on how the compile goes. */
1222    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1223    next_binding_table_offset++;
1224
1225    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1226
1227    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1228 }
1229
1230 static void
1231 setup_vec4_uniform_value(const gl_constant_value **params,
1232                          const gl_constant_value *values,
1233                          unsigned n)
1234 {
1235    static const gl_constant_value zero = { 0 };
1236
1237    for (unsigned i = 0; i < n; ++i)
1238       params[i] = &values[i];
1239
1240    for (unsigned i = n; i < 4; ++i)
1241       params[i] = &zero;
1242 }
1243
1244 void
1245 brw_setup_image_uniform_values(gl_shader_stage stage,
1246                                struct brw_stage_prog_data *stage_prog_data,
1247                                unsigned param_start_index,
1248                                const gl_uniform_storage *storage)
1249 {
1250    const gl_constant_value **param =
1251       &stage_prog_data->param[param_start_index];
1252
1253    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1254       const unsigned image_idx = storage->opaque[stage].index + i;
1255       const brw_image_param *image_param =
1256          &stage_prog_data->image_param[image_idx];
1257
1258       /* Upload the brw_image_param structure.  The order is expected to match
1259        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1260        */
1261       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1262          (const gl_constant_value *)&image_param->surface_idx, 1);
1263       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1264          (const gl_constant_value *)image_param->offset, 2);
1265       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1266          (const gl_constant_value *)image_param->size, 3);
1267       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1268          (const gl_constant_value *)image_param->stride, 4);
1269       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1270          (const gl_constant_value *)image_param->tiling, 3);
1271       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1272          (const gl_constant_value *)image_param->swizzling, 2);
1273       param += BRW_IMAGE_PARAM_SIZE;
1274
1275       brw_mark_surface_used(
1276          stage_prog_data,
1277          stage_prog_data->binding_table.image_start + image_idx);
1278    }
1279 }
1280
1281 /**
1282  * Decide which set of clip planes should be used when clipping via
1283  * gl_Position or gl_ClipVertex.
1284  */
1285 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1286 {
1287    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1288       /* There is currently a GLSL vertex shader, so clip according to GLSL
1289        * rules, which means compare gl_ClipVertex (or gl_Position, if
1290        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1291        * that were stored in EyeUserPlane at the time the clip planes were
1292        * specified.
1293        */
1294       return ctx->Transform.EyeUserPlane;
1295    } else {
1296       /* Either we are using fixed function or an ARB vertex program.  In
1297        * either case the clip planes are going to be compared against
1298        * gl_Position (which is in clip coordinates) so we have to clip using
1299        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1300        * core.
1301        */
1302       return ctx->Transform._ClipUserPlane;
1303    }
1304 }
1305
1306 extern "C" const unsigned *
1307 brw_compile_tes(const struct brw_compiler *compiler,
1308                 void *log_data,
1309                 void *mem_ctx,
1310                 const struct brw_tes_prog_key *key,
1311                 struct brw_tes_prog_data *prog_data,
1312                 const nir_shader *src_shader,
1313                 struct gl_shader_program *shader_prog,
1314                 int shader_time_index,
1315                 unsigned *final_assembly_size,
1316                 char **error_str)
1317 {
1318    const struct brw_device_info *devinfo = compiler->devinfo;
1319    struct gl_shader *shader =
1320       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1321    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1322
1323    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1324    nir->info.inputs_read = key->inputs_read;
1325    nir->info.patch_inputs_read = key->patch_inputs_read;
1326
1327    struct brw_vue_map input_vue_map;
1328    brw_compute_tess_vue_map(&input_vue_map,
1329                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1330                             nir->info.patch_inputs_read);
1331
1332    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1333    brw_nir_lower_tes_inputs(nir, &input_vue_map);
1334    brw_nir_lower_vue_outputs(nir, is_scalar);
1335    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1336
1337    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1338                        nir->info.outputs_written,
1339                        nir->info.separate_shader);
1340
1341    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1342
1343    assert(output_size_bytes >= 1);
1344    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1345       if (error_str)
1346          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1347       return NULL;
1348    }
1349
1350    /* URB entry sizes are stored as a multiple of 64 bytes. */
1351    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1352
1353    bool need_patch_header = nir->info.system_values_read &
1354       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1355        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1356
1357    /* The TES will pull most inputs using URB read messages.
1358     *
1359     * However, we push the patch header for TessLevel factors when required,
1360     * as it's a tiny amount of extra data.
1361     */
1362    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1363
1364    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1365       fprintf(stderr, "TES Input ");
1366       brw_print_vue_map(stderr, &input_vue_map);
1367       fprintf(stderr, "TES Output ");
1368       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1369    }
1370
1371    if (is_scalar) {
1372       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1373                    &prog_data->base.base, shader->Program, nir, 8,
1374                    shader_time_index, &input_vue_map);
1375       if (!v.run_tes()) {
1376          if (error_str)
1377             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1378          return NULL;
1379       }
1380
1381       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1382
1383       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1384                      &prog_data->base.base, v.promoted_constants, false,
1385                      MESA_SHADER_TESS_EVAL);
1386       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1387          g.enable_debug(ralloc_asprintf(mem_ctx,
1388                                         "%s tessellation evaluation shader %s",
1389                                         nir->info.label ? nir->info.label
1390                                                         : "unnamed",
1391                                         nir->info.name));
1392       }
1393
1394       g.generate_code(v.cfg, 8);
1395
1396       return g.get_assembly(final_assembly_size);
1397    } else {
1398       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1399                               nir, mem_ctx, shader_time_index);
1400       if (!v.run()) {
1401          if (error_str)
1402             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1403          return NULL;
1404       }
1405
1406       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1407          v.dump_instructions();
1408
1409       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1410                                         &prog_data->base, v.cfg,
1411                                         final_assembly_size);
1412    }
1413 }