i965: Handle BRW_OPCODE_DO on Gen6+ in brw_instruction_name().
[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_cfg.h"
26 #include "brw_eu.h"
27 #include "brw_fs.h"
28 #include "brw_nir.h"
29 #include "brw_vec4_tes.h"
30 #include "main/shaderobj.h"
31 #include "main/uniforms.h"
32
33 extern "C" struct gl_shader *
34 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
35 {
36 struct brw_shader *shader;
37
38 shader = rzalloc(NULL, struct brw_shader);
39 if (shader) {
40 shader->base.Type = type;
41 shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
42 shader->base.Name = name;
43 _mesa_init_shader(ctx, &shader->base);
44 }
45
46 return &shader->base;
47 }
48
49 extern "C" void
50 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
51 unsigned surf_index)
52 {
53 assert(surf_index < BRW_MAX_SURFACES);
54
55 prog_data->binding_table.size_bytes =
56 MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
57 }
58
59 enum brw_reg_type
60 brw_type_for_base_type(const struct glsl_type *type)
61 {
62 switch (type->base_type) {
63 case GLSL_TYPE_FLOAT:
64 return BRW_REGISTER_TYPE_F;
65 case GLSL_TYPE_INT:
66 case GLSL_TYPE_BOOL:
67 case GLSL_TYPE_SUBROUTINE:
68 return BRW_REGISTER_TYPE_D;
69 case GLSL_TYPE_UINT:
70 return BRW_REGISTER_TYPE_UD;
71 case GLSL_TYPE_ARRAY:
72 return brw_type_for_base_type(type->fields.array);
73 case GLSL_TYPE_STRUCT:
74 case GLSL_TYPE_SAMPLER:
75 case GLSL_TYPE_ATOMIC_UINT:
76 /* These should be overridden with the type of the member when
77 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
78 * way to trip up if we don't.
79 */
80 return BRW_REGISTER_TYPE_UD;
81 case GLSL_TYPE_IMAGE:
82 return BRW_REGISTER_TYPE_UD;
83 case GLSL_TYPE_DOUBLE:
84 return BRW_REGISTER_TYPE_DF;
85 case GLSL_TYPE_VOID:
86 case GLSL_TYPE_ERROR:
87 case GLSL_TYPE_INTERFACE:
88 case GLSL_TYPE_FUNCTION:
89 unreachable("not reached");
90 }
91
92 return BRW_REGISTER_TYPE_F;
93 }
94
95 enum brw_conditional_mod
96 brw_conditional_for_comparison(unsigned int op)
97 {
98 switch (op) {
99 case ir_binop_less:
100 return BRW_CONDITIONAL_L;
101 case ir_binop_greater:
102 return BRW_CONDITIONAL_G;
103 case ir_binop_lequal:
104 return BRW_CONDITIONAL_LE;
105 case ir_binop_gequal:
106 return BRW_CONDITIONAL_GE;
107 case ir_binop_equal:
108 case ir_binop_all_equal: /* same as equal for scalars */
109 return BRW_CONDITIONAL_Z;
110 case ir_binop_nequal:
111 case ir_binop_any_nequal: /* same as nequal for scalars */
112 return BRW_CONDITIONAL_NZ;
113 default:
114 unreachable("not reached: bad operation for comparison");
115 }
116 }
117
118 uint32_t
119 brw_math_function(enum opcode op)
120 {
121 switch (op) {
122 case SHADER_OPCODE_RCP:
123 return BRW_MATH_FUNCTION_INV;
124 case SHADER_OPCODE_RSQ:
125 return BRW_MATH_FUNCTION_RSQ;
126 case SHADER_OPCODE_SQRT:
127 return BRW_MATH_FUNCTION_SQRT;
128 case SHADER_OPCODE_EXP2:
129 return BRW_MATH_FUNCTION_EXP;
130 case SHADER_OPCODE_LOG2:
131 return BRW_MATH_FUNCTION_LOG;
132 case SHADER_OPCODE_POW:
133 return BRW_MATH_FUNCTION_POW;
134 case SHADER_OPCODE_SIN:
135 return BRW_MATH_FUNCTION_SIN;
136 case SHADER_OPCODE_COS:
137 return BRW_MATH_FUNCTION_COS;
138 case SHADER_OPCODE_INT_QUOTIENT:
139 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
140 case SHADER_OPCODE_INT_REMAINDER:
141 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
142 default:
143 unreachable("not reached: unknown math function");
144 }
145 }
146
147 uint32_t
148 brw_texture_offset(int *offsets, unsigned num_components)
149 {
150 if (!offsets) return 0; /* nonconstant offset; caller will handle it. */
151
152 /* Combine all three offsets into a single unsigned dword:
153 *
154 * bits 11:8 - U Offset (X component)
155 * bits 7:4 - V Offset (Y component)
156 * bits 3:0 - R Offset (Z component)
157 */
158 unsigned offset_bits = 0;
159 for (unsigned i = 0; i < num_components; i++) {
160 const unsigned shift = 4 * (2 - i);
161 offset_bits |= (offsets[i] << shift) & (0xF << shift);
162 }
163 return offset_bits;
164 }
165
166 const char *
167 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
168 {
169 switch (op) {
170 case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
171 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
172 * start of a loop in the IR.
173 */
174 if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
175 return "do";
176
177 assert(brw_opcode_desc(devinfo, op)->name);
178 return brw_opcode_desc(devinfo, op)->name;
179 case FS_OPCODE_FB_WRITE:
180 return "fb_write";
181 case FS_OPCODE_FB_WRITE_LOGICAL:
182 return "fb_write_logical";
183 case FS_OPCODE_PACK_STENCIL_REF:
184 return "pack_stencil_ref";
185 case FS_OPCODE_BLORP_FB_WRITE:
186 return "blorp_fb_write";
187 case FS_OPCODE_REP_FB_WRITE:
188 return "rep_fb_write";
189
190 case SHADER_OPCODE_RCP:
191 return "rcp";
192 case SHADER_OPCODE_RSQ:
193 return "rsq";
194 case SHADER_OPCODE_SQRT:
195 return "sqrt";
196 case SHADER_OPCODE_EXP2:
197 return "exp2";
198 case SHADER_OPCODE_LOG2:
199 return "log2";
200 case SHADER_OPCODE_POW:
201 return "pow";
202 case SHADER_OPCODE_INT_QUOTIENT:
203 return "int_quot";
204 case SHADER_OPCODE_INT_REMAINDER:
205 return "int_rem";
206 case SHADER_OPCODE_SIN:
207 return "sin";
208 case SHADER_OPCODE_COS:
209 return "cos";
210
211 case SHADER_OPCODE_TEX:
212 return "tex";
213 case SHADER_OPCODE_TEX_LOGICAL:
214 return "tex_logical";
215 case SHADER_OPCODE_TXD:
216 return "txd";
217 case SHADER_OPCODE_TXD_LOGICAL:
218 return "txd_logical";
219 case SHADER_OPCODE_TXF:
220 return "txf";
221 case SHADER_OPCODE_TXF_LOGICAL:
222 return "txf_logical";
223 case SHADER_OPCODE_TXL:
224 return "txl";
225 case SHADER_OPCODE_TXL_LOGICAL:
226 return "txl_logical";
227 case SHADER_OPCODE_TXS:
228 return "txs";
229 case SHADER_OPCODE_TXS_LOGICAL:
230 return "txs_logical";
231 case FS_OPCODE_TXB:
232 return "txb";
233 case FS_OPCODE_TXB_LOGICAL:
234 return "txb_logical";
235 case SHADER_OPCODE_TXF_CMS:
236 return "txf_cms";
237 case SHADER_OPCODE_TXF_CMS_LOGICAL:
238 return "txf_cms_logical";
239 case SHADER_OPCODE_TXF_CMS_W:
240 return "txf_cms_w";
241 case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
242 return "txf_cms_w_logical";
243 case SHADER_OPCODE_TXF_UMS:
244 return "txf_ums";
245 case SHADER_OPCODE_TXF_UMS_LOGICAL:
246 return "txf_ums_logical";
247 case SHADER_OPCODE_TXF_MCS:
248 return "txf_mcs";
249 case SHADER_OPCODE_TXF_MCS_LOGICAL:
250 return "txf_mcs_logical";
251 case SHADER_OPCODE_LOD:
252 return "lod";
253 case SHADER_OPCODE_LOD_LOGICAL:
254 return "lod_logical";
255 case SHADER_OPCODE_TG4:
256 return "tg4";
257 case SHADER_OPCODE_TG4_LOGICAL:
258 return "tg4_logical";
259 case SHADER_OPCODE_TG4_OFFSET:
260 return "tg4_offset";
261 case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
262 return "tg4_offset_logical";
263 case SHADER_OPCODE_SAMPLEINFO:
264 return "sampleinfo";
265
266 case SHADER_OPCODE_SHADER_TIME_ADD:
267 return "shader_time_add";
268
269 case SHADER_OPCODE_UNTYPED_ATOMIC:
270 return "untyped_atomic";
271 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
272 return "untyped_atomic_logical";
273 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
274 return "untyped_surface_read";
275 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
276 return "untyped_surface_read_logical";
277 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
278 return "untyped_surface_write";
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
280 return "untyped_surface_write_logical";
281 case SHADER_OPCODE_TYPED_ATOMIC:
282 return "typed_atomic";
283 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
284 return "typed_atomic_logical";
285 case SHADER_OPCODE_TYPED_SURFACE_READ:
286 return "typed_surface_read";
287 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
288 return "typed_surface_read_logical";
289 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
290 return "typed_surface_write";
291 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
292 return "typed_surface_write_logical";
293 case SHADER_OPCODE_MEMORY_FENCE:
294 return "memory_fence";
295
296 case SHADER_OPCODE_LOAD_PAYLOAD:
297 return "load_payload";
298 case FS_OPCODE_PACK:
299 return "pack";
300
301 case SHADER_OPCODE_GEN4_SCRATCH_READ:
302 return "gen4_scratch_read";
303 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
304 return "gen4_scratch_write";
305 case SHADER_OPCODE_GEN7_SCRATCH_READ:
306 return "gen7_scratch_read";
307 case SHADER_OPCODE_URB_WRITE_SIMD8:
308 return "gen8_urb_write_simd8";
309 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
310 return "gen8_urb_write_simd8_per_slot";
311 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
312 return "gen8_urb_write_simd8_masked";
313 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
314 return "gen8_urb_write_simd8_masked_per_slot";
315 case SHADER_OPCODE_URB_READ_SIMD8:
316 return "urb_read_simd8";
317 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
318 return "urb_read_simd8_per_slot";
319
320 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
321 return "find_live_channel";
322 case SHADER_OPCODE_BROADCAST:
323 return "broadcast";
324
325 case SHADER_OPCODE_EXTRACT_BYTE:
326 return "extract_byte";
327 case SHADER_OPCODE_EXTRACT_WORD:
328 return "extract_word";
329 case VEC4_OPCODE_MOV_BYTES:
330 return "mov_bytes";
331 case VEC4_OPCODE_PACK_BYTES:
332 return "pack_bytes";
333 case VEC4_OPCODE_UNPACK_UNIFORM:
334 return "unpack_uniform";
335
336 case FS_OPCODE_DDX_COARSE:
337 return "ddx_coarse";
338 case FS_OPCODE_DDX_FINE:
339 return "ddx_fine";
340 case FS_OPCODE_DDY_COARSE:
341 return "ddy_coarse";
342 case FS_OPCODE_DDY_FINE:
343 return "ddy_fine";
344
345 case FS_OPCODE_CINTERP:
346 return "cinterp";
347 case FS_OPCODE_LINTERP:
348 return "linterp";
349
350 case FS_OPCODE_PIXEL_X:
351 return "pixel_x";
352 case FS_OPCODE_PIXEL_Y:
353 return "pixel_y";
354
355 case FS_OPCODE_GET_BUFFER_SIZE:
356 return "fs_get_buffer_size";
357
358 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
359 return "uniform_pull_const";
360 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
361 return "uniform_pull_const_gen7";
362 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
363 return "varying_pull_const";
364 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
365 return "varying_pull_const_gen7";
366
367 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
368 return "mov_dispatch_to_flags";
369 case FS_OPCODE_DISCARD_JUMP:
370 return "discard_jump";
371
372 case FS_OPCODE_SET_SAMPLE_ID:
373 return "set_sample_id";
374 case FS_OPCODE_SET_SIMD4X2_OFFSET:
375 return "set_simd4x2_offset";
376
377 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
378 return "pack_half_2x16_split";
379 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
380 return "unpack_half_2x16_split_x";
381 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
382 return "unpack_half_2x16_split_y";
383
384 case FS_OPCODE_PLACEHOLDER_HALT:
385 return "placeholder_halt";
386
387 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
388 return "interp_centroid";
389 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
390 return "interp_sample";
391 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
392 return "interp_shared_offset";
393 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
394 return "interp_per_slot_offset";
395
396 case VS_OPCODE_URB_WRITE:
397 return "vs_urb_write";
398 case VS_OPCODE_PULL_CONSTANT_LOAD:
399 return "pull_constant_load";
400 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
401 return "pull_constant_load_gen7";
402
403 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
404 return "set_simd4x2_header_gen9";
405
406 case VS_OPCODE_GET_BUFFER_SIZE:
407 return "vs_get_buffer_size";
408
409 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
410 return "unpack_flags_simd4x2";
411
412 case GS_OPCODE_URB_WRITE:
413 return "gs_urb_write";
414 case GS_OPCODE_URB_WRITE_ALLOCATE:
415 return "gs_urb_write_allocate";
416 case GS_OPCODE_THREAD_END:
417 return "gs_thread_end";
418 case GS_OPCODE_SET_WRITE_OFFSET:
419 return "set_write_offset";
420 case GS_OPCODE_SET_VERTEX_COUNT:
421 return "set_vertex_count";
422 case GS_OPCODE_SET_DWORD_2:
423 return "set_dword_2";
424 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
425 return "prepare_channel_masks";
426 case GS_OPCODE_SET_CHANNEL_MASKS:
427 return "set_channel_masks";
428 case GS_OPCODE_GET_INSTANCE_ID:
429 return "get_instance_id";
430 case GS_OPCODE_FF_SYNC:
431 return "ff_sync";
432 case GS_OPCODE_SET_PRIMITIVE_ID:
433 return "set_primitive_id";
434 case GS_OPCODE_SVB_WRITE:
435 return "gs_svb_write";
436 case GS_OPCODE_SVB_SET_DST_INDEX:
437 return "gs_svb_set_dst_index";
438 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
439 return "gs_ff_sync_set_primitives";
440 case CS_OPCODE_CS_TERMINATE:
441 return "cs_terminate";
442 case SHADER_OPCODE_BARRIER:
443 return "barrier";
444 case SHADER_OPCODE_MULH:
445 return "mulh";
446 case SHADER_OPCODE_MOV_INDIRECT:
447 return "mov_indirect";
448
449 case VEC4_OPCODE_URB_READ:
450 return "urb_read";
451 case TCS_OPCODE_GET_INSTANCE_ID:
452 return "tcs_get_instance_id";
453 case TCS_OPCODE_URB_WRITE:
454 return "tcs_urb_write";
455 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
456 return "tcs_set_input_urb_offsets";
457 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
458 return "tcs_set_output_urb_offsets";
459 case TCS_OPCODE_GET_PRIMITIVE_ID:
460 return "tcs_get_primitive_id";
461 case TCS_OPCODE_CREATE_BARRIER_HEADER:
462 return "tcs_create_barrier_header";
463 case TCS_OPCODE_SRC0_010_IS_ZERO:
464 return "tcs_src0<0,1,0>_is_zero";
465 case TCS_OPCODE_RELEASE_INPUT:
466 return "tcs_release_input";
467 case TCS_OPCODE_THREAD_END:
468 return "tcs_thread_end";
469 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
470 return "tes_create_input_read_header";
471 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
472 return "tes_add_indirect_urb_offset";
473 case TES_OPCODE_GET_PRIMITIVE_ID:
474 return "tes_get_primitive_id";
475 }
476
477 unreachable("not reached");
478 }
479
480 bool
481 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
482 {
483 union {
484 unsigned ud;
485 int d;
486 float f;
487 double df;
488 } imm, sat_imm = { 0 };
489
490 const unsigned size = type_sz(type);
491
492 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
493 * irrelevant, so just check the size of the type and copy from/to an
494 * appropriately sized field.
495 */
496 if (size < 8)
497 imm.ud = reg->ud;
498 else
499 imm.df = reg->df;
500
501 switch (type) {
502 case BRW_REGISTER_TYPE_UD:
503 case BRW_REGISTER_TYPE_D:
504 case BRW_REGISTER_TYPE_UW:
505 case BRW_REGISTER_TYPE_W:
506 case BRW_REGISTER_TYPE_UQ:
507 case BRW_REGISTER_TYPE_Q:
508 /* Nothing to do. */
509 return false;
510 case BRW_REGISTER_TYPE_F:
511 sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
512 break;
513 case BRW_REGISTER_TYPE_DF:
514 sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
515 break;
516 case BRW_REGISTER_TYPE_UB:
517 case BRW_REGISTER_TYPE_B:
518 unreachable("no UB/B immediates");
519 case BRW_REGISTER_TYPE_V:
520 case BRW_REGISTER_TYPE_UV:
521 case BRW_REGISTER_TYPE_VF:
522 unreachable("unimplemented: saturate vector immediate");
523 case BRW_REGISTER_TYPE_HF:
524 unreachable("unimplemented: saturate HF immediate");
525 }
526
527 if (size < 8) {
528 if (imm.ud != sat_imm.ud) {
529 reg->ud = sat_imm.ud;
530 return true;
531 }
532 } else {
533 if (imm.df != sat_imm.df) {
534 reg->df = sat_imm.df;
535 return true;
536 }
537 }
538 return false;
539 }
540
541 bool
542 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
543 {
544 switch (type) {
545 case BRW_REGISTER_TYPE_D:
546 case BRW_REGISTER_TYPE_UD:
547 reg->d = -reg->d;
548 return true;
549 case BRW_REGISTER_TYPE_W:
550 case BRW_REGISTER_TYPE_UW:
551 reg->d = -(int16_t)reg->ud;
552 return true;
553 case BRW_REGISTER_TYPE_F:
554 reg->f = -reg->f;
555 return true;
556 case BRW_REGISTER_TYPE_VF:
557 reg->ud ^= 0x80808080;
558 return true;
559 case BRW_REGISTER_TYPE_DF:
560 reg->df = -reg->df;
561 return true;
562 case BRW_REGISTER_TYPE_UB:
563 case BRW_REGISTER_TYPE_B:
564 unreachable("no UB/B immediates");
565 case BRW_REGISTER_TYPE_UV:
566 case BRW_REGISTER_TYPE_V:
567 assert(!"unimplemented: negate UV/V immediate");
568 case BRW_REGISTER_TYPE_UQ:
569 case BRW_REGISTER_TYPE_Q:
570 assert(!"unimplemented: negate UQ/Q immediate");
571 case BRW_REGISTER_TYPE_HF:
572 assert(!"unimplemented: negate HF immediate");
573 }
574
575 return false;
576 }
577
578 bool
579 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
580 {
581 switch (type) {
582 case BRW_REGISTER_TYPE_D:
583 reg->d = abs(reg->d);
584 return true;
585 case BRW_REGISTER_TYPE_W:
586 reg->d = abs((int16_t)reg->ud);
587 return true;
588 case BRW_REGISTER_TYPE_F:
589 reg->f = fabsf(reg->f);
590 return true;
591 case BRW_REGISTER_TYPE_DF:
592 reg->df = fabs(reg->df);
593 return true;
594 case BRW_REGISTER_TYPE_VF:
595 reg->ud &= ~0x80808080;
596 return true;
597 case BRW_REGISTER_TYPE_UB:
598 case BRW_REGISTER_TYPE_B:
599 unreachable("no UB/B immediates");
600 case BRW_REGISTER_TYPE_UQ:
601 case BRW_REGISTER_TYPE_UD:
602 case BRW_REGISTER_TYPE_UW:
603 case BRW_REGISTER_TYPE_UV:
604 /* Presumably the absolute value modifier on an unsigned source is a
605 * nop, but it would be nice to confirm.
606 */
607 assert(!"unimplemented: abs unsigned immediate");
608 case BRW_REGISTER_TYPE_V:
609 assert(!"unimplemented: abs V immediate");
610 case BRW_REGISTER_TYPE_Q:
611 assert(!"unimplemented: abs Q immediate");
612 case BRW_REGISTER_TYPE_HF:
613 assert(!"unimplemented: abs HF immediate");
614 }
615
616 return false;
617 }
618
619 unsigned
620 tesslevel_outer_components(GLenum tes_primitive_mode)
621 {
622 switch (tes_primitive_mode) {
623 case GL_QUADS:
624 return 4;
625 case GL_TRIANGLES:
626 return 3;
627 case GL_ISOLINES:
628 return 2;
629 default:
630 unreachable("Bogus tessellation domain");
631 }
632 return 0;
633 }
634
635 unsigned
636 tesslevel_inner_components(GLenum tes_primitive_mode)
637 {
638 switch (tes_primitive_mode) {
639 case GL_QUADS:
640 return 2;
641 case GL_TRIANGLES:
642 return 1;
643 case GL_ISOLINES:
644 return 0;
645 default:
646 unreachable("Bogus tessellation domain");
647 }
648 return 0;
649 }
650
651 /**
652 * Given a normal .xyzw writemask, convert it to a writemask for a vector
653 * that's stored backwards, i.e. .wzyx.
654 */
655 unsigned
656 writemask_for_backwards_vector(unsigned mask)
657 {
658 unsigned new_mask = 0;
659
660 for (int i = 0; i < 4; i++)
661 new_mask |= ((mask >> i) & 1) << (3 - i);
662
663 return new_mask;
664 }
665
666 backend_shader::backend_shader(const struct brw_compiler *compiler,
667 void *log_data,
668 void *mem_ctx,
669 const nir_shader *shader,
670 struct brw_stage_prog_data *stage_prog_data)
671 : compiler(compiler),
672 log_data(log_data),
673 devinfo(compiler->devinfo),
674 nir(shader),
675 stage_prog_data(stage_prog_data),
676 mem_ctx(mem_ctx),
677 cfg(NULL),
678 stage(shader->stage)
679 {
680 debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
681 stage_name = _mesa_shader_stage_to_string(stage);
682 stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
683 is_passthrough_shader =
684 nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
685 }
686
687 bool
688 backend_reg::equals(const backend_reg &r) const
689 {
690 return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
691 reg_offset == r.reg_offset;
692 }
693
694 bool
695 backend_reg::is_zero() const
696 {
697 if (file != IMM)
698 return false;
699
700 switch (type) {
701 case BRW_REGISTER_TYPE_F:
702 return f == 0;
703 case BRW_REGISTER_TYPE_DF:
704 return df == 0;
705 case BRW_REGISTER_TYPE_D:
706 case BRW_REGISTER_TYPE_UD:
707 return d == 0;
708 default:
709 return false;
710 }
711 }
712
713 bool
714 backend_reg::is_one() const
715 {
716 if (file != IMM)
717 return false;
718
719 switch (type) {
720 case BRW_REGISTER_TYPE_F:
721 return f == 1.0f;
722 case BRW_REGISTER_TYPE_DF:
723 return df == 1.0;
724 case BRW_REGISTER_TYPE_D:
725 case BRW_REGISTER_TYPE_UD:
726 return d == 1;
727 default:
728 return false;
729 }
730 }
731
732 bool
733 backend_reg::is_negative_one() const
734 {
735 if (file != IMM)
736 return false;
737
738 switch (type) {
739 case BRW_REGISTER_TYPE_F:
740 return f == -1.0;
741 case BRW_REGISTER_TYPE_DF:
742 return df == -1.0;
743 case BRW_REGISTER_TYPE_D:
744 return d == -1;
745 default:
746 return false;
747 }
748 }
749
750 bool
751 backend_reg::is_null() const
752 {
753 return file == ARF && nr == BRW_ARF_NULL;
754 }
755
756
757 bool
758 backend_reg::is_accumulator() const
759 {
760 return file == ARF && nr == BRW_ARF_ACCUMULATOR;
761 }
762
763 bool
764 backend_reg::in_range(const backend_reg &r, unsigned n) const
765 {
766 return (file == r.file &&
767 nr == r.nr &&
768 reg_offset >= r.reg_offset &&
769 reg_offset < r.reg_offset + n);
770 }
771
772 bool
773 backend_instruction::is_commutative() const
774 {
775 switch (opcode) {
776 case BRW_OPCODE_AND:
777 case BRW_OPCODE_OR:
778 case BRW_OPCODE_XOR:
779 case BRW_OPCODE_ADD:
780 case BRW_OPCODE_MUL:
781 case SHADER_OPCODE_MULH:
782 return true;
783 case BRW_OPCODE_SEL:
784 /* MIN and MAX are commutative. */
785 if (conditional_mod == BRW_CONDITIONAL_GE ||
786 conditional_mod == BRW_CONDITIONAL_L) {
787 return true;
788 }
789 /* fallthrough */
790 default:
791 return false;
792 }
793 }
794
795 bool
796 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
797 {
798 return ::is_3src(devinfo, opcode);
799 }
800
801 bool
802 backend_instruction::is_tex() const
803 {
804 return (opcode == SHADER_OPCODE_TEX ||
805 opcode == FS_OPCODE_TXB ||
806 opcode == SHADER_OPCODE_TXD ||
807 opcode == SHADER_OPCODE_TXF ||
808 opcode == SHADER_OPCODE_TXF_CMS ||
809 opcode == SHADER_OPCODE_TXF_CMS_W ||
810 opcode == SHADER_OPCODE_TXF_UMS ||
811 opcode == SHADER_OPCODE_TXF_MCS ||
812 opcode == SHADER_OPCODE_TXL ||
813 opcode == SHADER_OPCODE_TXS ||
814 opcode == SHADER_OPCODE_LOD ||
815 opcode == SHADER_OPCODE_TG4 ||
816 opcode == SHADER_OPCODE_TG4_OFFSET ||
817 opcode == SHADER_OPCODE_SAMPLEINFO);
818 }
819
820 bool
821 backend_instruction::is_math() const
822 {
823 return (opcode == SHADER_OPCODE_RCP ||
824 opcode == SHADER_OPCODE_RSQ ||
825 opcode == SHADER_OPCODE_SQRT ||
826 opcode == SHADER_OPCODE_EXP2 ||
827 opcode == SHADER_OPCODE_LOG2 ||
828 opcode == SHADER_OPCODE_SIN ||
829 opcode == SHADER_OPCODE_COS ||
830 opcode == SHADER_OPCODE_INT_QUOTIENT ||
831 opcode == SHADER_OPCODE_INT_REMAINDER ||
832 opcode == SHADER_OPCODE_POW);
833 }
834
835 bool
836 backend_instruction::is_control_flow() const
837 {
838 switch (opcode) {
839 case BRW_OPCODE_DO:
840 case BRW_OPCODE_WHILE:
841 case BRW_OPCODE_IF:
842 case BRW_OPCODE_ELSE:
843 case BRW_OPCODE_ENDIF:
844 case BRW_OPCODE_BREAK:
845 case BRW_OPCODE_CONTINUE:
846 return true;
847 default:
848 return false;
849 }
850 }
851
852 bool
853 backend_instruction::can_do_source_mods() const
854 {
855 switch (opcode) {
856 case BRW_OPCODE_ADDC:
857 case BRW_OPCODE_BFE:
858 case BRW_OPCODE_BFI1:
859 case BRW_OPCODE_BFI2:
860 case BRW_OPCODE_BFREV:
861 case BRW_OPCODE_CBIT:
862 case BRW_OPCODE_FBH:
863 case BRW_OPCODE_FBL:
864 case BRW_OPCODE_SUBB:
865 return false;
866 default:
867 return true;
868 }
869 }
870
871 bool
872 backend_instruction::can_do_saturate() const
873 {
874 switch (opcode) {
875 case BRW_OPCODE_ADD:
876 case BRW_OPCODE_ASR:
877 case BRW_OPCODE_AVG:
878 case BRW_OPCODE_DP2:
879 case BRW_OPCODE_DP3:
880 case BRW_OPCODE_DP4:
881 case BRW_OPCODE_DPH:
882 case BRW_OPCODE_F16TO32:
883 case BRW_OPCODE_F32TO16:
884 case BRW_OPCODE_LINE:
885 case BRW_OPCODE_LRP:
886 case BRW_OPCODE_MAC:
887 case BRW_OPCODE_MAD:
888 case BRW_OPCODE_MATH:
889 case BRW_OPCODE_MOV:
890 case BRW_OPCODE_MUL:
891 case SHADER_OPCODE_MULH:
892 case BRW_OPCODE_PLN:
893 case BRW_OPCODE_RNDD:
894 case BRW_OPCODE_RNDE:
895 case BRW_OPCODE_RNDU:
896 case BRW_OPCODE_RNDZ:
897 case BRW_OPCODE_SEL:
898 case BRW_OPCODE_SHL:
899 case BRW_OPCODE_SHR:
900 case FS_OPCODE_LINTERP:
901 case SHADER_OPCODE_COS:
902 case SHADER_OPCODE_EXP2:
903 case SHADER_OPCODE_LOG2:
904 case SHADER_OPCODE_POW:
905 case SHADER_OPCODE_RCP:
906 case SHADER_OPCODE_RSQ:
907 case SHADER_OPCODE_SIN:
908 case SHADER_OPCODE_SQRT:
909 return true;
910 default:
911 return false;
912 }
913 }
914
915 bool
916 backend_instruction::can_do_cmod() const
917 {
918 switch (opcode) {
919 case BRW_OPCODE_ADD:
920 case BRW_OPCODE_ADDC:
921 case BRW_OPCODE_AND:
922 case BRW_OPCODE_ASR:
923 case BRW_OPCODE_AVG:
924 case BRW_OPCODE_CMP:
925 case BRW_OPCODE_CMPN:
926 case BRW_OPCODE_DP2:
927 case BRW_OPCODE_DP3:
928 case BRW_OPCODE_DP4:
929 case BRW_OPCODE_DPH:
930 case BRW_OPCODE_F16TO32:
931 case BRW_OPCODE_F32TO16:
932 case BRW_OPCODE_FRC:
933 case BRW_OPCODE_LINE:
934 case BRW_OPCODE_LRP:
935 case BRW_OPCODE_LZD:
936 case BRW_OPCODE_MAC:
937 case BRW_OPCODE_MACH:
938 case BRW_OPCODE_MAD:
939 case BRW_OPCODE_MOV:
940 case BRW_OPCODE_MUL:
941 case BRW_OPCODE_NOT:
942 case BRW_OPCODE_OR:
943 case BRW_OPCODE_PLN:
944 case BRW_OPCODE_RNDD:
945 case BRW_OPCODE_RNDE:
946 case BRW_OPCODE_RNDU:
947 case BRW_OPCODE_RNDZ:
948 case BRW_OPCODE_SAD2:
949 case BRW_OPCODE_SADA2:
950 case BRW_OPCODE_SHL:
951 case BRW_OPCODE_SHR:
952 case BRW_OPCODE_SUBB:
953 case BRW_OPCODE_XOR:
954 case FS_OPCODE_CINTERP:
955 case FS_OPCODE_LINTERP:
956 return true;
957 default:
958 return false;
959 }
960 }
961
962 bool
963 backend_instruction::reads_accumulator_implicitly() const
964 {
965 switch (opcode) {
966 case BRW_OPCODE_MAC:
967 case BRW_OPCODE_MACH:
968 case BRW_OPCODE_SADA2:
969 return true;
970 default:
971 return false;
972 }
973 }
974
975 bool
976 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
977 {
978 return writes_accumulator ||
979 (devinfo->gen < 6 &&
980 ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
981 (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
982 opcode != FS_OPCODE_CINTERP)));
983 }
984
985 bool
986 backend_instruction::has_side_effects() const
987 {
988 switch (opcode) {
989 case SHADER_OPCODE_UNTYPED_ATOMIC:
990 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
991 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
992 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
993 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
994 case SHADER_OPCODE_TYPED_ATOMIC:
995 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
996 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
997 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
998 case SHADER_OPCODE_MEMORY_FENCE:
999 case SHADER_OPCODE_URB_WRITE_SIMD8:
1000 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1001 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1002 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1003 case FS_OPCODE_FB_WRITE:
1004 case SHADER_OPCODE_BARRIER:
1005 case TCS_OPCODE_URB_WRITE:
1006 case TCS_OPCODE_RELEASE_INPUT:
1007 return true;
1008 default:
1009 return false;
1010 }
1011 }
1012
1013 bool
1014 backend_instruction::is_volatile() const
1015 {
1016 switch (opcode) {
1017 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1018 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1019 case SHADER_OPCODE_TYPED_SURFACE_READ:
1020 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1021 case SHADER_OPCODE_URB_READ_SIMD8:
1022 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1023 case VEC4_OPCODE_URB_READ:
1024 return true;
1025 default:
1026 return false;
1027 }
1028 }
1029
1030 #ifndef NDEBUG
1031 static bool
1032 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1033 {
1034 bool found = false;
1035 foreach_inst_in_block (backend_instruction, i, block) {
1036 if (inst == i) {
1037 found = true;
1038 }
1039 }
1040 return found;
1041 }
1042 #endif
1043
1044 static void
1045 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1046 {
1047 for (bblock_t *block_iter = start_block->next();
1048 block_iter;
1049 block_iter = block_iter->next()) {
1050 block_iter->start_ip += ip_adjustment;
1051 block_iter->end_ip += ip_adjustment;
1052 }
1053 }
1054
1055 void
1056 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1057 {
1058 assert(this != inst);
1059
1060 if (!this->is_head_sentinel())
1061 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1062
1063 block->end_ip++;
1064
1065 adjust_later_block_ips(block, 1);
1066
1067 exec_node::insert_after(inst);
1068 }
1069
1070 void
1071 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1072 {
1073 assert(this != inst);
1074
1075 if (!this->is_tail_sentinel())
1076 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1077
1078 block->end_ip++;
1079
1080 adjust_later_block_ips(block, 1);
1081
1082 exec_node::insert_before(inst);
1083 }
1084
1085 void
1086 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1087 {
1088 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1089
1090 unsigned num_inst = list->length();
1091
1092 block->end_ip += num_inst;
1093
1094 adjust_later_block_ips(block, num_inst);
1095
1096 exec_node::insert_before(list);
1097 }
1098
1099 void
1100 backend_instruction::remove(bblock_t *block)
1101 {
1102 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1103
1104 adjust_later_block_ips(block, -1);
1105
1106 if (block->start_ip == block->end_ip) {
1107 block->cfg->remove_block(block);
1108 } else {
1109 block->end_ip--;
1110 }
1111
1112 exec_node::remove();
1113 }
1114
1115 void
1116 backend_shader::dump_instructions()
1117 {
1118 dump_instructions(NULL);
1119 }
1120
1121 void
1122 backend_shader::dump_instructions(const char *name)
1123 {
1124 FILE *file = stderr;
1125 if (name && geteuid() != 0) {
1126 file = fopen(name, "w");
1127 if (!file)
1128 file = stderr;
1129 }
1130
1131 if (cfg) {
1132 int ip = 0;
1133 foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1134 if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1135 fprintf(file, "%4d: ", ip++);
1136 dump_instruction(inst, file);
1137 }
1138 } else {
1139 int ip = 0;
1140 foreach_in_list(backend_instruction, inst, &instructions) {
1141 if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1142 fprintf(file, "%4d: ", ip++);
1143 dump_instruction(inst, file);
1144 }
1145 }
1146
1147 if (file != stderr) {
1148 fclose(file);
1149 }
1150 }
1151
1152 void
1153 backend_shader::calculate_cfg()
1154 {
1155 if (this->cfg)
1156 return;
1157 cfg = new(mem_ctx) cfg_t(&this->instructions);
1158 }
1159
1160 /**
1161 * Sets up the starting offsets for the groups of binding table entries
1162 * commong to all pipeline stages.
1163 *
1164 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1165 * unused but also make sure that addition of small offsets to them will
1166 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1167 */
1168 void
1169 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1170 const struct brw_device_info *devinfo,
1171 const struct gl_shader_program *shader_prog,
1172 const struct gl_program *prog,
1173 struct brw_stage_prog_data *stage_prog_data,
1174 uint32_t next_binding_table_offset)
1175 {
1176 const struct gl_shader *shader = NULL;
1177 int num_textures = _mesa_fls(prog->SamplersUsed);
1178
1179 if (shader_prog)
1180 shader = shader_prog->_LinkedShaders[stage];
1181
1182 stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1183 next_binding_table_offset += num_textures;
1184
1185 if (shader) {
1186 assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1187 stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1188 next_binding_table_offset += shader->NumUniformBlocks;
1189
1190 assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1191 stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1192 next_binding_table_offset += shader->NumShaderStorageBlocks;
1193 } else {
1194 stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1195 stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1196 }
1197
1198 if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1199 stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1200 next_binding_table_offset++;
1201 } else {
1202 stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1203 }
1204
1205 if (prog->UsesGather) {
1206 if (devinfo->gen >= 8) {
1207 stage_prog_data->binding_table.gather_texture_start =
1208 stage_prog_data->binding_table.texture_start;
1209 } else {
1210 stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1211 next_binding_table_offset += num_textures;
1212 }
1213 } else {
1214 stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1215 }
1216
1217 if (shader && shader->NumAtomicBuffers) {
1218 stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1219 next_binding_table_offset += shader->NumAtomicBuffers;
1220 } else {
1221 stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1222 }
1223
1224 if (shader && shader->NumImages) {
1225 stage_prog_data->binding_table.image_start = next_binding_table_offset;
1226 next_binding_table_offset += shader->NumImages;
1227 } else {
1228 stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1229 }
1230
1231 /* This may or may not be used depending on how the compile goes. */
1232 stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1233 next_binding_table_offset++;
1234
1235 assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1236
1237 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1238 }
1239
1240 static void
1241 setup_vec4_uniform_value(const gl_constant_value **params,
1242 const gl_constant_value *values,
1243 unsigned n)
1244 {
1245 static const gl_constant_value zero = { 0 };
1246
1247 for (unsigned i = 0; i < n; ++i)
1248 params[i] = &values[i];
1249
1250 for (unsigned i = n; i < 4; ++i)
1251 params[i] = &zero;
1252 }
1253
1254 void
1255 brw_setup_image_uniform_values(gl_shader_stage stage,
1256 struct brw_stage_prog_data *stage_prog_data,
1257 unsigned param_start_index,
1258 const gl_uniform_storage *storage)
1259 {
1260 const gl_constant_value **param =
1261 &stage_prog_data->param[param_start_index];
1262
1263 for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1264 const unsigned image_idx = storage->opaque[stage].index + i;
1265 const brw_image_param *image_param =
1266 &stage_prog_data->image_param[image_idx];
1267
1268 /* Upload the brw_image_param structure. The order is expected to match
1269 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1270 */
1271 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1272 (const gl_constant_value *)&image_param->surface_idx, 1);
1273 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1274 (const gl_constant_value *)image_param->offset, 2);
1275 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1276 (const gl_constant_value *)image_param->size, 3);
1277 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1278 (const gl_constant_value *)image_param->stride, 4);
1279 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1280 (const gl_constant_value *)image_param->tiling, 3);
1281 setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1282 (const gl_constant_value *)image_param->swizzling, 2);
1283 param += BRW_IMAGE_PARAM_SIZE;
1284
1285 brw_mark_surface_used(
1286 stage_prog_data,
1287 stage_prog_data->binding_table.image_start + image_idx);
1288 }
1289 }
1290
1291 /**
1292 * Decide which set of clip planes should be used when clipping via
1293 * gl_Position or gl_ClipVertex.
1294 */
1295 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1296 {
1297 if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1298 /* There is currently a GLSL vertex shader, so clip according to GLSL
1299 * rules, which means compare gl_ClipVertex (or gl_Position, if
1300 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1301 * that were stored in EyeUserPlane at the time the clip planes were
1302 * specified.
1303 */
1304 return ctx->Transform.EyeUserPlane;
1305 } else {
1306 /* Either we are using fixed function or an ARB vertex program. In
1307 * either case the clip planes are going to be compared against
1308 * gl_Position (which is in clip coordinates) so we have to clip using
1309 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1310 * core.
1311 */
1312 return ctx->Transform._ClipUserPlane;
1313 }
1314 }
1315
1316 extern "C" const unsigned *
1317 brw_compile_tes(const struct brw_compiler *compiler,
1318 void *log_data,
1319 void *mem_ctx,
1320 const struct brw_tes_prog_key *key,
1321 struct brw_tes_prog_data *prog_data,
1322 const nir_shader *src_shader,
1323 struct gl_shader_program *shader_prog,
1324 int shader_time_index,
1325 unsigned *final_assembly_size,
1326 char **error_str)
1327 {
1328 const struct brw_device_info *devinfo = compiler->devinfo;
1329 struct gl_shader *shader =
1330 shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1331 const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1332
1333 nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1334 nir->info.inputs_read = key->inputs_read;
1335 nir->info.patch_inputs_read = key->patch_inputs_read;
1336
1337 struct brw_vue_map input_vue_map;
1338 brw_compute_tess_vue_map(&input_vue_map,
1339 nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1340 nir->info.patch_inputs_read);
1341
1342 nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1343 brw_nir_lower_tes_inputs(nir, &input_vue_map);
1344 brw_nir_lower_vue_outputs(nir, is_scalar);
1345 nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1346
1347 brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1348 nir->info.outputs_written,
1349 nir->info.separate_shader);
1350
1351 unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1352
1353 assert(output_size_bytes >= 1);
1354 if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1355 if (error_str)
1356 *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1357 return NULL;
1358 }
1359
1360 /* URB entry sizes are stored as a multiple of 64 bytes. */
1361 prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1362
1363 bool need_patch_header = nir->info.system_values_read &
1364 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1365 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1366
1367 /* The TES will pull most inputs using URB read messages.
1368 *
1369 * However, we push the patch header for TessLevel factors when required,
1370 * as it's a tiny amount of extra data.
1371 */
1372 prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1373
1374 if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1375 fprintf(stderr, "TES Input ");
1376 brw_print_vue_map(stderr, &input_vue_map);
1377 fprintf(stderr, "TES Output ");
1378 brw_print_vue_map(stderr, &prog_data->base.vue_map);
1379 }
1380
1381 if (is_scalar) {
1382 fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1383 &prog_data->base.base, shader->Program, nir, 8,
1384 shader_time_index, &input_vue_map);
1385 if (!v.run_tes()) {
1386 if (error_str)
1387 *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1388 return NULL;
1389 }
1390
1391 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1392
1393 fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1394 &prog_data->base.base, v.promoted_constants, false,
1395 MESA_SHADER_TESS_EVAL);
1396 if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1397 g.enable_debug(ralloc_asprintf(mem_ctx,
1398 "%s tessellation evaluation shader %s",
1399 nir->info.label ? nir->info.label
1400 : "unnamed",
1401 nir->info.name));
1402 }
1403
1404 g.generate_code(v.cfg, 8);
1405
1406 return g.get_assembly(final_assembly_size);
1407 } else {
1408 brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1409 nir, mem_ctx, shader_time_index);
1410 if (!v.run()) {
1411 if (error_str)
1412 *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1413 return NULL;
1414 }
1415
1416 if (unlikely(INTEL_DEBUG & DEBUG_TES))
1417 v.dump_instructions();
1418
1419 return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1420 &prog_data->base, v.cfg,
1421 final_assembly_size);
1422 }
1423 }