2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/macros.h"
25 #include "brw_context.h"
31 #include "glsl/ir_optimization.h"
32 #include "glsl/glsl_parser_extras.h"
33 #include "main/shaderapi.h"
36 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
38 struct brw_context
*brw
= (struct brw_context
*)data
;
43 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
44 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
45 MESA_DEBUG_TYPE_OTHER
,
46 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
51 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
53 struct brw_context
*brw
= (struct brw_context
*)data
;
58 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
60 va_copy(args_copy
, args
);
61 vfprintf(stderr
, fmt
, args_copy
);
65 if (brw
->perf_debug
) {
67 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
68 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
69 MESA_DEBUG_TYPE_PERFORMANCE
,
70 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
76 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
78 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
80 compiler
->devinfo
= devinfo
;
81 compiler
->shader_debug_log
= shader_debug_log_mesa
;
82 compiler
->shader_perf_log
= shader_perf_log_mesa
;
84 brw_fs_alloc_reg_sets(compiler
);
85 brw_vec4_alloc_reg_set(compiler
);
87 if (devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
))
88 compiler
->scalar_vs
= true;
90 nir_shader_compiler_options
*nir_options
=
91 rzalloc(compiler
, nir_shader_compiler_options
);
92 nir_options
->native_integers
= true;
93 /* In order to help allow for better CSE at the NIR level we tell NIR
94 * to split all ffma instructions during opt_algebraic and we then
95 * re-combine them as a later step.
97 nir_options
->lower_ffma
= true;
98 nir_options
->lower_sub
= true;
100 /* We want the GLSL compiler to emit code that uses condition codes */
101 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
102 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
103 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
104 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
106 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
107 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
108 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
109 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
110 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
=
111 (i
== MESA_SHADER_FRAGMENT
);
112 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
=
113 (i
== MESA_SHADER_FRAGMENT
);
114 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
115 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
117 /* !ARB_gpu_shader5 */
118 if (devinfo
->gen
< 7)
119 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
122 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].OptimizeForAOS
= true;
123 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].OptimizeForAOS
= true;
125 if (compiler
->scalar_vs
|| brw_env_var_as_boolean("INTEL_USE_NIR", true)) {
126 if (compiler
->scalar_vs
) {
127 /* If we're using the scalar backend for vertex shaders, we need to
128 * configure these accordingly.
130 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].EmitNoIndirectOutput
= true;
131 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].EmitNoIndirectTemp
= true;
132 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].OptimizeForAOS
= false;
135 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].NirOptions
= nir_options
;
138 if (brw_env_var_as_boolean("INTEL_USE_NIR", true)) {
139 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].NirOptions
= nir_options
;
142 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
= nir_options
;
143 compiler
->glsl_compiler_options
[MESA_SHADER_COMPUTE
].NirOptions
= nir_options
;
149 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
151 struct brw_shader
*shader
;
153 shader
= rzalloc(NULL
, struct brw_shader
);
155 shader
->base
.Type
= type
;
156 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
157 shader
->base
.Name
= name
;
158 _mesa_init_shader(ctx
, &shader
->base
);
161 return &shader
->base
;
165 * Performs a compile of the shader stages even when we don't know
166 * what non-orthogonal state will be set, in the hope that it reflects
167 * the eventual NOS used, and thus allows us to produce link failures.
170 brw_shader_precompile(struct gl_context
*ctx
,
171 struct gl_shader_program
*sh_prog
)
173 struct gl_shader
*vs
= sh_prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
174 struct gl_shader
*gs
= sh_prog
->_LinkedShaders
[MESA_SHADER_GEOMETRY
];
175 struct gl_shader
*fs
= sh_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
176 struct gl_shader
*cs
= sh_prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
];
178 if (fs
&& !brw_fs_precompile(ctx
, sh_prog
, fs
->Program
))
181 if (gs
&& !brw_gs_precompile(ctx
, sh_prog
, gs
->Program
))
184 if (vs
&& !brw_vs_precompile(ctx
, sh_prog
, vs
->Program
))
187 if (cs
&& !brw_cs_precompile(ctx
, sh_prog
, cs
->Program
))
194 is_scalar_shader_stage(struct brw_context
*brw
, int stage
)
197 case MESA_SHADER_FRAGMENT
:
199 case MESA_SHADER_VERTEX
:
200 return brw
->intelScreen
->compiler
->scalar_vs
;
207 brw_lower_packing_builtins(struct brw_context
*brw
,
208 gl_shader_stage shader_type
,
211 int ops
= LOWER_PACK_SNORM_2x16
212 | LOWER_UNPACK_SNORM_2x16
213 | LOWER_PACK_UNORM_2x16
214 | LOWER_UNPACK_UNORM_2x16
;
216 if (is_scalar_shader_stage(brw
, shader_type
)) {
217 ops
|= LOWER_UNPACK_UNORM_4x8
218 | LOWER_UNPACK_SNORM_4x8
219 | LOWER_PACK_UNORM_4x8
220 | LOWER_PACK_SNORM_4x8
;
224 /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
225 * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
226 * lowering is needed. For SOA code, the Half2x16 ops must be
229 if (is_scalar_shader_stage(brw
, shader_type
)) {
230 ops
|= LOWER_PACK_HALF_2x16_TO_SPLIT
231 | LOWER_UNPACK_HALF_2x16_TO_SPLIT
;
234 ops
|= LOWER_PACK_HALF_2x16
235 | LOWER_UNPACK_HALF_2x16
;
238 lower_packing_builtins(ir
, ops
);
242 process_glsl_ir(gl_shader_stage stage
,
243 struct brw_context
*brw
,
244 struct gl_shader_program
*shader_prog
,
245 struct gl_shader
*shader
)
247 struct gl_context
*ctx
= &brw
->ctx
;
248 const struct gl_shader_compiler_options
*options
=
249 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
251 /* Temporary memory context for any new IR. */
252 void *mem_ctx
= ralloc_context(NULL
);
254 ralloc_adopt(mem_ctx
, shader
->ir
);
256 /* lower_packing_builtins() inserts arithmetic instructions, so it
257 * must precede lower_instructions().
259 brw_lower_packing_builtins(brw
, shader
->Stage
, shader
->ir
);
260 do_mat_op_to_vec(shader
->ir
);
261 const int bitfield_insert
= brw
->gen
>= 7 ? BITFIELD_INSERT_TO_BFM_BFI
: 0;
262 lower_instructions(shader
->ir
,
273 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
274 * if-statements need to be flattened.
277 lower_if_to_cond_assign(shader
->ir
, 16);
279 do_lower_texture_projection(shader
->ir
);
280 brw_lower_texture_gradients(brw
, shader
->ir
);
281 do_vec_index_to_cond_assign(shader
->ir
);
282 lower_vector_insert(shader
->ir
, true);
283 if (options
->NirOptions
== NULL
)
284 brw_do_cubemap_normalize(shader
->ir
);
285 lower_offset_arrays(shader
->ir
);
286 brw_do_lower_unnormalized_offset(shader
->ir
);
287 lower_noise(shader
->ir
);
288 lower_quadop_vector(shader
->ir
, false);
290 bool lowered_variable_indexing
=
291 lower_variable_index_to_cond_assign((gl_shader_stage
)stage
,
293 options
->EmitNoIndirectInput
,
294 options
->EmitNoIndirectOutput
,
295 options
->EmitNoIndirectTemp
,
296 options
->EmitNoIndirectUniform
);
298 if (unlikely(brw
->perf_debug
&& lowered_variable_indexing
)) {
299 perf_debug("Unsupported form of variable indexing in %s; falling "
300 "back to very inefficient code generation\n",
301 _mesa_shader_stage_to_abbrev(shader
->Stage
));
304 lower_ubo_reference(shader
, shader
->ir
);
310 if (is_scalar_shader_stage(brw
, shader
->Stage
)) {
311 brw_do_channel_expressions(shader
->ir
);
312 brw_do_vector_splitting(shader
->ir
);
315 progress
= do_lower_jumps(shader
->ir
, true, true,
316 true, /* main return */
317 false, /* continue */
321 progress
= do_common_optimization(shader
->ir
, true, true,
322 options
, ctx
->Const
.NativeIntegers
) || progress
;
325 if (options
->NirOptions
!= NULL
)
326 lower_output_reads(stage
, shader
->ir
);
328 validate_ir_tree(shader
->ir
);
330 /* Now that we've finished altering the linked IR, reparent any live IR back
331 * to the permanent memory context, and free the temporary one (discarding any
332 * junk we optimized away).
334 reparent_ir(shader
->ir
, shader
->ir
);
335 ralloc_free(mem_ctx
);
337 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
338 fprintf(stderr
, "\n");
339 fprintf(stderr
, "GLSL IR for linked %s program %d:\n",
340 _mesa_shader_stage_to_string(shader
->Stage
),
342 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
343 fprintf(stderr
, "\n");
348 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*shProg
)
350 struct brw_context
*brw
= brw_context(ctx
);
353 for (stage
= 0; stage
< ARRAY_SIZE(shProg
->_LinkedShaders
); stage
++) {
354 struct gl_shader
*shader
= shProg
->_LinkedShaders
[stage
];
355 const struct gl_shader_compiler_options
*options
=
356 &ctx
->Const
.ShaderCompilerOptions
[stage
];
361 struct gl_program
*prog
=
362 ctx
->Driver
.NewProgram(ctx
, _mesa_shader_stage_to_program(stage
),
366 prog
->Parameters
= _mesa_new_parameter_list();
368 _mesa_copy_linked_program_data((gl_shader_stage
) stage
, shProg
, prog
);
370 process_glsl_ir((gl_shader_stage
) stage
, brw
, shProg
, shader
);
372 /* Make a pass over the IR to add state references for any built-in
373 * uniforms that are used. This has to be done now (during linking).
374 * Code generation doesn't happen until the first time this shader is
375 * used for rendering. Waiting until then to generate the parameters is
376 * too late. At that point, the values for the built-in uniforms won't
377 * get sent to the shader.
379 foreach_in_list(ir_instruction
, node
, shader
->ir
) {
380 ir_variable
*var
= node
->as_variable();
382 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
383 || (strncmp(var
->name
, "gl_", 3) != 0))
386 const ir_state_slot
*const slots
= var
->get_state_slots();
387 assert(slots
!= NULL
);
389 for (unsigned int i
= 0; i
< var
->get_num_state_slots(); i
++) {
390 _mesa_add_state_reference(prog
->Parameters
,
391 (gl_state_index
*) slots
[i
].tokens
);
395 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
397 prog
->SamplersUsed
= shader
->active_samplers
;
398 prog
->ShadowSamplers
= shader
->shadow_samplers
;
399 _mesa_update_shader_textures_used(shProg
, prog
);
401 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
403 brw_add_texrect_params(prog
);
405 if (options
->NirOptions
) {
406 prog
->nir
= brw_create_nir(brw
, shProg
, prog
, (gl_shader_stage
) stage
,
407 is_scalar_shader_stage(brw
, stage
));
410 _mesa_reference_program(ctx
, &prog
, NULL
);
413 if ((ctx
->_Shader
->Flags
& GLSL_DUMP
) && shProg
->Name
!= 0) {
414 for (unsigned i
= 0; i
< shProg
->NumShaders
; i
++) {
415 const struct gl_shader
*sh
= shProg
->Shaders
[i
];
419 fprintf(stderr
, "GLSL %s shader %d source for linked program %d:\n",
420 _mesa_shader_stage_to_string(sh
->Stage
),
422 fprintf(stderr
, "%s", sh
->Source
);
423 fprintf(stderr
, "\n");
427 if (brw
->precompile
&& !brw_shader_precompile(ctx
, shProg
))
435 brw_type_for_base_type(const struct glsl_type
*type
)
437 switch (type
->base_type
) {
438 case GLSL_TYPE_FLOAT
:
439 return BRW_REGISTER_TYPE_F
;
442 case GLSL_TYPE_SUBROUTINE
:
443 return BRW_REGISTER_TYPE_D
;
445 return BRW_REGISTER_TYPE_UD
;
446 case GLSL_TYPE_ARRAY
:
447 return brw_type_for_base_type(type
->fields
.array
);
448 case GLSL_TYPE_STRUCT
:
449 case GLSL_TYPE_SAMPLER
:
450 case GLSL_TYPE_ATOMIC_UINT
:
451 /* These should be overridden with the type of the member when
452 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
453 * way to trip up if we don't.
455 return BRW_REGISTER_TYPE_UD
;
456 case GLSL_TYPE_IMAGE
:
457 return BRW_REGISTER_TYPE_UD
;
459 case GLSL_TYPE_ERROR
:
460 case GLSL_TYPE_INTERFACE
:
461 case GLSL_TYPE_DOUBLE
:
462 unreachable("not reached");
465 return BRW_REGISTER_TYPE_F
;
468 enum brw_conditional_mod
469 brw_conditional_for_comparison(unsigned int op
)
473 return BRW_CONDITIONAL_L
;
474 case ir_binop_greater
:
475 return BRW_CONDITIONAL_G
;
476 case ir_binop_lequal
:
477 return BRW_CONDITIONAL_LE
;
478 case ir_binop_gequal
:
479 return BRW_CONDITIONAL_GE
;
481 case ir_binop_all_equal
: /* same as equal for scalars */
482 return BRW_CONDITIONAL_Z
;
483 case ir_binop_nequal
:
484 case ir_binop_any_nequal
: /* same as nequal for scalars */
485 return BRW_CONDITIONAL_NZ
;
487 unreachable("not reached: bad operation for comparison");
492 brw_math_function(enum opcode op
)
495 case SHADER_OPCODE_RCP
:
496 return BRW_MATH_FUNCTION_INV
;
497 case SHADER_OPCODE_RSQ
:
498 return BRW_MATH_FUNCTION_RSQ
;
499 case SHADER_OPCODE_SQRT
:
500 return BRW_MATH_FUNCTION_SQRT
;
501 case SHADER_OPCODE_EXP2
:
502 return BRW_MATH_FUNCTION_EXP
;
503 case SHADER_OPCODE_LOG2
:
504 return BRW_MATH_FUNCTION_LOG
;
505 case SHADER_OPCODE_POW
:
506 return BRW_MATH_FUNCTION_POW
;
507 case SHADER_OPCODE_SIN
:
508 return BRW_MATH_FUNCTION_SIN
;
509 case SHADER_OPCODE_COS
:
510 return BRW_MATH_FUNCTION_COS
;
511 case SHADER_OPCODE_INT_QUOTIENT
:
512 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
513 case SHADER_OPCODE_INT_REMAINDER
:
514 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
516 unreachable("not reached: unknown math function");
521 brw_texture_offset(int *offsets
, unsigned num_components
)
523 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
525 /* Combine all three offsets into a single unsigned dword:
527 * bits 11:8 - U Offset (X component)
528 * bits 7:4 - V Offset (Y component)
529 * bits 3:0 - R Offset (Z component)
531 unsigned offset_bits
= 0;
532 for (unsigned i
= 0; i
< num_components
; i
++) {
533 const unsigned shift
= 4 * (2 - i
);
534 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
540 brw_instruction_name(enum opcode op
)
543 case BRW_OPCODE_MOV
... BRW_OPCODE_NOP
:
544 assert(opcode_descs
[op
].name
);
545 return opcode_descs
[op
].name
;
546 case FS_OPCODE_FB_WRITE
:
548 case FS_OPCODE_FB_WRITE_LOGICAL
:
549 return "fb_write_logical";
550 case FS_OPCODE_BLORP_FB_WRITE
:
551 return "blorp_fb_write";
552 case FS_OPCODE_REP_FB_WRITE
:
553 return "rep_fb_write";
555 case SHADER_OPCODE_RCP
:
557 case SHADER_OPCODE_RSQ
:
559 case SHADER_OPCODE_SQRT
:
561 case SHADER_OPCODE_EXP2
:
563 case SHADER_OPCODE_LOG2
:
565 case SHADER_OPCODE_POW
:
567 case SHADER_OPCODE_INT_QUOTIENT
:
569 case SHADER_OPCODE_INT_REMAINDER
:
571 case SHADER_OPCODE_SIN
:
573 case SHADER_OPCODE_COS
:
576 case SHADER_OPCODE_TEX
:
578 case SHADER_OPCODE_TEX_LOGICAL
:
579 return "tex_logical";
580 case SHADER_OPCODE_TXD
:
582 case SHADER_OPCODE_TXD_LOGICAL
:
583 return "txd_logical";
584 case SHADER_OPCODE_TXF
:
586 case SHADER_OPCODE_TXF_LOGICAL
:
587 return "txf_logical";
588 case SHADER_OPCODE_TXL
:
590 case SHADER_OPCODE_TXL_LOGICAL
:
591 return "txl_logical";
592 case SHADER_OPCODE_TXS
:
594 case SHADER_OPCODE_TXS_LOGICAL
:
595 return "txs_logical";
598 case FS_OPCODE_TXB_LOGICAL
:
599 return "txb_logical";
600 case SHADER_OPCODE_TXF_CMS
:
602 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
603 return "txf_cms_logical";
604 case SHADER_OPCODE_TXF_UMS
:
606 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
607 return "txf_ums_logical";
608 case SHADER_OPCODE_TXF_MCS
:
610 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
611 return "txf_mcs_logical";
612 case SHADER_OPCODE_LOD
:
614 case SHADER_OPCODE_LOD_LOGICAL
:
615 return "lod_logical";
616 case SHADER_OPCODE_TG4
:
618 case SHADER_OPCODE_TG4_LOGICAL
:
619 return "tg4_logical";
620 case SHADER_OPCODE_TG4_OFFSET
:
622 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
623 return "tg4_offset_logical";
625 case SHADER_OPCODE_SHADER_TIME_ADD
:
626 return "shader_time_add";
628 case SHADER_OPCODE_UNTYPED_ATOMIC
:
629 return "untyped_atomic";
630 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
631 return "untyped_atomic_logical";
632 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
633 return "untyped_surface_read";
634 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
635 return "untyped_surface_read_logical";
636 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
637 return "untyped_surface_write";
638 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
639 return "untyped_surface_write_logical";
640 case SHADER_OPCODE_TYPED_ATOMIC
:
641 return "typed_atomic";
642 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
643 return "typed_atomic_logical";
644 case SHADER_OPCODE_TYPED_SURFACE_READ
:
645 return "typed_surface_read";
646 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
647 return "typed_surface_read_logical";
648 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
649 return "typed_surface_write";
650 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
651 return "typed_surface_write_logical";
652 case SHADER_OPCODE_MEMORY_FENCE
:
653 return "memory_fence";
655 case SHADER_OPCODE_LOAD_PAYLOAD
:
656 return "load_payload";
658 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
659 return "gen4_scratch_read";
660 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
661 return "gen4_scratch_write";
662 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
663 return "gen7_scratch_read";
664 case SHADER_OPCODE_URB_WRITE_SIMD8
:
665 return "gen8_urb_write_simd8";
667 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
668 return "find_live_channel";
669 case SHADER_OPCODE_BROADCAST
:
672 case VEC4_OPCODE_MOV_BYTES
:
674 case VEC4_OPCODE_PACK_BYTES
:
676 case VEC4_OPCODE_UNPACK_UNIFORM
:
677 return "unpack_uniform";
679 case FS_OPCODE_DDX_COARSE
:
681 case FS_OPCODE_DDX_FINE
:
683 case FS_OPCODE_DDY_COARSE
:
685 case FS_OPCODE_DDY_FINE
:
688 case FS_OPCODE_CINTERP
:
690 case FS_OPCODE_LINTERP
:
693 case FS_OPCODE_PIXEL_X
:
695 case FS_OPCODE_PIXEL_Y
:
698 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
699 return "uniform_pull_const";
700 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
701 return "uniform_pull_const_gen7";
702 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
703 return "varying_pull_const";
704 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
705 return "varying_pull_const_gen7";
707 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
708 return "mov_dispatch_to_flags";
709 case FS_OPCODE_DISCARD_JUMP
:
710 return "discard_jump";
712 case FS_OPCODE_SET_SAMPLE_ID
:
713 return "set_sample_id";
714 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
715 return "set_simd4x2_offset";
717 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
718 return "pack_half_2x16_split";
719 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
720 return "unpack_half_2x16_split_x";
721 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
722 return "unpack_half_2x16_split_y";
724 case FS_OPCODE_PLACEHOLDER_HALT
:
725 return "placeholder_halt";
727 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
728 return "interp_centroid";
729 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
730 return "interp_sample";
731 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
732 return "interp_shared_offset";
733 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
734 return "interp_per_slot_offset";
736 case VS_OPCODE_URB_WRITE
:
737 return "vs_urb_write";
738 case VS_OPCODE_PULL_CONSTANT_LOAD
:
739 return "pull_constant_load";
740 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
741 return "pull_constant_load_gen7";
743 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
744 return "set_simd4x2_header_gen9";
746 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
747 return "unpack_flags_simd4x2";
749 case GS_OPCODE_URB_WRITE
:
750 return "gs_urb_write";
751 case GS_OPCODE_URB_WRITE_ALLOCATE
:
752 return "gs_urb_write_allocate";
753 case GS_OPCODE_THREAD_END
:
754 return "gs_thread_end";
755 case GS_OPCODE_SET_WRITE_OFFSET
:
756 return "set_write_offset";
757 case GS_OPCODE_SET_VERTEX_COUNT
:
758 return "set_vertex_count";
759 case GS_OPCODE_SET_DWORD_2
:
760 return "set_dword_2";
761 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
762 return "prepare_channel_masks";
763 case GS_OPCODE_SET_CHANNEL_MASKS
:
764 return "set_channel_masks";
765 case GS_OPCODE_GET_INSTANCE_ID
:
766 return "get_instance_id";
767 case GS_OPCODE_FF_SYNC
:
769 case GS_OPCODE_SET_PRIMITIVE_ID
:
770 return "set_primitive_id";
771 case GS_OPCODE_SVB_WRITE
:
772 return "gs_svb_write";
773 case GS_OPCODE_SVB_SET_DST_INDEX
:
774 return "gs_svb_set_dst_index";
775 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
776 return "gs_ff_sync_set_primitives";
777 case CS_OPCODE_CS_TERMINATE
:
778 return "cs_terminate";
779 case SHADER_OPCODE_BARRIER
:
781 case SHADER_OPCODE_MULH
:
785 unreachable("not reached");
789 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
795 } imm
= { reg
->dw1
.ud
}, sat_imm
= { 0 };
798 case BRW_REGISTER_TYPE_UD
:
799 case BRW_REGISTER_TYPE_D
:
800 case BRW_REGISTER_TYPE_UQ
:
801 case BRW_REGISTER_TYPE_Q
:
804 case BRW_REGISTER_TYPE_UW
:
805 sat_imm
.ud
= CLAMP(imm
.ud
, 0, USHRT_MAX
);
807 case BRW_REGISTER_TYPE_W
:
808 sat_imm
.d
= CLAMP(imm
.d
, SHRT_MIN
, SHRT_MAX
);
810 case BRW_REGISTER_TYPE_F
:
811 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
813 case BRW_REGISTER_TYPE_UB
:
814 case BRW_REGISTER_TYPE_B
:
815 unreachable("no UB/B immediates");
816 case BRW_REGISTER_TYPE_V
:
817 case BRW_REGISTER_TYPE_UV
:
818 case BRW_REGISTER_TYPE_VF
:
819 unreachable("unimplemented: saturate vector immediate");
820 case BRW_REGISTER_TYPE_DF
:
821 case BRW_REGISTER_TYPE_HF
:
822 unreachable("unimplemented: saturate DF/HF immediate");
825 if (imm
.ud
!= sat_imm
.ud
) {
826 reg
->dw1
.ud
= sat_imm
.ud
;
833 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
836 case BRW_REGISTER_TYPE_D
:
837 case BRW_REGISTER_TYPE_UD
:
838 reg
->dw1
.d
= -reg
->dw1
.d
;
840 case BRW_REGISTER_TYPE_W
:
841 case BRW_REGISTER_TYPE_UW
:
842 reg
->dw1
.d
= -(int16_t)reg
->dw1
.ud
;
844 case BRW_REGISTER_TYPE_F
:
845 reg
->dw1
.f
= -reg
->dw1
.f
;
847 case BRW_REGISTER_TYPE_VF
:
848 reg
->dw1
.ud
^= 0x80808080;
850 case BRW_REGISTER_TYPE_UB
:
851 case BRW_REGISTER_TYPE_B
:
852 unreachable("no UB/B immediates");
853 case BRW_REGISTER_TYPE_UV
:
854 case BRW_REGISTER_TYPE_V
:
855 assert(!"unimplemented: negate UV/V immediate");
856 case BRW_REGISTER_TYPE_UQ
:
857 case BRW_REGISTER_TYPE_Q
:
858 assert(!"unimplemented: negate UQ/Q immediate");
859 case BRW_REGISTER_TYPE_DF
:
860 case BRW_REGISTER_TYPE_HF
:
861 assert(!"unimplemented: negate DF/HF immediate");
868 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
871 case BRW_REGISTER_TYPE_D
:
872 reg
->dw1
.d
= abs(reg
->dw1
.d
);
874 case BRW_REGISTER_TYPE_W
:
875 reg
->dw1
.d
= abs((int16_t)reg
->dw1
.ud
);
877 case BRW_REGISTER_TYPE_F
:
878 reg
->dw1
.f
= fabsf(reg
->dw1
.f
);
880 case BRW_REGISTER_TYPE_VF
:
881 reg
->dw1
.ud
&= ~0x80808080;
883 case BRW_REGISTER_TYPE_UB
:
884 case BRW_REGISTER_TYPE_B
:
885 unreachable("no UB/B immediates");
886 case BRW_REGISTER_TYPE_UQ
:
887 case BRW_REGISTER_TYPE_UD
:
888 case BRW_REGISTER_TYPE_UW
:
889 case BRW_REGISTER_TYPE_UV
:
890 /* Presumably the absolute value modifier on an unsigned source is a
891 * nop, but it would be nice to confirm.
893 assert(!"unimplemented: abs unsigned immediate");
894 case BRW_REGISTER_TYPE_V
:
895 assert(!"unimplemented: abs V immediate");
896 case BRW_REGISTER_TYPE_Q
:
897 assert(!"unimplemented: abs Q immediate");
898 case BRW_REGISTER_TYPE_DF
:
899 case BRW_REGISTER_TYPE_HF
:
900 assert(!"unimplemented: abs DF/HF immediate");
906 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
909 struct gl_shader_program
*shader_prog
,
910 struct gl_program
*prog
,
911 struct brw_stage_prog_data
*stage_prog_data
,
912 gl_shader_stage stage
)
913 : compiler(compiler
),
915 devinfo(compiler
->devinfo
),
917 (struct brw_shader
*)shader_prog
->_LinkedShaders
[stage
] : NULL
),
918 shader_prog(shader_prog
),
920 stage_prog_data(stage_prog_data
),
925 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
926 stage_name
= _mesa_shader_stage_to_string(stage
);
927 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
931 backend_reg::is_zero() const
936 return fixed_hw_reg
.dw1
.d
== 0;
940 backend_reg::is_one() const
945 return type
== BRW_REGISTER_TYPE_F
946 ? fixed_hw_reg
.dw1
.f
== 1.0
947 : fixed_hw_reg
.dw1
.d
== 1;
951 backend_reg::is_negative_one() const
957 case BRW_REGISTER_TYPE_F
:
958 return fixed_hw_reg
.dw1
.f
== -1.0;
959 case BRW_REGISTER_TYPE_D
:
960 return fixed_hw_reg
.dw1
.d
== -1;
967 backend_reg::is_null() const
969 return file
== HW_REG
&&
970 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
971 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
976 backend_reg::is_accumulator() const
978 return file
== HW_REG
&&
979 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
980 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
984 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
986 return (file
== r
.file
&&
988 reg_offset
>= r
.reg_offset
&&
989 reg_offset
< r
.reg_offset
+ n
);
993 backend_instruction::is_commutative() const
1000 case BRW_OPCODE_MUL
:
1001 case SHADER_OPCODE_MULH
:
1003 case BRW_OPCODE_SEL
:
1004 /* MIN and MAX are commutative. */
1005 if (conditional_mod
== BRW_CONDITIONAL_GE
||
1006 conditional_mod
== BRW_CONDITIONAL_L
) {
1016 backend_instruction::is_3src() const
1018 return opcode
< ARRAY_SIZE(opcode_descs
) && opcode_descs
[opcode
].nsrc
== 3;
1022 backend_instruction::is_tex() const
1024 return (opcode
== SHADER_OPCODE_TEX
||
1025 opcode
== FS_OPCODE_TXB
||
1026 opcode
== SHADER_OPCODE_TXD
||
1027 opcode
== SHADER_OPCODE_TXF
||
1028 opcode
== SHADER_OPCODE_TXF_CMS
||
1029 opcode
== SHADER_OPCODE_TXF_UMS
||
1030 opcode
== SHADER_OPCODE_TXF_MCS
||
1031 opcode
== SHADER_OPCODE_TXL
||
1032 opcode
== SHADER_OPCODE_TXS
||
1033 opcode
== SHADER_OPCODE_LOD
||
1034 opcode
== SHADER_OPCODE_TG4
||
1035 opcode
== SHADER_OPCODE_TG4_OFFSET
);
1039 backend_instruction::is_math() const
1041 return (opcode
== SHADER_OPCODE_RCP
||
1042 opcode
== SHADER_OPCODE_RSQ
||
1043 opcode
== SHADER_OPCODE_SQRT
||
1044 opcode
== SHADER_OPCODE_EXP2
||
1045 opcode
== SHADER_OPCODE_LOG2
||
1046 opcode
== SHADER_OPCODE_SIN
||
1047 opcode
== SHADER_OPCODE_COS
||
1048 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
1049 opcode
== SHADER_OPCODE_INT_REMAINDER
||
1050 opcode
== SHADER_OPCODE_POW
);
1054 backend_instruction::is_control_flow() const
1058 case BRW_OPCODE_WHILE
:
1060 case BRW_OPCODE_ELSE
:
1061 case BRW_OPCODE_ENDIF
:
1062 case BRW_OPCODE_BREAK
:
1063 case BRW_OPCODE_CONTINUE
:
1071 backend_instruction::can_do_source_mods() const
1074 case BRW_OPCODE_ADDC
:
1075 case BRW_OPCODE_BFE
:
1076 case BRW_OPCODE_BFI1
:
1077 case BRW_OPCODE_BFI2
:
1078 case BRW_OPCODE_BFREV
:
1079 case BRW_OPCODE_CBIT
:
1080 case BRW_OPCODE_FBH
:
1081 case BRW_OPCODE_FBL
:
1082 case BRW_OPCODE_SUBB
:
1090 backend_instruction::can_do_saturate() const
1093 case BRW_OPCODE_ADD
:
1094 case BRW_OPCODE_ASR
:
1095 case BRW_OPCODE_AVG
:
1096 case BRW_OPCODE_DP2
:
1097 case BRW_OPCODE_DP3
:
1098 case BRW_OPCODE_DP4
:
1099 case BRW_OPCODE_DPH
:
1100 case BRW_OPCODE_F16TO32
:
1101 case BRW_OPCODE_F32TO16
:
1102 case BRW_OPCODE_LINE
:
1103 case BRW_OPCODE_LRP
:
1104 case BRW_OPCODE_MAC
:
1105 case BRW_OPCODE_MAD
:
1106 case BRW_OPCODE_MATH
:
1107 case BRW_OPCODE_MOV
:
1108 case BRW_OPCODE_MUL
:
1109 case SHADER_OPCODE_MULH
:
1110 case BRW_OPCODE_PLN
:
1111 case BRW_OPCODE_RNDD
:
1112 case BRW_OPCODE_RNDE
:
1113 case BRW_OPCODE_RNDU
:
1114 case BRW_OPCODE_RNDZ
:
1115 case BRW_OPCODE_SEL
:
1116 case BRW_OPCODE_SHL
:
1117 case BRW_OPCODE_SHR
:
1118 case FS_OPCODE_LINTERP
:
1119 case SHADER_OPCODE_COS
:
1120 case SHADER_OPCODE_EXP2
:
1121 case SHADER_OPCODE_LOG2
:
1122 case SHADER_OPCODE_POW
:
1123 case SHADER_OPCODE_RCP
:
1124 case SHADER_OPCODE_RSQ
:
1125 case SHADER_OPCODE_SIN
:
1126 case SHADER_OPCODE_SQRT
:
1134 backend_instruction::can_do_cmod() const
1137 case BRW_OPCODE_ADD
:
1138 case BRW_OPCODE_ADDC
:
1139 case BRW_OPCODE_AND
:
1140 case BRW_OPCODE_ASR
:
1141 case BRW_OPCODE_AVG
:
1142 case BRW_OPCODE_CMP
:
1143 case BRW_OPCODE_CMPN
:
1144 case BRW_OPCODE_DP2
:
1145 case BRW_OPCODE_DP3
:
1146 case BRW_OPCODE_DP4
:
1147 case BRW_OPCODE_DPH
:
1148 case BRW_OPCODE_F16TO32
:
1149 case BRW_OPCODE_F32TO16
:
1150 case BRW_OPCODE_FRC
:
1151 case BRW_OPCODE_LINE
:
1152 case BRW_OPCODE_LRP
:
1153 case BRW_OPCODE_LZD
:
1154 case BRW_OPCODE_MAC
:
1155 case BRW_OPCODE_MACH
:
1156 case BRW_OPCODE_MAD
:
1157 case BRW_OPCODE_MOV
:
1158 case BRW_OPCODE_MUL
:
1159 case BRW_OPCODE_NOT
:
1161 case BRW_OPCODE_PLN
:
1162 case BRW_OPCODE_RNDD
:
1163 case BRW_OPCODE_RNDE
:
1164 case BRW_OPCODE_RNDU
:
1165 case BRW_OPCODE_RNDZ
:
1166 case BRW_OPCODE_SAD2
:
1167 case BRW_OPCODE_SADA2
:
1168 case BRW_OPCODE_SHL
:
1169 case BRW_OPCODE_SHR
:
1170 case BRW_OPCODE_SUBB
:
1171 case BRW_OPCODE_XOR
:
1172 case FS_OPCODE_CINTERP
:
1173 case FS_OPCODE_LINTERP
:
1181 backend_instruction::reads_accumulator_implicitly() const
1184 case BRW_OPCODE_MAC
:
1185 case BRW_OPCODE_MACH
:
1186 case BRW_OPCODE_SADA2
:
1194 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
1196 return writes_accumulator
||
1197 (devinfo
->gen
< 6 &&
1198 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
1199 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
1200 opcode
!= FS_OPCODE_CINTERP
)));
1204 backend_instruction::has_side_effects() const
1207 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1208 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
1209 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1210 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1211 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
1212 case SHADER_OPCODE_TYPED_ATOMIC
:
1213 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1214 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1215 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1216 case SHADER_OPCODE_MEMORY_FENCE
:
1217 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1218 case FS_OPCODE_FB_WRITE
:
1219 case SHADER_OPCODE_BARRIER
:
1228 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1231 foreach_inst_in_block (backend_instruction
, i
, block
) {
1241 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1243 for (bblock_t
*block_iter
= start_block
->next();
1244 !block_iter
->link
.is_tail_sentinel();
1245 block_iter
= block_iter
->next()) {
1246 block_iter
->start_ip
+= ip_adjustment
;
1247 block_iter
->end_ip
+= ip_adjustment
;
1252 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1254 if (!this->is_head_sentinel())
1255 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1259 adjust_later_block_ips(block
, 1);
1261 exec_node::insert_after(inst
);
1265 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1267 if (!this->is_tail_sentinel())
1268 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1272 adjust_later_block_ips(block
, 1);
1274 exec_node::insert_before(inst
);
1278 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1280 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1282 unsigned num_inst
= list
->length();
1284 block
->end_ip
+= num_inst
;
1286 adjust_later_block_ips(block
, num_inst
);
1288 exec_node::insert_before(list
);
1292 backend_instruction::remove(bblock_t
*block
)
1294 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1296 adjust_later_block_ips(block
, -1);
1298 if (block
->start_ip
== block
->end_ip
) {
1299 block
->cfg
->remove_block(block
);
1304 exec_node::remove();
1308 backend_shader::dump_instructions()
1310 dump_instructions(NULL
);
1314 backend_shader::dump_instructions(const char *name
)
1316 FILE *file
= stderr
;
1317 if (name
&& geteuid() != 0) {
1318 file
= fopen(name
, "w");
1325 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1326 fprintf(file
, "%4d: ", ip
++);
1327 dump_instruction(inst
, file
);
1331 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1332 fprintf(file
, "%4d: ", ip
++);
1333 dump_instruction(inst
, file
);
1337 if (file
!= stderr
) {
1343 backend_shader::calculate_cfg()
1347 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1351 backend_shader::invalidate_cfg()
1353 ralloc_free(this->cfg
);
1358 * Sets up the starting offsets for the groups of binding table entries
1359 * commong to all pipeline stages.
1361 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1362 * unused but also make sure that addition of small offsets to them will
1363 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1366 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset
)
1368 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1370 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1371 next_binding_table_offset
+= num_textures
;
1374 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1375 next_binding_table_offset
+= shader
->base
.NumUniformBlocks
;
1377 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1380 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1381 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1382 next_binding_table_offset
++;
1384 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1387 if (prog
->UsesGather
) {
1388 if (devinfo
->gen
>= 8) {
1389 stage_prog_data
->binding_table
.gather_texture_start
=
1390 stage_prog_data
->binding_table
.texture_start
;
1392 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1393 next_binding_table_offset
+= num_textures
;
1396 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1399 if (shader_prog
&& shader_prog
->NumAtomicBuffers
) {
1400 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1401 next_binding_table_offset
+= shader_prog
->NumAtomicBuffers
;
1403 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1406 if (shader
&& shader
->base
.NumImages
) {
1407 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1408 next_binding_table_offset
+= shader
->base
.NumImages
;
1410 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1413 /* This may or may not be used depending on how the compile goes. */
1414 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1415 next_binding_table_offset
++;
1417 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1419 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1423 backend_shader::setup_image_uniform_values(const gl_uniform_storage
*storage
)
1425 const unsigned stage
= _mesa_program_enum_to_shader_stage(prog
->Target
);
1427 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1428 const unsigned image_idx
= storage
->image
[stage
].index
+ i
;
1429 const brw_image_param
*param
= &stage_prog_data
->image_param
[image_idx
];
1431 /* Upload the brw_image_param structure. The order is expected to match
1432 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1434 setup_vec4_uniform_value(
1435 (const gl_constant_value
*)¶m
->surface_idx
, 1);
1436 setup_vec4_uniform_value(
1437 (const gl_constant_value
*)param
->offset
, 2);
1438 setup_vec4_uniform_value(
1439 (const gl_constant_value
*)param
->size
, 3);
1440 setup_vec4_uniform_value(
1441 (const gl_constant_value
*)param
->stride
, 4);
1442 setup_vec4_uniform_value(
1443 (const gl_constant_value
*)param
->tiling
, 3);
1444 setup_vec4_uniform_value(
1445 (const gl_constant_value
*)param
->swizzling
, 2);
1447 brw_mark_surface_used(
1449 stage_prog_data
->binding_table
.image_start
+ image_idx
);