2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_context.h"
29 #include "brw_vec4_tes.h"
30 #include "main/shaderobj.h"
31 #include "main/uniforms.h"
33 extern "C" struct gl_shader
*
34 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
36 struct brw_shader
*shader
;
38 shader
= rzalloc(NULL
, struct brw_shader
);
40 shader
->base
.Type
= type
;
41 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
42 shader
->base
.Name
= name
;
43 _mesa_init_shader(ctx
, &shader
->base
);
50 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
53 assert(surf_index
< BRW_MAX_SURFACES
);
55 prog_data
->binding_table
.size_bytes
=
56 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
60 brw_type_for_base_type(const struct glsl_type
*type
)
62 switch (type
->base_type
) {
64 return BRW_REGISTER_TYPE_F
;
67 case GLSL_TYPE_SUBROUTINE
:
68 return BRW_REGISTER_TYPE_D
;
70 return BRW_REGISTER_TYPE_UD
;
72 return brw_type_for_base_type(type
->fields
.array
);
73 case GLSL_TYPE_STRUCT
:
74 case GLSL_TYPE_SAMPLER
:
75 case GLSL_TYPE_ATOMIC_UINT
:
76 /* These should be overridden with the type of the member when
77 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
78 * way to trip up if we don't.
80 return BRW_REGISTER_TYPE_UD
;
82 return BRW_REGISTER_TYPE_UD
;
85 case GLSL_TYPE_INTERFACE
:
86 case GLSL_TYPE_DOUBLE
:
87 case GLSL_TYPE_FUNCTION
:
88 unreachable("not reached");
91 return BRW_REGISTER_TYPE_F
;
94 enum brw_conditional_mod
95 brw_conditional_for_comparison(unsigned int op
)
99 return BRW_CONDITIONAL_L
;
100 case ir_binop_greater
:
101 return BRW_CONDITIONAL_G
;
102 case ir_binop_lequal
:
103 return BRW_CONDITIONAL_LE
;
104 case ir_binop_gequal
:
105 return BRW_CONDITIONAL_GE
;
107 case ir_binop_all_equal
: /* same as equal for scalars */
108 return BRW_CONDITIONAL_Z
;
109 case ir_binop_nequal
:
110 case ir_binop_any_nequal
: /* same as nequal for scalars */
111 return BRW_CONDITIONAL_NZ
;
113 unreachable("not reached: bad operation for comparison");
118 brw_math_function(enum opcode op
)
121 case SHADER_OPCODE_RCP
:
122 return BRW_MATH_FUNCTION_INV
;
123 case SHADER_OPCODE_RSQ
:
124 return BRW_MATH_FUNCTION_RSQ
;
125 case SHADER_OPCODE_SQRT
:
126 return BRW_MATH_FUNCTION_SQRT
;
127 case SHADER_OPCODE_EXP2
:
128 return BRW_MATH_FUNCTION_EXP
;
129 case SHADER_OPCODE_LOG2
:
130 return BRW_MATH_FUNCTION_LOG
;
131 case SHADER_OPCODE_POW
:
132 return BRW_MATH_FUNCTION_POW
;
133 case SHADER_OPCODE_SIN
:
134 return BRW_MATH_FUNCTION_SIN
;
135 case SHADER_OPCODE_COS
:
136 return BRW_MATH_FUNCTION_COS
;
137 case SHADER_OPCODE_INT_QUOTIENT
:
138 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
139 case SHADER_OPCODE_INT_REMAINDER
:
140 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
142 unreachable("not reached: unknown math function");
147 brw_texture_offset(int *offsets
, unsigned num_components
)
149 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
151 /* Combine all three offsets into a single unsigned dword:
153 * bits 11:8 - U Offset (X component)
154 * bits 7:4 - V Offset (Y component)
155 * bits 3:0 - R Offset (Z component)
157 unsigned offset_bits
= 0;
158 for (unsigned i
= 0; i
< num_components
; i
++) {
159 const unsigned shift
= 4 * (2 - i
);
160 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
166 brw_instruction_name(enum opcode op
)
169 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
170 assert(opcode_descs
[op
].name
);
171 return opcode_descs
[op
].name
;
172 case FS_OPCODE_FB_WRITE
:
174 case FS_OPCODE_FB_WRITE_LOGICAL
:
175 return "fb_write_logical";
176 case FS_OPCODE_PACK_STENCIL_REF
:
177 return "pack_stencil_ref";
178 case FS_OPCODE_BLORP_FB_WRITE
:
179 return "blorp_fb_write";
180 case FS_OPCODE_REP_FB_WRITE
:
181 return "rep_fb_write";
183 case SHADER_OPCODE_RCP
:
185 case SHADER_OPCODE_RSQ
:
187 case SHADER_OPCODE_SQRT
:
189 case SHADER_OPCODE_EXP2
:
191 case SHADER_OPCODE_LOG2
:
193 case SHADER_OPCODE_POW
:
195 case SHADER_OPCODE_INT_QUOTIENT
:
197 case SHADER_OPCODE_INT_REMAINDER
:
199 case SHADER_OPCODE_SIN
:
201 case SHADER_OPCODE_COS
:
204 case SHADER_OPCODE_TEX
:
206 case SHADER_OPCODE_TEX_LOGICAL
:
207 return "tex_logical";
208 case SHADER_OPCODE_TXD
:
210 case SHADER_OPCODE_TXD_LOGICAL
:
211 return "txd_logical";
212 case SHADER_OPCODE_TXF
:
214 case SHADER_OPCODE_TXF_LOGICAL
:
215 return "txf_logical";
216 case SHADER_OPCODE_TXL
:
218 case SHADER_OPCODE_TXL_LOGICAL
:
219 return "txl_logical";
220 case SHADER_OPCODE_TXS
:
222 case SHADER_OPCODE_TXS_LOGICAL
:
223 return "txs_logical";
226 case FS_OPCODE_TXB_LOGICAL
:
227 return "txb_logical";
228 case SHADER_OPCODE_TXF_CMS
:
230 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
231 return "txf_cms_logical";
232 case SHADER_OPCODE_TXF_CMS_W
:
234 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
235 return "txf_cms_w_logical";
236 case SHADER_OPCODE_TXF_UMS
:
238 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
239 return "txf_ums_logical";
240 case SHADER_OPCODE_TXF_MCS
:
242 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
243 return "txf_mcs_logical";
244 case SHADER_OPCODE_LOD
:
246 case SHADER_OPCODE_LOD_LOGICAL
:
247 return "lod_logical";
248 case SHADER_OPCODE_TG4
:
250 case SHADER_OPCODE_TG4_LOGICAL
:
251 return "tg4_logical";
252 case SHADER_OPCODE_TG4_OFFSET
:
254 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
255 return "tg4_offset_logical";
256 case SHADER_OPCODE_SAMPLEINFO
:
259 case SHADER_OPCODE_SHADER_TIME_ADD
:
260 return "shader_time_add";
262 case SHADER_OPCODE_UNTYPED_ATOMIC
:
263 return "untyped_atomic";
264 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
265 return "untyped_atomic_logical";
266 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
267 return "untyped_surface_read";
268 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
269 return "untyped_surface_read_logical";
270 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
271 return "untyped_surface_write";
272 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
273 return "untyped_surface_write_logical";
274 case SHADER_OPCODE_TYPED_ATOMIC
:
275 return "typed_atomic";
276 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
277 return "typed_atomic_logical";
278 case SHADER_OPCODE_TYPED_SURFACE_READ
:
279 return "typed_surface_read";
280 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
281 return "typed_surface_read_logical";
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 return "typed_surface_write";
284 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
285 return "typed_surface_write_logical";
286 case SHADER_OPCODE_MEMORY_FENCE
:
287 return "memory_fence";
289 case SHADER_OPCODE_LOAD_PAYLOAD
:
290 return "load_payload";
292 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
293 return "gen4_scratch_read";
294 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
295 return "gen4_scratch_write";
296 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
297 return "gen7_scratch_read";
298 case SHADER_OPCODE_URB_WRITE_SIMD8
:
299 return "gen8_urb_write_simd8";
300 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
301 return "gen8_urb_write_simd8_per_slot";
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
303 return "gen8_urb_write_simd8_masked";
304 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
305 return "gen8_urb_write_simd8_masked_per_slot";
306 case SHADER_OPCODE_URB_READ_SIMD8
:
307 return "urb_read_simd8";
308 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
309 return "urb_read_simd8_per_slot";
311 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
312 return "find_live_channel";
313 case SHADER_OPCODE_BROADCAST
:
316 case SHADER_OPCODE_EXTRACT_BYTE
:
317 return "extract_byte";
318 case SHADER_OPCODE_EXTRACT_WORD
:
319 return "extract_word";
320 case VEC4_OPCODE_MOV_BYTES
:
322 case VEC4_OPCODE_PACK_BYTES
:
324 case VEC4_OPCODE_UNPACK_UNIFORM
:
325 return "unpack_uniform";
327 case FS_OPCODE_DDX_COARSE
:
329 case FS_OPCODE_DDX_FINE
:
331 case FS_OPCODE_DDY_COARSE
:
333 case FS_OPCODE_DDY_FINE
:
336 case FS_OPCODE_CINTERP
:
338 case FS_OPCODE_LINTERP
:
341 case FS_OPCODE_PIXEL_X
:
343 case FS_OPCODE_PIXEL_Y
:
346 case FS_OPCODE_GET_BUFFER_SIZE
:
347 return "fs_get_buffer_size";
349 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
350 return "uniform_pull_const";
351 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
352 return "uniform_pull_const_gen7";
353 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
354 return "varying_pull_const";
355 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
356 return "varying_pull_const_gen7";
358 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
359 return "mov_dispatch_to_flags";
360 case FS_OPCODE_DISCARD_JUMP
:
361 return "discard_jump";
363 case FS_OPCODE_SET_SAMPLE_ID
:
364 return "set_sample_id";
365 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
366 return "set_simd4x2_offset";
368 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
369 return "pack_half_2x16_split";
370 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
371 return "unpack_half_2x16_split_x";
372 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
373 return "unpack_half_2x16_split_y";
375 case FS_OPCODE_PLACEHOLDER_HALT
:
376 return "placeholder_halt";
378 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
379 return "interp_centroid";
380 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
381 return "interp_sample";
382 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
383 return "interp_shared_offset";
384 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
385 return "interp_per_slot_offset";
387 case VS_OPCODE_URB_WRITE
:
388 return "vs_urb_write";
389 case VS_OPCODE_PULL_CONSTANT_LOAD
:
390 return "pull_constant_load";
391 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
392 return "pull_constant_load_gen7";
394 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
395 return "set_simd4x2_header_gen9";
397 case VS_OPCODE_GET_BUFFER_SIZE
:
398 return "vs_get_buffer_size";
400 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
401 return "unpack_flags_simd4x2";
403 case GS_OPCODE_URB_WRITE
:
404 return "gs_urb_write";
405 case GS_OPCODE_URB_WRITE_ALLOCATE
:
406 return "gs_urb_write_allocate";
407 case GS_OPCODE_THREAD_END
:
408 return "gs_thread_end";
409 case GS_OPCODE_SET_WRITE_OFFSET
:
410 return "set_write_offset";
411 case GS_OPCODE_SET_VERTEX_COUNT
:
412 return "set_vertex_count";
413 case GS_OPCODE_SET_DWORD_2
:
414 return "set_dword_2";
415 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
416 return "prepare_channel_masks";
417 case GS_OPCODE_SET_CHANNEL_MASKS
:
418 return "set_channel_masks";
419 case GS_OPCODE_GET_INSTANCE_ID
:
420 return "get_instance_id";
421 case GS_OPCODE_FF_SYNC
:
423 case GS_OPCODE_SET_PRIMITIVE_ID
:
424 return "set_primitive_id";
425 case GS_OPCODE_SVB_WRITE
:
426 return "gs_svb_write";
427 case GS_OPCODE_SVB_SET_DST_INDEX
:
428 return "gs_svb_set_dst_index";
429 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
430 return "gs_ff_sync_set_primitives";
431 case CS_OPCODE_CS_TERMINATE
:
432 return "cs_terminate";
433 case SHADER_OPCODE_BARRIER
:
435 case SHADER_OPCODE_MULH
:
437 case SHADER_OPCODE_MOV_INDIRECT
:
438 return "mov_indirect";
440 case VEC4_OPCODE_URB_READ
:
442 case TCS_OPCODE_GET_INSTANCE_ID
:
443 return "tcs_get_instance_id";
444 case TCS_OPCODE_URB_WRITE
:
445 return "tcs_urb_write";
446 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
447 return "tcs_set_input_urb_offsets";
448 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
449 return "tcs_set_output_urb_offsets";
450 case TCS_OPCODE_GET_PRIMITIVE_ID
:
451 return "tcs_get_primitive_id";
452 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
453 return "tcs_create_barrier_header";
454 case TCS_OPCODE_SRC0_010_IS_ZERO
:
455 return "tcs_src0<0,1,0>_is_zero";
456 case TCS_OPCODE_RELEASE_INPUT
:
457 return "tcs_release_input";
458 case TCS_OPCODE_THREAD_END
:
459 return "tcs_thread_end";
460 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
461 return "tes_create_input_read_header";
462 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
463 return "tes_add_indirect_urb_offset";
464 case TES_OPCODE_GET_PRIMITIVE_ID
:
465 return "tes_get_primitive_id";
468 unreachable("not reached");
472 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
478 } imm
= { reg
->ud
}, sat_imm
= { 0 };
481 case BRW_REGISTER_TYPE_UD
:
482 case BRW_REGISTER_TYPE_D
:
483 case BRW_REGISTER_TYPE_UW
:
484 case BRW_REGISTER_TYPE_W
:
485 case BRW_REGISTER_TYPE_UQ
:
486 case BRW_REGISTER_TYPE_Q
:
489 case BRW_REGISTER_TYPE_F
:
490 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
492 case BRW_REGISTER_TYPE_UB
:
493 case BRW_REGISTER_TYPE_B
:
494 unreachable("no UB/B immediates");
495 case BRW_REGISTER_TYPE_V
:
496 case BRW_REGISTER_TYPE_UV
:
497 case BRW_REGISTER_TYPE_VF
:
498 unreachable("unimplemented: saturate vector immediate");
499 case BRW_REGISTER_TYPE_DF
:
500 case BRW_REGISTER_TYPE_HF
:
501 unreachable("unimplemented: saturate DF/HF immediate");
504 if (imm
.ud
!= sat_imm
.ud
) {
505 reg
->ud
= sat_imm
.ud
;
512 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
515 case BRW_REGISTER_TYPE_D
:
516 case BRW_REGISTER_TYPE_UD
:
519 case BRW_REGISTER_TYPE_W
:
520 case BRW_REGISTER_TYPE_UW
:
521 reg
->d
= -(int16_t)reg
->ud
;
523 case BRW_REGISTER_TYPE_F
:
526 case BRW_REGISTER_TYPE_VF
:
527 reg
->ud
^= 0x80808080;
529 case BRW_REGISTER_TYPE_UB
:
530 case BRW_REGISTER_TYPE_B
:
531 unreachable("no UB/B immediates");
532 case BRW_REGISTER_TYPE_UV
:
533 case BRW_REGISTER_TYPE_V
:
534 assert(!"unimplemented: negate UV/V immediate");
535 case BRW_REGISTER_TYPE_UQ
:
536 case BRW_REGISTER_TYPE_Q
:
537 assert(!"unimplemented: negate UQ/Q immediate");
538 case BRW_REGISTER_TYPE_DF
:
539 case BRW_REGISTER_TYPE_HF
:
540 assert(!"unimplemented: negate DF/HF immediate");
547 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
550 case BRW_REGISTER_TYPE_D
:
551 reg
->d
= abs(reg
->d
);
553 case BRW_REGISTER_TYPE_W
:
554 reg
->d
= abs((int16_t)reg
->ud
);
556 case BRW_REGISTER_TYPE_F
:
557 reg
->f
= fabsf(reg
->f
);
559 case BRW_REGISTER_TYPE_VF
:
560 reg
->ud
&= ~0x80808080;
562 case BRW_REGISTER_TYPE_UB
:
563 case BRW_REGISTER_TYPE_B
:
564 unreachable("no UB/B immediates");
565 case BRW_REGISTER_TYPE_UQ
:
566 case BRW_REGISTER_TYPE_UD
:
567 case BRW_REGISTER_TYPE_UW
:
568 case BRW_REGISTER_TYPE_UV
:
569 /* Presumably the absolute value modifier on an unsigned source is a
570 * nop, but it would be nice to confirm.
572 assert(!"unimplemented: abs unsigned immediate");
573 case BRW_REGISTER_TYPE_V
:
574 assert(!"unimplemented: abs V immediate");
575 case BRW_REGISTER_TYPE_Q
:
576 assert(!"unimplemented: abs Q immediate");
577 case BRW_REGISTER_TYPE_DF
:
578 case BRW_REGISTER_TYPE_HF
:
579 assert(!"unimplemented: abs DF/HF immediate");
585 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
588 const nir_shader
*shader
,
589 struct brw_stage_prog_data
*stage_prog_data
)
590 : compiler(compiler
),
592 devinfo(compiler
->devinfo
),
594 stage_prog_data(stage_prog_data
),
599 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
600 stage_name
= _mesa_shader_stage_to_string(stage
);
601 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
605 backend_reg::equals(const backend_reg
&r
) const
607 return memcmp((brw_reg
*)this, (brw_reg
*)&r
, sizeof(brw_reg
)) == 0 &&
608 reg_offset
== r
.reg_offset
;
612 backend_reg::is_zero() const
621 backend_reg::is_one() const
626 return type
== BRW_REGISTER_TYPE_F
632 backend_reg::is_negative_one() const
638 case BRW_REGISTER_TYPE_F
:
640 case BRW_REGISTER_TYPE_D
:
648 backend_reg::is_null() const
650 return file
== ARF
&& nr
== BRW_ARF_NULL
;
655 backend_reg::is_accumulator() const
657 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
661 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
663 return (file
== r
.file
&&
665 reg_offset
>= r
.reg_offset
&&
666 reg_offset
< r
.reg_offset
+ n
);
670 backend_instruction::is_commutative() const
678 case SHADER_OPCODE_MULH
:
681 /* MIN and MAX are commutative. */
682 if (conditional_mod
== BRW_CONDITIONAL_GE
||
683 conditional_mod
== BRW_CONDITIONAL_L
) {
693 backend_instruction::is_3src() const
695 return ::is_3src(opcode
);
699 backend_instruction::is_tex() const
701 return (opcode
== SHADER_OPCODE_TEX
||
702 opcode
== FS_OPCODE_TXB
||
703 opcode
== SHADER_OPCODE_TXD
||
704 opcode
== SHADER_OPCODE_TXF
||
705 opcode
== SHADER_OPCODE_TXF_CMS
||
706 opcode
== SHADER_OPCODE_TXF_CMS_W
||
707 opcode
== SHADER_OPCODE_TXF_UMS
||
708 opcode
== SHADER_OPCODE_TXF_MCS
||
709 opcode
== SHADER_OPCODE_TXL
||
710 opcode
== SHADER_OPCODE_TXS
||
711 opcode
== SHADER_OPCODE_LOD
||
712 opcode
== SHADER_OPCODE_TG4
||
713 opcode
== SHADER_OPCODE_TG4_OFFSET
);
717 backend_instruction::is_math() const
719 return (opcode
== SHADER_OPCODE_RCP
||
720 opcode
== SHADER_OPCODE_RSQ
||
721 opcode
== SHADER_OPCODE_SQRT
||
722 opcode
== SHADER_OPCODE_EXP2
||
723 opcode
== SHADER_OPCODE_LOG2
||
724 opcode
== SHADER_OPCODE_SIN
||
725 opcode
== SHADER_OPCODE_COS
||
726 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
727 opcode
== SHADER_OPCODE_INT_REMAINDER
||
728 opcode
== SHADER_OPCODE_POW
);
732 backend_instruction::is_control_flow() const
736 case BRW_OPCODE_WHILE
:
738 case BRW_OPCODE_ELSE
:
739 case BRW_OPCODE_ENDIF
:
740 case BRW_OPCODE_BREAK
:
741 case BRW_OPCODE_CONTINUE
:
749 backend_instruction::can_do_source_mods() const
752 case BRW_OPCODE_ADDC
:
754 case BRW_OPCODE_BFI1
:
755 case BRW_OPCODE_BFI2
:
756 case BRW_OPCODE_BFREV
:
757 case BRW_OPCODE_CBIT
:
760 case BRW_OPCODE_SUBB
:
768 backend_instruction::can_do_saturate() const
778 case BRW_OPCODE_F16TO32
:
779 case BRW_OPCODE_F32TO16
:
780 case BRW_OPCODE_LINE
:
784 case BRW_OPCODE_MATH
:
787 case SHADER_OPCODE_MULH
:
789 case BRW_OPCODE_RNDD
:
790 case BRW_OPCODE_RNDE
:
791 case BRW_OPCODE_RNDU
:
792 case BRW_OPCODE_RNDZ
:
796 case FS_OPCODE_LINTERP
:
797 case SHADER_OPCODE_COS
:
798 case SHADER_OPCODE_EXP2
:
799 case SHADER_OPCODE_LOG2
:
800 case SHADER_OPCODE_POW
:
801 case SHADER_OPCODE_RCP
:
802 case SHADER_OPCODE_RSQ
:
803 case SHADER_OPCODE_SIN
:
804 case SHADER_OPCODE_SQRT
:
812 backend_instruction::can_do_cmod() const
816 case BRW_OPCODE_ADDC
:
821 case BRW_OPCODE_CMPN
:
826 case BRW_OPCODE_F16TO32
:
827 case BRW_OPCODE_F32TO16
:
829 case BRW_OPCODE_LINE
:
833 case BRW_OPCODE_MACH
:
840 case BRW_OPCODE_RNDD
:
841 case BRW_OPCODE_RNDE
:
842 case BRW_OPCODE_RNDU
:
843 case BRW_OPCODE_RNDZ
:
844 case BRW_OPCODE_SAD2
:
845 case BRW_OPCODE_SADA2
:
848 case BRW_OPCODE_SUBB
:
850 case FS_OPCODE_CINTERP
:
851 case FS_OPCODE_LINTERP
:
859 backend_instruction::reads_accumulator_implicitly() const
863 case BRW_OPCODE_MACH
:
864 case BRW_OPCODE_SADA2
:
872 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
874 return writes_accumulator
||
876 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
877 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
878 opcode
!= FS_OPCODE_CINTERP
)));
882 backend_instruction::has_side_effects() const
885 case SHADER_OPCODE_UNTYPED_ATOMIC
:
886 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
887 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
888 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
889 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
890 case SHADER_OPCODE_TYPED_ATOMIC
:
891 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
892 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
893 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
894 case SHADER_OPCODE_MEMORY_FENCE
:
895 case SHADER_OPCODE_URB_WRITE_SIMD8
:
896 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
897 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
898 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
899 case FS_OPCODE_FB_WRITE
:
900 case SHADER_OPCODE_BARRIER
:
901 case TCS_OPCODE_URB_WRITE
:
902 case TCS_OPCODE_RELEASE_INPUT
:
910 backend_instruction::is_volatile() const
913 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
914 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
915 case SHADER_OPCODE_TYPED_SURFACE_READ
:
916 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
925 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
928 foreach_inst_in_block (backend_instruction
, i
, block
) {
938 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
940 for (bblock_t
*block_iter
= start_block
->next();
941 !block_iter
->link
.is_tail_sentinel();
942 block_iter
= block_iter
->next()) {
943 block_iter
->start_ip
+= ip_adjustment
;
944 block_iter
->end_ip
+= ip_adjustment
;
949 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
951 assert(this != inst
);
953 if (!this->is_head_sentinel())
954 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
958 adjust_later_block_ips(block
, 1);
960 exec_node::insert_after(inst
);
964 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
966 assert(this != inst
);
968 if (!this->is_tail_sentinel())
969 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
973 adjust_later_block_ips(block
, 1);
975 exec_node::insert_before(inst
);
979 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
981 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
983 unsigned num_inst
= list
->length();
985 block
->end_ip
+= num_inst
;
987 adjust_later_block_ips(block
, num_inst
);
989 exec_node::insert_before(list
);
993 backend_instruction::remove(bblock_t
*block
)
995 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
997 adjust_later_block_ips(block
, -1);
999 if (block
->start_ip
== block
->end_ip
) {
1000 block
->cfg
->remove_block(block
);
1005 exec_node::remove();
1009 backend_shader::dump_instructions()
1011 dump_instructions(NULL
);
1015 backend_shader::dump_instructions(const char *name
)
1017 FILE *file
= stderr
;
1018 if (name
&& geteuid() != 0) {
1019 file
= fopen(name
, "w");
1026 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1027 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1028 fprintf(file
, "%4d: ", ip
++);
1029 dump_instruction(inst
, file
);
1033 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1034 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1035 fprintf(file
, "%4d: ", ip
++);
1036 dump_instruction(inst
, file
);
1040 if (file
!= stderr
) {
1046 backend_shader::calculate_cfg()
1050 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1054 * Sets up the starting offsets for the groups of binding table entries
1055 * commong to all pipeline stages.
1057 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1058 * unused but also make sure that addition of small offsets to them will
1059 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1062 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
1063 const struct brw_device_info
*devinfo
,
1064 const struct gl_shader_program
*shader_prog
,
1065 const struct gl_program
*prog
,
1066 struct brw_stage_prog_data
*stage_prog_data
,
1067 uint32_t next_binding_table_offset
)
1069 const struct gl_shader
*shader
= NULL
;
1070 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1073 shader
= shader_prog
->_LinkedShaders
[stage
];
1075 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1076 next_binding_table_offset
+= num_textures
;
1079 assert(shader
->NumUniformBlocks
<= BRW_MAX_UBO
);
1080 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1081 next_binding_table_offset
+= shader
->NumUniformBlocks
;
1083 assert(shader
->NumShaderStorageBlocks
<= BRW_MAX_SSBO
);
1084 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
1085 next_binding_table_offset
+= shader
->NumShaderStorageBlocks
;
1087 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1088 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
1091 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1092 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1093 next_binding_table_offset
++;
1095 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1098 if (prog
->UsesGather
) {
1099 if (devinfo
->gen
>= 8) {
1100 stage_prog_data
->binding_table
.gather_texture_start
=
1101 stage_prog_data
->binding_table
.texture_start
;
1103 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1104 next_binding_table_offset
+= num_textures
;
1107 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1110 if (shader
&& shader
->NumAtomicBuffers
) {
1111 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1112 next_binding_table_offset
+= shader
->NumAtomicBuffers
;
1114 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1117 if (shader
&& shader
->NumImages
) {
1118 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1119 next_binding_table_offset
+= shader
->NumImages
;
1121 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1124 /* This may or may not be used depending on how the compile goes. */
1125 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1126 next_binding_table_offset
++;
1128 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1130 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1134 setup_vec4_uniform_value(const gl_constant_value
**params
,
1135 const gl_constant_value
*values
,
1138 static const gl_constant_value zero
= { 0 };
1140 for (unsigned i
= 0; i
< n
; ++i
)
1141 params
[i
] = &values
[i
];
1143 for (unsigned i
= n
; i
< 4; ++i
)
1148 brw_setup_image_uniform_values(gl_shader_stage stage
,
1149 struct brw_stage_prog_data
*stage_prog_data
,
1150 unsigned param_start_index
,
1151 const gl_uniform_storage
*storage
)
1153 const gl_constant_value
**param
=
1154 &stage_prog_data
->param
[param_start_index
];
1156 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1157 const unsigned image_idx
= storage
->opaque
[stage
].index
+ i
;
1158 const brw_image_param
*image_param
=
1159 &stage_prog_data
->image_param
[image_idx
];
1161 /* Upload the brw_image_param structure. The order is expected to match
1162 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1164 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1165 (const gl_constant_value
*)&image_param
->surface_idx
, 1);
1166 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1167 (const gl_constant_value
*)image_param
->offset
, 2);
1168 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1169 (const gl_constant_value
*)image_param
->size
, 3);
1170 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1171 (const gl_constant_value
*)image_param
->stride
, 4);
1172 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1173 (const gl_constant_value
*)image_param
->tiling
, 3);
1174 setup_vec4_uniform_value(param
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1175 (const gl_constant_value
*)image_param
->swizzling
, 2);
1176 param
+= BRW_IMAGE_PARAM_SIZE
;
1178 brw_mark_surface_used(
1180 stage_prog_data
->binding_table
.image_start
+ image_idx
);
1185 * Decide which set of clip planes should be used when clipping via
1186 * gl_Position or gl_ClipVertex.
1188 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
)
1190 if (ctx
->_Shader
->CurrentProgram
[MESA_SHADER_VERTEX
]) {
1191 /* There is currently a GLSL vertex shader, so clip according to GLSL
1192 * rules, which means compare gl_ClipVertex (or gl_Position, if
1193 * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1194 * that were stored in EyeUserPlane at the time the clip planes were
1197 return ctx
->Transform
.EyeUserPlane
;
1199 /* Either we are using fixed function or an ARB vertex program. In
1200 * either case the clip planes are going to be compared against
1201 * gl_Position (which is in clip coordinates) so we have to clip using
1202 * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1205 return ctx
->Transform
._ClipUserPlane
;
1209 extern "C" const unsigned *
1210 brw_compile_tes(const struct brw_compiler
*compiler
,
1213 const struct brw_tes_prog_key
*key
,
1214 struct brw_tes_prog_data
*prog_data
,
1215 const nir_shader
*src_shader
,
1216 struct gl_shader_program
*shader_prog
,
1217 int shader_time_index
,
1218 unsigned *final_assembly_size
,
1221 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
1222 struct gl_shader
*shader
=
1223 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
];
1224 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1226 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1227 nir
->info
.inputs_read
= key
->inputs_read
;
1228 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1230 struct brw_vue_map input_vue_map
;
1231 brw_compute_tess_vue_map(&input_vue_map
,
1232 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
1233 nir
->info
.patch_inputs_read
);
1235 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
1236 brw_nir_lower_tes_inputs(nir
, &input_vue_map
);
1237 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1238 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
1240 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1241 nir
->info
.outputs_written
,
1242 nir
->info
.separate_shader
);
1244 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1246 assert(output_size_bytes
>= 1);
1247 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1249 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1253 /* URB entry sizes are stored as a multiple of 64 bytes. */
1254 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1256 bool need_patch_header
= nir
->info
.system_values_read
&
1257 (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER
) |
1258 BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER
));
1260 /* The TES will pull most inputs using URB read messages.
1262 * However, we push the patch header for TessLevel factors when required,
1263 * as it's a tiny amount of extra data.
1265 prog_data
->base
.urb_read_length
= need_patch_header
? 1 : 0;
1267 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1268 fprintf(stderr
, "TES Input ");
1269 brw_print_vue_map(stderr
, &input_vue_map
);
1270 fprintf(stderr
, "TES Output ");
1271 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1275 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1276 &prog_data
->base
.base
, shader
->Program
, nir
, 8,
1277 shader_time_index
, &input_vue_map
);
1280 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1284 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1286 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1287 &prog_data
->base
.base
, v
.promoted_constants
, false,
1288 MESA_SHADER_TESS_EVAL
);
1289 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1290 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1291 "%s tessellation evaluation shader %s",
1292 nir
->info
.label
? nir
->info
.label
1297 g
.generate_code(v
.cfg
, 8);
1299 return g
.get_assembly(final_assembly_size
);
1301 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1302 nir
, mem_ctx
, shader_time_index
);
1305 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1309 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1310 v
.dump_instructions();
1312 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1313 &prog_data
->base
, v
.cfg
,
1314 final_assembly_size
);