src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  88       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  89    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  90       devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false);
  91    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  92    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  93
  94    nir_shader_compiler_options *nir_options =
  95       rzalloc(compiler, nir_shader_compiler_options);
  96    nir_options->native_integers = true;
  97    /* In order to help allow for better CSE at the NIR level we tell NIR
  98     * to split all ffma instructions during opt_algebraic and we then
  99     * re-combine them as a later step.
 100     */
 101    nir_options->lower_ffma = true;
 102    nir_options->lower_sub = true;
 103    /* In the vec4 backend, our dpN instruction replicates its result to all
 104     * the components of a vec4.  We would like NIR to give us replicated fdot
 105     * instructions because it can optimize better for us.
 106     *
 107     * For the FS backend, it should be lowered away by the scalarizing pass so
 108     * we should never see fdot anyway.
 109     */
 110    nir_options->fdot_replicates = true;
 111
 112    /* We want the GLSL compiler to emit code that uses condition codes */
 113    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 114       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 115       compiler->glsl_compiler_options[i].MaxIfDepth =
 116          devinfo->gen < 6 ? 16 : UINT_MAX;
 117
 118       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 119       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 120       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 121       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 122       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 123       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 124
 125       bool is_scalar = compiler->scalar_stage[i];
 126
 127       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 128       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 129       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 130
 131       /* !ARB_gpu_shader5 */
 132       if (devinfo->gen < 7)
 133          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 134
 135       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 136
 137       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 138    }
 139
 140    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 141       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 142
 143    return compiler;
 144 }
 145
 146 struct gl_shader *
 147 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 148 {
 149    struct brw_shader *shader;
 150
 151    shader = rzalloc(NULL, struct brw_shader);
 152    if (shader) {
 153       shader->base.Type = type;
 154       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 155       shader->base.Name = name;
 156       _mesa_init_shader(ctx, &shader->base);
 157    }
 158
 159    return &shader->base;
 160 }
 161
 162 void
 163 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 164                       unsigned surf_index)
 165 {
 166    assert(surf_index < BRW_MAX_SURFACES);
 167
 168    prog_data->binding_table.size_bytes =
 169       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 170 }
 171
 172 enum brw_reg_type
 173 brw_type_for_base_type(const struct glsl_type *type)
 174 {
 175    switch (type->base_type) {
 176    case GLSL_TYPE_FLOAT:
 177       return BRW_REGISTER_TYPE_F;
 178    case GLSL_TYPE_INT:
 179    case GLSL_TYPE_BOOL:
 180    case GLSL_TYPE_SUBROUTINE:
 181       return BRW_REGISTER_TYPE_D;
 182    case GLSL_TYPE_UINT:
 183       return BRW_REGISTER_TYPE_UD;
 184    case GLSL_TYPE_ARRAY:
 185       return brw_type_for_base_type(type->fields.array);
 186    case GLSL_TYPE_STRUCT:
 187    case GLSL_TYPE_SAMPLER:
 188    case GLSL_TYPE_ATOMIC_UINT:
 189       /* These should be overridden with the type of the member when
 190        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 191        * way to trip up if we don't.
 192        */
 193       return BRW_REGISTER_TYPE_UD;
 194    case GLSL_TYPE_IMAGE:
 195       return BRW_REGISTER_TYPE_UD;
 196    case GLSL_TYPE_VOID:
 197    case GLSL_TYPE_ERROR:
 198    case GLSL_TYPE_INTERFACE:
 199    case GLSL_TYPE_DOUBLE:
 200       unreachable("not reached");
 201    }
 202
 203    return BRW_REGISTER_TYPE_F;
 204 }
 205
 206 enum brw_conditional_mod
 207 brw_conditional_for_comparison(unsigned int op)
 208 {
 209    switch (op) {
 210    case ir_binop_less:
 211       return BRW_CONDITIONAL_L;
 212    case ir_binop_greater:
 213       return BRW_CONDITIONAL_G;
 214    case ir_binop_lequal:
 215       return BRW_CONDITIONAL_LE;
 216    case ir_binop_gequal:
 217       return BRW_CONDITIONAL_GE;
 218    case ir_binop_equal:
 219    case ir_binop_all_equal: /* same as equal for scalars */
 220       return BRW_CONDITIONAL_Z;
 221    case ir_binop_nequal:
 222    case ir_binop_any_nequal: /* same as nequal for scalars */
 223       return BRW_CONDITIONAL_NZ;
 224    default:
 225       unreachable("not reached: bad operation for comparison");
 226    }
 227 }
 228
 229 uint32_t
 230 brw_math_function(enum opcode op)
 231 {
 232    switch (op) {
 233    case SHADER_OPCODE_RCP:
 234       return BRW_MATH_FUNCTION_INV;
 235    case SHADER_OPCODE_RSQ:
 236       return BRW_MATH_FUNCTION_RSQ;
 237    case SHADER_OPCODE_SQRT:
 238       return BRW_MATH_FUNCTION_SQRT;
 239    case SHADER_OPCODE_EXP2:
 240       return BRW_MATH_FUNCTION_EXP;
 241    case SHADER_OPCODE_LOG2:
 242       return BRW_MATH_FUNCTION_LOG;
 243    case SHADER_OPCODE_POW:
 244       return BRW_MATH_FUNCTION_POW;
 245    case SHADER_OPCODE_SIN:
 246       return BRW_MATH_FUNCTION_SIN;
 247    case SHADER_OPCODE_COS:
 248       return BRW_MATH_FUNCTION_COS;
 249    case SHADER_OPCODE_INT_QUOTIENT:
 250       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 251    case SHADER_OPCODE_INT_REMAINDER:
 252       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 253    default:
 254       unreachable("not reached: unknown math function");
 255    }
 256 }
 257
 258 uint32_t
 259 brw_texture_offset(int *offsets, unsigned num_components)
 260 {
 261    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 262
 263    /* Combine all three offsets into a single unsigned dword:
 264     *
 265     *    bits 11:8 - U Offset (X component)
 266     *    bits  7:4 - V Offset (Y component)
 267     *    bits  3:0 - R Offset (Z component)
 268     */
 269    unsigned offset_bits = 0;
 270    for (unsigned i = 0; i < num_components; i++) {
 271       const unsigned shift = 4 * (2 - i);
 272       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 273    }
 274    return offset_bits;
 275 }
 276
 277 const char *
 278 brw_instruction_name(enum opcode op)
 279 {
 280    switch (op) {
 281    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 282       assert(opcode_descs[op].name);
 283       return opcode_descs[op].name;
 284    case FS_OPCODE_FB_WRITE:
 285       return "fb_write";
 286    case FS_OPCODE_FB_WRITE_LOGICAL:
 287       return "fb_write_logical";
 288    case FS_OPCODE_PACK_STENCIL_REF:
 289       return "pack_stencil_ref";
 290    case FS_OPCODE_BLORP_FB_WRITE:
 291       return "blorp_fb_write";
 292    case FS_OPCODE_REP_FB_WRITE:
 293       return "rep_fb_write";
 294
 295    case SHADER_OPCODE_RCP:
 296       return "rcp";
 297    case SHADER_OPCODE_RSQ:
 298       return "rsq";
 299    case SHADER_OPCODE_SQRT:
 300       return "sqrt";
 301    case SHADER_OPCODE_EXP2:
 302       return "exp2";
 303    case SHADER_OPCODE_LOG2:
 304       return "log2";
 305    case SHADER_OPCODE_POW:
 306       return "pow";
 307    case SHADER_OPCODE_INT_QUOTIENT:
 308       return "int_quot";
 309    case SHADER_OPCODE_INT_REMAINDER:
 310       return "int_rem";
 311    case SHADER_OPCODE_SIN:
 312       return "sin";
 313    case SHADER_OPCODE_COS:
 314       return "cos";
 315
 316    case SHADER_OPCODE_TEX:
 317       return "tex";
 318    case SHADER_OPCODE_TEX_LOGICAL:
 319       return "tex_logical";
 320    case SHADER_OPCODE_TXD:
 321       return "txd";
 322    case SHADER_OPCODE_TXD_LOGICAL:
 323       return "txd_logical";
 324    case SHADER_OPCODE_TXF:
 325       return "txf";
 326    case SHADER_OPCODE_TXF_LOGICAL:
 327       return "txf_logical";
 328    case SHADER_OPCODE_TXL:
 329       return "txl";
 330    case SHADER_OPCODE_TXL_LOGICAL:
 331       return "txl_logical";
 332    case SHADER_OPCODE_TXS:
 333       return "txs";
 334    case SHADER_OPCODE_TXS_LOGICAL:
 335       return "txs_logical";
 336    case FS_OPCODE_TXB:
 337       return "txb";
 338    case FS_OPCODE_TXB_LOGICAL:
 339       return "txb_logical";
 340    case SHADER_OPCODE_TXF_CMS:
 341       return "txf_cms";
 342    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 343       return "txf_cms_logical";
 344    case SHADER_OPCODE_TXF_CMS_W:
 345       return "txf_cms_w";
 346    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 347       return "txf_cms_w_logical";
 348    case SHADER_OPCODE_TXF_UMS:
 349       return "txf_ums";
 350    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 351       return "txf_ums_logical";
 352    case SHADER_OPCODE_TXF_MCS:
 353       return "txf_mcs";
 354    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 355       return "txf_mcs_logical";
 356    case SHADER_OPCODE_LOD:
 357       return "lod";
 358    case SHADER_OPCODE_LOD_LOGICAL:
 359       return "lod_logical";
 360    case SHADER_OPCODE_TG4:
 361       return "tg4";
 362    case SHADER_OPCODE_TG4_LOGICAL:
 363       return "tg4_logical";
 364    case SHADER_OPCODE_TG4_OFFSET:
 365       return "tg4_offset";
 366    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 367       return "tg4_offset_logical";
 368    case SHADER_OPCODE_SAMPLEINFO:
 369       return "sampleinfo";
 370
 371    case SHADER_OPCODE_SHADER_TIME_ADD:
 372       return "shader_time_add";
 373
 374    case SHADER_OPCODE_UNTYPED_ATOMIC:
 375       return "untyped_atomic";
 376    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 377       return "untyped_atomic_logical";
 378    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 379       return "untyped_surface_read";
 380    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 381       return "untyped_surface_read_logical";
 382    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 383       return "untyped_surface_write";
 384    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 385       return "untyped_surface_write_logical";
 386    case SHADER_OPCODE_TYPED_ATOMIC:
 387       return "typed_atomic";
 388    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 389       return "typed_atomic_logical";
 390    case SHADER_OPCODE_TYPED_SURFACE_READ:
 391       return "typed_surface_read";
 392    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 393       return "typed_surface_read_logical";
 394    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 395       return "typed_surface_write";
 396    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 397       return "typed_surface_write_logical";
 398    case SHADER_OPCODE_MEMORY_FENCE:
 399       return "memory_fence";
 400
 401    case SHADER_OPCODE_LOAD_PAYLOAD:
 402       return "load_payload";
 403
 404    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 405       return "gen4_scratch_read";
 406    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 407       return "gen4_scratch_write";
 408    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 409       return "gen7_scratch_read";
 410    case SHADER_OPCODE_URB_WRITE_SIMD8:
 411       return "gen8_urb_write_simd8";
 412    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 413       return "gen8_urb_write_simd8_per_slot";
 414    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 415       return "gen8_urb_write_simd8_masked";
 416    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 417       return "gen8_urb_write_simd8_masked_per_slot";
 418    case SHADER_OPCODE_URB_READ_SIMD8:
 419       return "urb_read_simd8";
 420    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 421       return "urb_read_simd8_per_slot";
 422
 423    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 424       return "find_live_channel";
 425    case SHADER_OPCODE_BROADCAST:
 426       return "broadcast";
 427
 428    case VEC4_OPCODE_MOV_BYTES:
 429       return "mov_bytes";
 430    case VEC4_OPCODE_PACK_BYTES:
 431       return "pack_bytes";
 432    case VEC4_OPCODE_UNPACK_UNIFORM:
 433       return "unpack_uniform";
 434
 435    case FS_OPCODE_DDX_COARSE:
 436       return "ddx_coarse";
 437    case FS_OPCODE_DDX_FINE:
 438       return "ddx_fine";
 439    case FS_OPCODE_DDY_COARSE:
 440       return "ddy_coarse";
 441    case FS_OPCODE_DDY_FINE:
 442       return "ddy_fine";
 443
 444    case FS_OPCODE_CINTERP:
 445       return "cinterp";
 446    case FS_OPCODE_LINTERP:
 447       return "linterp";
 448
 449    case FS_OPCODE_PIXEL_X:
 450       return "pixel_x";
 451    case FS_OPCODE_PIXEL_Y:
 452       return "pixel_y";
 453
 454    case FS_OPCODE_GET_BUFFER_SIZE:
 455       return "fs_get_buffer_size";
 456
 457    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 458       return "uniform_pull_const";
 459    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 460       return "uniform_pull_const_gen7";
 461    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 462       return "varying_pull_const";
 463    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 464       return "varying_pull_const_gen7";
 465
 466    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 467       return "mov_dispatch_to_flags";
 468    case FS_OPCODE_DISCARD_JUMP:
 469       return "discard_jump";
 470
 471    case FS_OPCODE_SET_SAMPLE_ID:
 472       return "set_sample_id";
 473    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 474       return "set_simd4x2_offset";
 475
 476    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 477       return "pack_half_2x16_split";
 478    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 479       return "unpack_half_2x16_split_x";
 480    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 481       return "unpack_half_2x16_split_y";
 482
 483    case FS_OPCODE_PLACEHOLDER_HALT:
 484       return "placeholder_halt";
 485
 486    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 487       return "interp_centroid";
 488    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 489       return "interp_sample";
 490    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 491       return "interp_shared_offset";
 492    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 493       return "interp_per_slot_offset";
 494
 495    case VS_OPCODE_URB_WRITE:
 496       return "vs_urb_write";
 497    case VS_OPCODE_PULL_CONSTANT_LOAD:
 498       return "pull_constant_load";
 499    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 500       return "pull_constant_load_gen7";
 501
 502    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 503       return "set_simd4x2_header_gen9";
 504
 505    case VS_OPCODE_GET_BUFFER_SIZE:
 506       return "vs_get_buffer_size";
 507
 508    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 509       return "unpack_flags_simd4x2";
 510
 511    case GS_OPCODE_URB_WRITE:
 512       return "gs_urb_write";
 513    case GS_OPCODE_URB_WRITE_ALLOCATE:
 514       return "gs_urb_write_allocate";
 515    case GS_OPCODE_THREAD_END:
 516       return "gs_thread_end";
 517    case GS_OPCODE_SET_WRITE_OFFSET:
 518       return "set_write_offset";
 519    case GS_OPCODE_SET_VERTEX_COUNT:
 520       return "set_vertex_count";
 521    case GS_OPCODE_SET_DWORD_2:
 522       return "set_dword_2";
 523    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 524       return "prepare_channel_masks";
 525    case GS_OPCODE_SET_CHANNEL_MASKS:
 526       return "set_channel_masks";
 527    case GS_OPCODE_GET_INSTANCE_ID:
 528       return "get_instance_id";
 529    case GS_OPCODE_FF_SYNC:
 530       return "ff_sync";
 531    case GS_OPCODE_SET_PRIMITIVE_ID:
 532       return "set_primitive_id";
 533    case GS_OPCODE_SVB_WRITE:
 534       return "gs_svb_write";
 535    case GS_OPCODE_SVB_SET_DST_INDEX:
 536       return "gs_svb_set_dst_index";
 537    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 538       return "gs_ff_sync_set_primitives";
 539    case CS_OPCODE_CS_TERMINATE:
 540       return "cs_terminate";
 541    case SHADER_OPCODE_BARRIER:
 542       return "barrier";
 543    case SHADER_OPCODE_MULH:
 544       return "mulh";
 545    case SHADER_OPCODE_MOV_INDIRECT:
 546       return "mov_indirect";
 547    }
 548
 549    unreachable("not reached");
 550 }
 551
 552 bool
 553 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 554 {
 555    union {
 556       unsigned ud;
 557       int d;
 558       float f;
 559    } imm = { reg->ud }, sat_imm = { 0 };
 560
 561    switch (type) {
 562    case BRW_REGISTER_TYPE_UD:
 563    case BRW_REGISTER_TYPE_D:
 564    case BRW_REGISTER_TYPE_UW:
 565    case BRW_REGISTER_TYPE_W:
 566    case BRW_REGISTER_TYPE_UQ:
 567    case BRW_REGISTER_TYPE_Q:
 568       /* Nothing to do. */
 569       return false;
 570    case BRW_REGISTER_TYPE_F:
 571       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 572       break;
 573    case BRW_REGISTER_TYPE_UB:
 574    case BRW_REGISTER_TYPE_B:
 575       unreachable("no UB/B immediates");
 576    case BRW_REGISTER_TYPE_V:
 577    case BRW_REGISTER_TYPE_UV:
 578    case BRW_REGISTER_TYPE_VF:
 579       unreachable("unimplemented: saturate vector immediate");
 580    case BRW_REGISTER_TYPE_DF:
 581    case BRW_REGISTER_TYPE_HF:
 582       unreachable("unimplemented: saturate DF/HF immediate");
 583    }
 584
 585    if (imm.ud != sat_imm.ud) {
 586       reg->ud = sat_imm.ud;
 587       return true;
 588    }
 589    return false;
 590 }
 591
 592 bool
 593 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 594 {
 595    switch (type) {
 596    case BRW_REGISTER_TYPE_D:
 597    case BRW_REGISTER_TYPE_UD:
 598       reg->d = -reg->d;
 599       return true;
 600    case BRW_REGISTER_TYPE_W:
 601    case BRW_REGISTER_TYPE_UW:
 602       reg->d = -(int16_t)reg->ud;
 603       return true;
 604    case BRW_REGISTER_TYPE_F:
 605       reg->f = -reg->f;
 606       return true;
 607    case BRW_REGISTER_TYPE_VF:
 608       reg->ud ^= 0x80808080;
 609       return true;
 610    case BRW_REGISTER_TYPE_UB:
 611    case BRW_REGISTER_TYPE_B:
 612       unreachable("no UB/B immediates");
 613    case BRW_REGISTER_TYPE_UV:
 614    case BRW_REGISTER_TYPE_V:
 615       assert(!"unimplemented: negate UV/V immediate");
 616    case BRW_REGISTER_TYPE_UQ:
 617    case BRW_REGISTER_TYPE_Q:
 618       assert(!"unimplemented: negate UQ/Q immediate");
 619    case BRW_REGISTER_TYPE_DF:
 620    case BRW_REGISTER_TYPE_HF:
 621       assert(!"unimplemented: negate DF/HF immediate");
 622    }
 623
 624    return false;
 625 }
 626
 627 bool
 628 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 629 {
 630    switch (type) {
 631    case BRW_REGISTER_TYPE_D:
 632       reg->d = abs(reg->d);
 633       return true;
 634    case BRW_REGISTER_TYPE_W:
 635       reg->d = abs((int16_t)reg->ud);
 636       return true;
 637    case BRW_REGISTER_TYPE_F:
 638       reg->f = fabsf(reg->f);
 639       return true;
 640    case BRW_REGISTER_TYPE_VF:
 641       reg->ud &= ~0x80808080;
 642       return true;
 643    case BRW_REGISTER_TYPE_UB:
 644    case BRW_REGISTER_TYPE_B:
 645       unreachable("no UB/B immediates");
 646    case BRW_REGISTER_TYPE_UQ:
 647    case BRW_REGISTER_TYPE_UD:
 648    case BRW_REGISTER_TYPE_UW:
 649    case BRW_REGISTER_TYPE_UV:
 650       /* Presumably the absolute value modifier on an unsigned source is a
 651        * nop, but it would be nice to confirm.
 652        */
 653       assert(!"unimplemented: abs unsigned immediate");
 654    case BRW_REGISTER_TYPE_V:
 655       assert(!"unimplemented: abs V immediate");
 656    case BRW_REGISTER_TYPE_Q:
 657       assert(!"unimplemented: abs Q immediate");
 658    case BRW_REGISTER_TYPE_DF:
 659    case BRW_REGISTER_TYPE_HF:
 660       assert(!"unimplemented: abs DF/HF immediate");
 661    }
 662
 663    return false;
 664 }
 665
 666 backend_shader::backend_shader(const struct brw_compiler *compiler,
 667                                void *log_data,
 668                                void *mem_ctx,
 669                                const nir_shader *shader,
 670                                struct brw_stage_prog_data *stage_prog_data)
 671    : compiler(compiler),
 672      log_data(log_data),
 673      devinfo(compiler->devinfo),
 674      nir(shader),
 675      stage_prog_data(stage_prog_data),
 676      mem_ctx(mem_ctx),
 677      cfg(NULL),
 678      stage(shader->stage)
 679 {
 680    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 681    stage_name = _mesa_shader_stage_to_string(stage);
 682    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 683 }
 684
 685 bool
 686 backend_reg::is_zero() const
 687 {
 688    if (file != IMM)
 689       return false;
 690
 691    return d == 0;
 692 }
 693
 694 bool
 695 backend_reg::is_one() const
 696 {
 697    if (file != IMM)
 698       return false;
 699
 700    return type == BRW_REGISTER_TYPE_F
 701           ? f == 1.0
 702           : d == 1;
 703 }
 704
 705 bool
 706 backend_reg::is_negative_one() const
 707 {
 708    if (file != IMM)
 709       return false;
 710
 711    switch (type) {
 712    case BRW_REGISTER_TYPE_F:
 713       return f == -1.0;
 714    case BRW_REGISTER_TYPE_D:
 715       return d == -1;
 716    default:
 717       return false;
 718    }
 719 }
 720
 721 bool
 722 backend_reg::is_null() const
 723 {
 724    return file == ARF && nr == BRW_ARF_NULL;
 725 }
 726
 727
 728 bool
 729 backend_reg::is_accumulator() const
 730 {
 731    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 732 }
 733
 734 bool
 735 backend_reg::in_range(const backend_reg &r, unsigned n) const
 736 {
 737    return (file == r.file &&
 738            nr == r.nr &&
 739            reg_offset >= r.reg_offset &&
 740            reg_offset < r.reg_offset + n);
 741 }
 742
 743 bool
 744 backend_instruction::is_commutative() const
 745 {
 746    switch (opcode) {
 747    case BRW_OPCODE_AND:
 748    case BRW_OPCODE_OR:
 749    case BRW_OPCODE_XOR:
 750    case BRW_OPCODE_ADD:
 751    case BRW_OPCODE_MUL:
 752    case SHADER_OPCODE_MULH:
 753       return true;
 754    case BRW_OPCODE_SEL:
 755       /* MIN and MAX are commutative. */
 756       if (conditional_mod == BRW_CONDITIONAL_GE ||
 757           conditional_mod == BRW_CONDITIONAL_L) {
 758          return true;
 759       }
 760       /* fallthrough */
 761    default:
 762       return false;
 763    }
 764 }
 765
 766 bool
 767 backend_instruction::is_3src() const
 768 {
 769    return ::is_3src(opcode);
 770 }
 771
 772 bool
 773 backend_instruction::is_tex() const
 774 {
 775    return (opcode == SHADER_OPCODE_TEX ||
 776            opcode == FS_OPCODE_TXB ||
 777            opcode == SHADER_OPCODE_TXD ||
 778            opcode == SHADER_OPCODE_TXF ||
 779            opcode == SHADER_OPCODE_TXF_CMS ||
 780            opcode == SHADER_OPCODE_TXF_CMS_W ||
 781            opcode == SHADER_OPCODE_TXF_UMS ||
 782            opcode == SHADER_OPCODE_TXF_MCS ||
 783            opcode == SHADER_OPCODE_TXL ||
 784            opcode == SHADER_OPCODE_TXS ||
 785            opcode == SHADER_OPCODE_LOD ||
 786            opcode == SHADER_OPCODE_TG4 ||
 787            opcode == SHADER_OPCODE_TG4_OFFSET);
 788 }
 789
 790 bool
 791 backend_instruction::is_math() const
 792 {
 793    return (opcode == SHADER_OPCODE_RCP ||
 794            opcode == SHADER_OPCODE_RSQ ||
 795            opcode == SHADER_OPCODE_SQRT ||
 796            opcode == SHADER_OPCODE_EXP2 ||
 797            opcode == SHADER_OPCODE_LOG2 ||
 798            opcode == SHADER_OPCODE_SIN ||
 799            opcode == SHADER_OPCODE_COS ||
 800            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 801            opcode == SHADER_OPCODE_INT_REMAINDER ||
 802            opcode == SHADER_OPCODE_POW);
 803 }
 804
 805 bool
 806 backend_instruction::is_control_flow() const
 807 {
 808    switch (opcode) {
 809    case BRW_OPCODE_DO:
 810    case BRW_OPCODE_WHILE:
 811    case BRW_OPCODE_IF:
 812    case BRW_OPCODE_ELSE:
 813    case BRW_OPCODE_ENDIF:
 814    case BRW_OPCODE_BREAK:
 815    case BRW_OPCODE_CONTINUE:
 816       return true;
 817    default:
 818       return false;
 819    }
 820 }
 821
 822 bool
 823 backend_instruction::can_do_source_mods() const
 824 {
 825    switch (opcode) {
 826    case BRW_OPCODE_ADDC:
 827    case BRW_OPCODE_BFE:
 828    case BRW_OPCODE_BFI1:
 829    case BRW_OPCODE_BFI2:
 830    case BRW_OPCODE_BFREV:
 831    case BRW_OPCODE_CBIT:
 832    case BRW_OPCODE_FBH:
 833    case BRW_OPCODE_FBL:
 834    case BRW_OPCODE_SUBB:
 835       return false;
 836    default:
 837       return true;
 838    }
 839 }
 840
 841 bool
 842 backend_instruction::can_do_saturate() const
 843 {
 844    switch (opcode) {
 845    case BRW_OPCODE_ADD:
 846    case BRW_OPCODE_ASR:
 847    case BRW_OPCODE_AVG:
 848    case BRW_OPCODE_DP2:
 849    case BRW_OPCODE_DP3:
 850    case BRW_OPCODE_DP4:
 851    case BRW_OPCODE_DPH:
 852    case BRW_OPCODE_F16TO32:
 853    case BRW_OPCODE_F32TO16:
 854    case BRW_OPCODE_LINE:
 855    case BRW_OPCODE_LRP:
 856    case BRW_OPCODE_MAC:
 857    case BRW_OPCODE_MAD:
 858    case BRW_OPCODE_MATH:
 859    case BRW_OPCODE_MOV:
 860    case BRW_OPCODE_MUL:
 861    case SHADER_OPCODE_MULH:
 862    case BRW_OPCODE_PLN:
 863    case BRW_OPCODE_RNDD:
 864    case BRW_OPCODE_RNDE:
 865    case BRW_OPCODE_RNDU:
 866    case BRW_OPCODE_RNDZ:
 867    case BRW_OPCODE_SEL:
 868    case BRW_OPCODE_SHL:
 869    case BRW_OPCODE_SHR:
 870    case FS_OPCODE_LINTERP:
 871    case SHADER_OPCODE_COS:
 872    case SHADER_OPCODE_EXP2:
 873    case SHADER_OPCODE_LOG2:
 874    case SHADER_OPCODE_POW:
 875    case SHADER_OPCODE_RCP:
 876    case SHADER_OPCODE_RSQ:
 877    case SHADER_OPCODE_SIN:
 878    case SHADER_OPCODE_SQRT:
 879       return true;
 880    default:
 881       return false;
 882    }
 883 }
 884
 885 bool
 886 backend_instruction::can_do_cmod() const
 887 {
 888    switch (opcode) {
 889    case BRW_OPCODE_ADD:
 890    case BRW_OPCODE_ADDC:
 891    case BRW_OPCODE_AND:
 892    case BRW_OPCODE_ASR:
 893    case BRW_OPCODE_AVG:
 894    case BRW_OPCODE_CMP:
 895    case BRW_OPCODE_CMPN:
 896    case BRW_OPCODE_DP2:
 897    case BRW_OPCODE_DP3:
 898    case BRW_OPCODE_DP4:
 899    case BRW_OPCODE_DPH:
 900    case BRW_OPCODE_F16TO32:
 901    case BRW_OPCODE_F32TO16:
 902    case BRW_OPCODE_FRC:
 903    case BRW_OPCODE_LINE:
 904    case BRW_OPCODE_LRP:
 905    case BRW_OPCODE_LZD:
 906    case BRW_OPCODE_MAC:
 907    case BRW_OPCODE_MACH:
 908    case BRW_OPCODE_MAD:
 909    case BRW_OPCODE_MOV:
 910    case BRW_OPCODE_MUL:
 911    case BRW_OPCODE_NOT:
 912    case BRW_OPCODE_OR:
 913    case BRW_OPCODE_PLN:
 914    case BRW_OPCODE_RNDD:
 915    case BRW_OPCODE_RNDE:
 916    case BRW_OPCODE_RNDU:
 917    case BRW_OPCODE_RNDZ:
 918    case BRW_OPCODE_SAD2:
 919    case BRW_OPCODE_SADA2:
 920    case BRW_OPCODE_SHL:
 921    case BRW_OPCODE_SHR:
 922    case BRW_OPCODE_SUBB:
 923    case BRW_OPCODE_XOR:
 924    case FS_OPCODE_CINTERP:
 925    case FS_OPCODE_LINTERP:
 926       return true;
 927    default:
 928       return false;
 929    }
 930 }
 931
 932 bool
 933 backend_instruction::reads_accumulator_implicitly() const
 934 {
 935    switch (opcode) {
 936    case BRW_OPCODE_MAC:
 937    case BRW_OPCODE_MACH:
 938    case BRW_OPCODE_SADA2:
 939       return true;
 940    default:
 941       return false;
 942    }
 943 }
 944
 945 bool
 946 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 947 {
 948    return writes_accumulator ||
 949           (devinfo->gen < 6 &&
 950            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 951             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 952              opcode != FS_OPCODE_CINTERP)));
 953 }
 954
 955 bool
 956 backend_instruction::has_side_effects() const
 957 {
 958    switch (opcode) {
 959    case SHADER_OPCODE_UNTYPED_ATOMIC:
 960    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 961    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 962    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 963    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 964    case SHADER_OPCODE_TYPED_ATOMIC:
 965    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 966    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 967    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 968    case SHADER_OPCODE_MEMORY_FENCE:
 969    case SHADER_OPCODE_URB_WRITE_SIMD8:
 970    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 971    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 972    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 973    case FS_OPCODE_FB_WRITE:
 974    case SHADER_OPCODE_BARRIER:
 975       return true;
 976    default:
 977       return false;
 978    }
 979 }
 980
 981 bool
 982 backend_instruction::is_volatile() const
 983 {
 984    switch (opcode) {
 985    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 986    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 987    case SHADER_OPCODE_TYPED_SURFACE_READ:
 988    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 989       return true;
 990    default:
 991       return false;
 992    }
 993 }
 994
 995 #ifndef NDEBUG
 996 static bool
 997 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 998 {
 999    bool found = false;
1000    foreach_inst_in_block (backend_instruction, i, block) {
1001       if (inst == i) {
1002          found = true;
1003       }
1004    }
1005    return found;
1006 }
1007 #endif
1008
1009 static void
1010 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1011 {
1012    for (bblock_t *block_iter = start_block->next();
1013         !block_iter->link.is_tail_sentinel();
1014         block_iter = block_iter->next()) {
1015       block_iter->start_ip += ip_adjustment;
1016       block_iter->end_ip += ip_adjustment;
1017    }
1018 }
1019
1020 void
1021 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1022 {
1023    if (!this->is_head_sentinel())
1024       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1025
1026    block->end_ip++;
1027
1028    adjust_later_block_ips(block, 1);
1029
1030    exec_node::insert_after(inst);
1031 }
1032
1033 void
1034 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1035 {
1036    if (!this->is_tail_sentinel())
1037       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1038
1039    block->end_ip++;
1040
1041    adjust_later_block_ips(block, 1);
1042
1043    exec_node::insert_before(inst);
1044 }
1045
1046 void
1047 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1048 {
1049    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1050
1051    unsigned num_inst = list->length();
1052
1053    block->end_ip += num_inst;
1054
1055    adjust_later_block_ips(block, num_inst);
1056
1057    exec_node::insert_before(list);
1058 }
1059
1060 void
1061 backend_instruction::remove(bblock_t *block)
1062 {
1063    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1064
1065    adjust_later_block_ips(block, -1);
1066
1067    if (block->start_ip == block->end_ip) {
1068       block->cfg->remove_block(block);
1069    } else {
1070       block->end_ip--;
1071    }
1072
1073    exec_node::remove();
1074 }
1075
1076 void
1077 backend_shader::dump_instructions()
1078 {
1079    dump_instructions(NULL);
1080 }
1081
1082 void
1083 backend_shader::dump_instructions(const char *name)
1084 {
1085    FILE *file = stderr;
1086    if (name && geteuid() != 0) {
1087       file = fopen(name, "w");
1088       if (!file)
1089          file = stderr;
1090    }
1091
1092    if (cfg) {
1093       int ip = 0;
1094       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1095          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1096             fprintf(file, "%4d: ", ip++);
1097          dump_instruction(inst, file);
1098       }
1099    } else {
1100       int ip = 0;
1101       foreach_in_list(backend_instruction, inst, &instructions) {
1102          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1103             fprintf(file, "%4d: ", ip++);
1104          dump_instruction(inst, file);
1105       }
1106    }
1107
1108    if (file != stderr) {
1109       fclose(file);
1110    }
1111 }
1112
1113 void
1114 backend_shader::calculate_cfg()
1115 {
1116    if (this->cfg)
1117       return;
1118    cfg = new(mem_ctx) cfg_t(&this->instructions);
1119 }
1120
1121 void
1122 backend_shader::invalidate_cfg()
1123 {
1124    ralloc_free(this->cfg);
1125    this->cfg = NULL;
1126 }
1127
1128 /**
1129  * Sets up the starting offsets for the groups of binding table entries
1130  * commong to all pipeline stages.
1131  *
1132  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1133  * unused but also make sure that addition of small offsets to them will
1134  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1135  */
1136 void
1137 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1138                                         const struct brw_device_info *devinfo,
1139                                         const struct gl_shader_program *shader_prog,
1140                                         const struct gl_program *prog,
1141                                         struct brw_stage_prog_data *stage_prog_data,
1142                                         uint32_t next_binding_table_offset)
1143 {
1144    const struct gl_shader *shader = NULL;
1145    int num_textures = _mesa_fls(prog->SamplersUsed);
1146
1147    if (shader_prog)
1148       shader = shader_prog->_LinkedShaders[stage];
1149
1150    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1151    next_binding_table_offset += num_textures;
1152
1153    if (shader) {
1154       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1155       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1156       next_binding_table_offset += shader->NumUniformBlocks;
1157
1158       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1159       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1160       next_binding_table_offset += shader->NumShaderStorageBlocks;
1161    } else {
1162       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1163       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1164    }
1165
1166    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1167       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1168       next_binding_table_offset++;
1169    } else {
1170       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1171    }
1172
1173    if (prog->UsesGather) {
1174       if (devinfo->gen >= 8) {
1175          stage_prog_data->binding_table.gather_texture_start =
1176             stage_prog_data->binding_table.texture_start;
1177       } else {
1178          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1179          next_binding_table_offset += num_textures;
1180       }
1181    } else {
1182       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1183    }
1184
1185    if (shader && shader->NumAtomicBuffers) {
1186       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1187       next_binding_table_offset += shader->NumAtomicBuffers;
1188    } else {
1189       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1190    }
1191
1192    if (shader && shader->NumImages) {
1193       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1194       next_binding_table_offset += shader->NumImages;
1195    } else {
1196       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1197    }
1198
1199    /* This may or may not be used depending on how the compile goes. */
1200    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1201    next_binding_table_offset++;
1202
1203    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1204
1205    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1206 }
1207
1208 static void
1209 setup_vec4_uniform_value(const gl_constant_value **params,
1210                          const gl_constant_value *values,
1211                          unsigned n)
1212 {
1213    static const gl_constant_value zero = { 0 };
1214
1215    for (unsigned i = 0; i < n; ++i)
1216       params[i] = &values[i];
1217
1218    for (unsigned i = n; i < 4; ++i)
1219       params[i] = &zero;
1220 }
1221
1222 void
1223 brw_setup_image_uniform_values(gl_shader_stage stage,
1224                                struct brw_stage_prog_data *stage_prog_data,
1225                                unsigned param_start_index,
1226                                const gl_uniform_storage *storage)
1227 {
1228    const gl_constant_value **param =
1229       &stage_prog_data->param[param_start_index];
1230
1231    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1232       const unsigned image_idx = storage->opaque[stage].index + i;
1233       const brw_image_param *image_param =
1234          &stage_prog_data->image_param[image_idx];
1235
1236       /* Upload the brw_image_param structure.  The order is expected to match
1237        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1238        */
1239       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1240          (const gl_constant_value *)&image_param->surface_idx, 1);
1241       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1242          (const gl_constant_value *)image_param->offset, 2);
1243       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1244          (const gl_constant_value *)image_param->size, 3);
1245       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1246          (const gl_constant_value *)image_param->stride, 4);
1247       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1248          (const gl_constant_value *)image_param->tiling, 3);
1249       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1250          (const gl_constant_value *)image_param->swizzling, 2);
1251       param += BRW_IMAGE_PARAM_SIZE;
1252
1253       brw_mark_surface_used(
1254          stage_prog_data,
1255          stage_prog_data->binding_table.image_start + image_idx);
1256    }
1257 }
1258
1259 /**
1260  * Decide which set of clip planes should be used when clipping via
1261  * gl_Position or gl_ClipVertex.
1262  */
1263 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1264 {
1265    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1266       /* There is currently a GLSL vertex shader, so clip according to GLSL
1267        * rules, which means compare gl_ClipVertex (or gl_Position, if
1268        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1269        * that were stored in EyeUserPlane at the time the clip planes were
1270        * specified.
1271        */
1272       return ctx->Transform.EyeUserPlane;
1273    } else {
1274       /* Either we are using fixed function or an ARB vertex program.  In
1275        * either case the clip planes are going to be compared against
1276        * gl_Position (which is in clip coordinates) so we have to clip using
1277        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1278        * core.
1279        */
1280       return ctx->Transform._ClipUserPlane;
1281    }
1282 }
1283