src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "glsl/glsl_parser_extras.h"
  31 #include "main/shaderobj.h"
  32 #include "main/uniforms.h"
  33 #include "util/debug.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  88       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  89    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = false;
  90    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
  91       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
  92    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  93       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  94    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  95    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  96
  97    nir_shader_compiler_options *nir_options =
  98       rzalloc(compiler, nir_shader_compiler_options);
  99    nir_options->native_integers = true;
 100    /* In order to help allow for better CSE at the NIR level we tell NIR
 101     * to split all ffma instructions during opt_algebraic and we then
 102     * re-combine them as a later step.
 103     */
 104    nir_options->lower_ffma = true;
 105    nir_options->lower_sub = true;
 106    nir_options->lower_fdiv = true;
 107
 108    /* In the vec4 backend, our dpN instruction replicates its result to all
 109     * the components of a vec4.  We would like NIR to give us replicated fdot
 110     * instructions because it can optimize better for us.
 111     *
 112     * For the FS backend, it should be lowered away by the scalarizing pass so
 113     * we should never see fdot anyway.
 114     */
 115    nir_options->fdot_replicates = true;
 116
 117    /* We want the GLSL compiler to emit code that uses condition codes */
 118    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 119       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 120       compiler->glsl_compiler_options[i].MaxIfDepth =
 121          devinfo->gen < 6 ? 16 : UINT_MAX;
 122
 123       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 124       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 125       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 126       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 127       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 128       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 129
 130       bool is_scalar = compiler->scalar_stage[i];
 131
 132       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 133       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 134       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 135
 136       /* !ARB_gpu_shader5 */
 137       if (devinfo->gen < 7)
 138          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 139
 140       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 141
 142       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 143    }
 144
 145    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 146    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 147
 148    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 149       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 150
 151    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 152       .LowerShaderSharedVariables = true;
 153
 154    return compiler;
 155 }
 156
 157 extern "C" struct gl_shader *
 158 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 159 {
 160    struct brw_shader *shader;
 161
 162    shader = rzalloc(NULL, struct brw_shader);
 163    if (shader) {
 164       shader->base.Type = type;
 165       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 166       shader->base.Name = name;
 167       _mesa_init_shader(ctx, &shader->base);
 168    }
 169
 170    return &shader->base;
 171 }
 172
 173 extern "C" void
 174 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 175                       unsigned surf_index)
 176 {
 177    assert(surf_index < BRW_MAX_SURFACES);
 178
 179    prog_data->binding_table.size_bytes =
 180       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 181 }
 182
 183 enum brw_reg_type
 184 brw_type_for_base_type(const struct glsl_type *type)
 185 {
 186    switch (type->base_type) {
 187    case GLSL_TYPE_FLOAT:
 188       return BRW_REGISTER_TYPE_F;
 189    case GLSL_TYPE_INT:
 190    case GLSL_TYPE_BOOL:
 191    case GLSL_TYPE_SUBROUTINE:
 192       return BRW_REGISTER_TYPE_D;
 193    case GLSL_TYPE_UINT:
 194       return BRW_REGISTER_TYPE_UD;
 195    case GLSL_TYPE_ARRAY:
 196       return brw_type_for_base_type(type->fields.array);
 197    case GLSL_TYPE_STRUCT:
 198    case GLSL_TYPE_SAMPLER:
 199    case GLSL_TYPE_ATOMIC_UINT:
 200       /* These should be overridden with the type of the member when
 201        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 202        * way to trip up if we don't.
 203        */
 204       return BRW_REGISTER_TYPE_UD;
 205    case GLSL_TYPE_IMAGE:
 206       return BRW_REGISTER_TYPE_UD;
 207    case GLSL_TYPE_VOID:
 208    case GLSL_TYPE_ERROR:
 209    case GLSL_TYPE_INTERFACE:
 210    case GLSL_TYPE_DOUBLE:
 211    case GLSL_TYPE_FUNCTION:
 212       unreachable("not reached");
 213    }
 214
 215    return BRW_REGISTER_TYPE_F;
 216 }
 217
 218 enum brw_conditional_mod
 219 brw_conditional_for_comparison(unsigned int op)
 220 {
 221    switch (op) {
 222    case ir_binop_less:
 223       return BRW_CONDITIONAL_L;
 224    case ir_binop_greater:
 225       return BRW_CONDITIONAL_G;
 226    case ir_binop_lequal:
 227       return BRW_CONDITIONAL_LE;
 228    case ir_binop_gequal:
 229       return BRW_CONDITIONAL_GE;
 230    case ir_binop_equal:
 231    case ir_binop_all_equal: /* same as equal for scalars */
 232       return BRW_CONDITIONAL_Z;
 233    case ir_binop_nequal:
 234    case ir_binop_any_nequal: /* same as nequal for scalars */
 235       return BRW_CONDITIONAL_NZ;
 236    default:
 237       unreachable("not reached: bad operation for comparison");
 238    }
 239 }
 240
 241 uint32_t
 242 brw_math_function(enum opcode op)
 243 {
 244    switch (op) {
 245    case SHADER_OPCODE_RCP:
 246       return BRW_MATH_FUNCTION_INV;
 247    case SHADER_OPCODE_RSQ:
 248       return BRW_MATH_FUNCTION_RSQ;
 249    case SHADER_OPCODE_SQRT:
 250       return BRW_MATH_FUNCTION_SQRT;
 251    case SHADER_OPCODE_EXP2:
 252       return BRW_MATH_FUNCTION_EXP;
 253    case SHADER_OPCODE_LOG2:
 254       return BRW_MATH_FUNCTION_LOG;
 255    case SHADER_OPCODE_POW:
 256       return BRW_MATH_FUNCTION_POW;
 257    case SHADER_OPCODE_SIN:
 258       return BRW_MATH_FUNCTION_SIN;
 259    case SHADER_OPCODE_COS:
 260       return BRW_MATH_FUNCTION_COS;
 261    case SHADER_OPCODE_INT_QUOTIENT:
 262       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 263    case SHADER_OPCODE_INT_REMAINDER:
 264       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 265    default:
 266       unreachable("not reached: unknown math function");
 267    }
 268 }
 269
 270 uint32_t
 271 brw_texture_offset(int *offsets, unsigned num_components)
 272 {
 273    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 274
 275    /* Combine all three offsets into a single unsigned dword:
 276     *
 277     *    bits 11:8 - U Offset (X component)
 278     *    bits  7:4 - V Offset (Y component)
 279     *    bits  3:0 - R Offset (Z component)
 280     */
 281    unsigned offset_bits = 0;
 282    for (unsigned i = 0; i < num_components; i++) {
 283       const unsigned shift = 4 * (2 - i);
 284       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 285    }
 286    return offset_bits;
 287 }
 288
 289 const char *
 290 brw_instruction_name(enum opcode op)
 291 {
 292    switch (op) {
 293    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 294       assert(opcode_descs[op].name);
 295       return opcode_descs[op].name;
 296    case FS_OPCODE_FB_WRITE:
 297       return "fb_write";
 298    case FS_OPCODE_FB_WRITE_LOGICAL:
 299       return "fb_write_logical";
 300    case FS_OPCODE_PACK_STENCIL_REF:
 301       return "pack_stencil_ref";
 302    case FS_OPCODE_BLORP_FB_WRITE:
 303       return "blorp_fb_write";
 304    case FS_OPCODE_REP_FB_WRITE:
 305       return "rep_fb_write";
 306
 307    case SHADER_OPCODE_RCP:
 308       return "rcp";
 309    case SHADER_OPCODE_RSQ:
 310       return "rsq";
 311    case SHADER_OPCODE_SQRT:
 312       return "sqrt";
 313    case SHADER_OPCODE_EXP2:
 314       return "exp2";
 315    case SHADER_OPCODE_LOG2:
 316       return "log2";
 317    case SHADER_OPCODE_POW:
 318       return "pow";
 319    case SHADER_OPCODE_INT_QUOTIENT:
 320       return "int_quot";
 321    case SHADER_OPCODE_INT_REMAINDER:
 322       return "int_rem";
 323    case SHADER_OPCODE_SIN:
 324       return "sin";
 325    case SHADER_OPCODE_COS:
 326       return "cos";
 327
 328    case SHADER_OPCODE_TEX:
 329       return "tex";
 330    case SHADER_OPCODE_TEX_LOGICAL:
 331       return "tex_logical";
 332    case SHADER_OPCODE_TXD:
 333       return "txd";
 334    case SHADER_OPCODE_TXD_LOGICAL:
 335       return "txd_logical";
 336    case SHADER_OPCODE_TXF:
 337       return "txf";
 338    case SHADER_OPCODE_TXF_LOGICAL:
 339       return "txf_logical";
 340    case SHADER_OPCODE_TXL:
 341       return "txl";
 342    case SHADER_OPCODE_TXL_LOGICAL:
 343       return "txl_logical";
 344    case SHADER_OPCODE_TXS:
 345       return "txs";
 346    case SHADER_OPCODE_TXS_LOGICAL:
 347       return "txs_logical";
 348    case FS_OPCODE_TXB:
 349       return "txb";
 350    case FS_OPCODE_TXB_LOGICAL:
 351       return "txb_logical";
 352    case SHADER_OPCODE_TXF_CMS:
 353       return "txf_cms";
 354    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 355       return "txf_cms_logical";
 356    case SHADER_OPCODE_TXF_CMS_W:
 357       return "txf_cms_w";
 358    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 359       return "txf_cms_w_logical";
 360    case SHADER_OPCODE_TXF_UMS:
 361       return "txf_ums";
 362    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 363       return "txf_ums_logical";
 364    case SHADER_OPCODE_TXF_MCS:
 365       return "txf_mcs";
 366    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 367       return "txf_mcs_logical";
 368    case SHADER_OPCODE_LOD:
 369       return "lod";
 370    case SHADER_OPCODE_LOD_LOGICAL:
 371       return "lod_logical";
 372    case SHADER_OPCODE_TG4:
 373       return "tg4";
 374    case SHADER_OPCODE_TG4_LOGICAL:
 375       return "tg4_logical";
 376    case SHADER_OPCODE_TG4_OFFSET:
 377       return "tg4_offset";
 378    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 379       return "tg4_offset_logical";
 380    case SHADER_OPCODE_SAMPLEINFO:
 381       return "sampleinfo";
 382
 383    case SHADER_OPCODE_SHADER_TIME_ADD:
 384       return "shader_time_add";
 385
 386    case SHADER_OPCODE_UNTYPED_ATOMIC:
 387       return "untyped_atomic";
 388    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 389       return "untyped_atomic_logical";
 390    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 391       return "untyped_surface_read";
 392    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 393       return "untyped_surface_read_logical";
 394    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 395       return "untyped_surface_write";
 396    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 397       return "untyped_surface_write_logical";
 398    case SHADER_OPCODE_TYPED_ATOMIC:
 399       return "typed_atomic";
 400    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 401       return "typed_atomic_logical";
 402    case SHADER_OPCODE_TYPED_SURFACE_READ:
 403       return "typed_surface_read";
 404    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 405       return "typed_surface_read_logical";
 406    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 407       return "typed_surface_write";
 408    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 409       return "typed_surface_write_logical";
 410    case SHADER_OPCODE_MEMORY_FENCE:
 411       return "memory_fence";
 412
 413    case SHADER_OPCODE_LOAD_PAYLOAD:
 414       return "load_payload";
 415
 416    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 417       return "gen4_scratch_read";
 418    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 419       return "gen4_scratch_write";
 420    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 421       return "gen7_scratch_read";
 422    case SHADER_OPCODE_URB_WRITE_SIMD8:
 423       return "gen8_urb_write_simd8";
 424    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 425       return "gen8_urb_write_simd8_per_slot";
 426    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 427       return "gen8_urb_write_simd8_masked";
 428    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 429       return "gen8_urb_write_simd8_masked_per_slot";
 430    case SHADER_OPCODE_URB_READ_SIMD8:
 431       return "urb_read_simd8";
 432    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 433       return "urb_read_simd8_per_slot";
 434
 435    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 436       return "find_live_channel";
 437    case SHADER_OPCODE_BROADCAST:
 438       return "broadcast";
 439
 440    case VEC4_OPCODE_MOV_BYTES:
 441       return "mov_bytes";
 442    case VEC4_OPCODE_PACK_BYTES:
 443       return "pack_bytes";
 444    case VEC4_OPCODE_UNPACK_UNIFORM:
 445       return "unpack_uniform";
 446
 447    case FS_OPCODE_DDX_COARSE:
 448       return "ddx_coarse";
 449    case FS_OPCODE_DDX_FINE:
 450       return "ddx_fine";
 451    case FS_OPCODE_DDY_COARSE:
 452       return "ddy_coarse";
 453    case FS_OPCODE_DDY_FINE:
 454       return "ddy_fine";
 455
 456    case FS_OPCODE_CINTERP:
 457       return "cinterp";
 458    case FS_OPCODE_LINTERP:
 459       return "linterp";
 460
 461    case FS_OPCODE_PIXEL_X:
 462       return "pixel_x";
 463    case FS_OPCODE_PIXEL_Y:
 464       return "pixel_y";
 465
 466    case FS_OPCODE_GET_BUFFER_SIZE:
 467       return "fs_get_buffer_size";
 468
 469    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 470       return "uniform_pull_const";
 471    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 472       return "uniform_pull_const_gen7";
 473    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 474       return "varying_pull_const";
 475    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 476       return "varying_pull_const_gen7";
 477
 478    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 479       return "mov_dispatch_to_flags";
 480    case FS_OPCODE_DISCARD_JUMP:
 481       return "discard_jump";
 482
 483    case FS_OPCODE_SET_SAMPLE_ID:
 484       return "set_sample_id";
 485    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 486       return "set_simd4x2_offset";
 487
 488    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 489       return "pack_half_2x16_split";
 490    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 491       return "unpack_half_2x16_split_x";
 492    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 493       return "unpack_half_2x16_split_y";
 494
 495    case FS_OPCODE_PLACEHOLDER_HALT:
 496       return "placeholder_halt";
 497
 498    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 499       return "interp_centroid";
 500    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 501       return "interp_sample";
 502    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 503       return "interp_shared_offset";
 504    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 505       return "interp_per_slot_offset";
 506
 507    case VS_OPCODE_URB_WRITE:
 508       return "vs_urb_write";
 509    case VS_OPCODE_PULL_CONSTANT_LOAD:
 510       return "pull_constant_load";
 511    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 512       return "pull_constant_load_gen7";
 513
 514    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 515       return "set_simd4x2_header_gen9";
 516
 517    case VS_OPCODE_GET_BUFFER_SIZE:
 518       return "vs_get_buffer_size";
 519
 520    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 521       return "unpack_flags_simd4x2";
 522
 523    case GS_OPCODE_URB_WRITE:
 524       return "gs_urb_write";
 525    case GS_OPCODE_URB_WRITE_ALLOCATE:
 526       return "gs_urb_write_allocate";
 527    case GS_OPCODE_THREAD_END:
 528       return "gs_thread_end";
 529    case GS_OPCODE_SET_WRITE_OFFSET:
 530       return "set_write_offset";
 531    case GS_OPCODE_SET_VERTEX_COUNT:
 532       return "set_vertex_count";
 533    case GS_OPCODE_SET_DWORD_2:
 534       return "set_dword_2";
 535    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 536       return "prepare_channel_masks";
 537    case GS_OPCODE_SET_CHANNEL_MASKS:
 538       return "set_channel_masks";
 539    case GS_OPCODE_GET_INSTANCE_ID:
 540       return "get_instance_id";
 541    case GS_OPCODE_FF_SYNC:
 542       return "ff_sync";
 543    case GS_OPCODE_SET_PRIMITIVE_ID:
 544       return "set_primitive_id";
 545    case GS_OPCODE_SVB_WRITE:
 546       return "gs_svb_write";
 547    case GS_OPCODE_SVB_SET_DST_INDEX:
 548       return "gs_svb_set_dst_index";
 549    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 550       return "gs_ff_sync_set_primitives";
 551    case CS_OPCODE_CS_TERMINATE:
 552       return "cs_terminate";
 553    case SHADER_OPCODE_BARRIER:
 554       return "barrier";
 555    case SHADER_OPCODE_MULH:
 556       return "mulh";
 557    case SHADER_OPCODE_MOV_INDIRECT:
 558       return "mov_indirect";
 559
 560    case VEC4_OPCODE_URB_READ:
 561       return "urb_read";
 562    case TCS_OPCODE_GET_INSTANCE_ID:
 563       return "tcs_get_instance_id";
 564    case TCS_OPCODE_URB_WRITE:
 565       return "tcs_urb_write";
 566    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 567       return "tcs_set_input_urb_offsets";
 568    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 569       return "tcs_set_output_urb_offsets";
 570    case TCS_OPCODE_GET_PRIMITIVE_ID:
 571       return "tcs_get_primitive_id";
 572    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 573       return "tcs_create_barrier_header";
 574    case TCS_OPCODE_SRC0_010_IS_ZERO:
 575       return "tcs_src0<0,1,0>_is_zero";
 576    case TCS_OPCODE_RELEASE_INPUT:
 577       return "tcs_release_input";
 578    case TCS_OPCODE_THREAD_END:
 579       return "tcs_thread_end";
 580    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 581       return "tes_create_input_read_header";
 582    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 583       return "tes_add_indirect_urb_offset";
 584    case TES_OPCODE_GET_PRIMITIVE_ID:
 585       return "tes_get_primitive_id";
 586    }
 587
 588    unreachable("not reached");
 589 }
 590
 591 bool
 592 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 593 {
 594    union {
 595       unsigned ud;
 596       int d;
 597       float f;
 598    } imm = { reg->ud }, sat_imm = { 0 };
 599
 600    switch (type) {
 601    case BRW_REGISTER_TYPE_UD:
 602    case BRW_REGISTER_TYPE_D:
 603    case BRW_REGISTER_TYPE_UW:
 604    case BRW_REGISTER_TYPE_W:
 605    case BRW_REGISTER_TYPE_UQ:
 606    case BRW_REGISTER_TYPE_Q:
 607       /* Nothing to do. */
 608       return false;
 609    case BRW_REGISTER_TYPE_F:
 610       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 611       break;
 612    case BRW_REGISTER_TYPE_UB:
 613    case BRW_REGISTER_TYPE_B:
 614       unreachable("no UB/B immediates");
 615    case BRW_REGISTER_TYPE_V:
 616    case BRW_REGISTER_TYPE_UV:
 617    case BRW_REGISTER_TYPE_VF:
 618       unreachable("unimplemented: saturate vector immediate");
 619    case BRW_REGISTER_TYPE_DF:
 620    case BRW_REGISTER_TYPE_HF:
 621       unreachable("unimplemented: saturate DF/HF immediate");
 622    }
 623
 624    if (imm.ud != sat_imm.ud) {
 625       reg->ud = sat_imm.ud;
 626       return true;
 627    }
 628    return false;
 629 }
 630
 631 bool
 632 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 633 {
 634    switch (type) {
 635    case BRW_REGISTER_TYPE_D:
 636    case BRW_REGISTER_TYPE_UD:
 637       reg->d = -reg->d;
 638       return true;
 639    case BRW_REGISTER_TYPE_W:
 640    case BRW_REGISTER_TYPE_UW:
 641       reg->d = -(int16_t)reg->ud;
 642       return true;
 643    case BRW_REGISTER_TYPE_F:
 644       reg->f = -reg->f;
 645       return true;
 646    case BRW_REGISTER_TYPE_VF:
 647       reg->ud ^= 0x80808080;
 648       return true;
 649    case BRW_REGISTER_TYPE_UB:
 650    case BRW_REGISTER_TYPE_B:
 651       unreachable("no UB/B immediates");
 652    case BRW_REGISTER_TYPE_UV:
 653    case BRW_REGISTER_TYPE_V:
 654       assert(!"unimplemented: negate UV/V immediate");
 655    case BRW_REGISTER_TYPE_UQ:
 656    case BRW_REGISTER_TYPE_Q:
 657       assert(!"unimplemented: negate UQ/Q immediate");
 658    case BRW_REGISTER_TYPE_DF:
 659    case BRW_REGISTER_TYPE_HF:
 660       assert(!"unimplemented: negate DF/HF immediate");
 661    }
 662
 663    return false;
 664 }
 665
 666 bool
 667 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 668 {
 669    switch (type) {
 670    case BRW_REGISTER_TYPE_D:
 671       reg->d = abs(reg->d);
 672       return true;
 673    case BRW_REGISTER_TYPE_W:
 674       reg->d = abs((int16_t)reg->ud);
 675       return true;
 676    case BRW_REGISTER_TYPE_F:
 677       reg->f = fabsf(reg->f);
 678       return true;
 679    case BRW_REGISTER_TYPE_VF:
 680       reg->ud &= ~0x80808080;
 681       return true;
 682    case BRW_REGISTER_TYPE_UB:
 683    case BRW_REGISTER_TYPE_B:
 684       unreachable("no UB/B immediates");
 685    case BRW_REGISTER_TYPE_UQ:
 686    case BRW_REGISTER_TYPE_UD:
 687    case BRW_REGISTER_TYPE_UW:
 688    case BRW_REGISTER_TYPE_UV:
 689       /* Presumably the absolute value modifier on an unsigned source is a
 690        * nop, but it would be nice to confirm.
 691        */
 692       assert(!"unimplemented: abs unsigned immediate");
 693    case BRW_REGISTER_TYPE_V:
 694       assert(!"unimplemented: abs V immediate");
 695    case BRW_REGISTER_TYPE_Q:
 696       assert(!"unimplemented: abs Q immediate");
 697    case BRW_REGISTER_TYPE_DF:
 698    case BRW_REGISTER_TYPE_HF:
 699       assert(!"unimplemented: abs DF/HF immediate");
 700    }
 701
 702    return false;
 703 }
 704
 705 backend_shader::backend_shader(const struct brw_compiler *compiler,
 706                                void *log_data,
 707                                void *mem_ctx,
 708                                const nir_shader *shader,
 709                                struct brw_stage_prog_data *stage_prog_data)
 710    : compiler(compiler),
 711      log_data(log_data),
 712      devinfo(compiler->devinfo),
 713      nir(shader),
 714      stage_prog_data(stage_prog_data),
 715      mem_ctx(mem_ctx),
 716      cfg(NULL),
 717      stage(shader->stage)
 718 {
 719    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 720    stage_name = _mesa_shader_stage_to_string(stage);
 721    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 722 }
 723
 724 bool
 725 backend_reg::equals(const backend_reg &r) const
 726 {
 727    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 728           reg_offset == r.reg_offset;
 729 }
 730
 731 bool
 732 backend_reg::is_zero() const
 733 {
 734    if (file != IMM)
 735       return false;
 736
 737    return d == 0;
 738 }
 739
 740 bool
 741 backend_reg::is_one() const
 742 {
 743    if (file != IMM)
 744       return false;
 745
 746    return type == BRW_REGISTER_TYPE_F
 747           ? f == 1.0
 748           : d == 1;
 749 }
 750
 751 bool
 752 backend_reg::is_negative_one() const
 753 {
 754    if (file != IMM)
 755       return false;
 756
 757    switch (type) {
 758    case BRW_REGISTER_TYPE_F:
 759       return f == -1.0;
 760    case BRW_REGISTER_TYPE_D:
 761       return d == -1;
 762    default:
 763       return false;
 764    }
 765 }
 766
 767 bool
 768 backend_reg::is_null() const
 769 {
 770    return file == ARF && nr == BRW_ARF_NULL;
 771 }
 772
 773
 774 bool
 775 backend_reg::is_accumulator() const
 776 {
 777    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 778 }
 779
 780 bool
 781 backend_reg::in_range(const backend_reg &r, unsigned n) const
 782 {
 783    return (file == r.file &&
 784            nr == r.nr &&
 785            reg_offset >= r.reg_offset &&
 786            reg_offset < r.reg_offset + n);
 787 }
 788
 789 bool
 790 backend_instruction::is_commutative() const
 791 {
 792    switch (opcode) {
 793    case BRW_OPCODE_AND:
 794    case BRW_OPCODE_OR:
 795    case BRW_OPCODE_XOR:
 796    case BRW_OPCODE_ADD:
 797    case BRW_OPCODE_MUL:
 798    case SHADER_OPCODE_MULH:
 799       return true;
 800    case BRW_OPCODE_SEL:
 801       /* MIN and MAX are commutative. */
 802       if (conditional_mod == BRW_CONDITIONAL_GE ||
 803           conditional_mod == BRW_CONDITIONAL_L) {
 804          return true;
 805       }
 806       /* fallthrough */
 807    default:
 808       return false;
 809    }
 810 }
 811
 812 bool
 813 backend_instruction::is_3src() const
 814 {
 815    return ::is_3src(opcode);
 816 }
 817
 818 bool
 819 backend_instruction::is_tex() const
 820 {
 821    return (opcode == SHADER_OPCODE_TEX ||
 822            opcode == FS_OPCODE_TXB ||
 823            opcode == SHADER_OPCODE_TXD ||
 824            opcode == SHADER_OPCODE_TXF ||
 825            opcode == SHADER_OPCODE_TXF_CMS ||
 826            opcode == SHADER_OPCODE_TXF_CMS_W ||
 827            opcode == SHADER_OPCODE_TXF_UMS ||
 828            opcode == SHADER_OPCODE_TXF_MCS ||
 829            opcode == SHADER_OPCODE_TXL ||
 830            opcode == SHADER_OPCODE_TXS ||
 831            opcode == SHADER_OPCODE_LOD ||
 832            opcode == SHADER_OPCODE_TG4 ||
 833            opcode == SHADER_OPCODE_TG4_OFFSET);
 834 }
 835
 836 bool
 837 backend_instruction::is_math() const
 838 {
 839    return (opcode == SHADER_OPCODE_RCP ||
 840            opcode == SHADER_OPCODE_RSQ ||
 841            opcode == SHADER_OPCODE_SQRT ||
 842            opcode == SHADER_OPCODE_EXP2 ||
 843            opcode == SHADER_OPCODE_LOG2 ||
 844            opcode == SHADER_OPCODE_SIN ||
 845            opcode == SHADER_OPCODE_COS ||
 846            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 847            opcode == SHADER_OPCODE_INT_REMAINDER ||
 848            opcode == SHADER_OPCODE_POW);
 849 }
 850
 851 bool
 852 backend_instruction::is_control_flow() const
 853 {
 854    switch (opcode) {
 855    case BRW_OPCODE_DO:
 856    case BRW_OPCODE_WHILE:
 857    case BRW_OPCODE_IF:
 858    case BRW_OPCODE_ELSE:
 859    case BRW_OPCODE_ENDIF:
 860    case BRW_OPCODE_BREAK:
 861    case BRW_OPCODE_CONTINUE:
 862       return true;
 863    default:
 864       return false;
 865    }
 866 }
 867
 868 bool
 869 backend_instruction::can_do_source_mods() const
 870 {
 871    switch (opcode) {
 872    case BRW_OPCODE_ADDC:
 873    case BRW_OPCODE_BFE:
 874    case BRW_OPCODE_BFI1:
 875    case BRW_OPCODE_BFI2:
 876    case BRW_OPCODE_BFREV:
 877    case BRW_OPCODE_CBIT:
 878    case BRW_OPCODE_FBH:
 879    case BRW_OPCODE_FBL:
 880    case BRW_OPCODE_SUBB:
 881       return false;
 882    default:
 883       return true;
 884    }
 885 }
 886
 887 bool
 888 backend_instruction::can_do_saturate() const
 889 {
 890    switch (opcode) {
 891    case BRW_OPCODE_ADD:
 892    case BRW_OPCODE_ASR:
 893    case BRW_OPCODE_AVG:
 894    case BRW_OPCODE_DP2:
 895    case BRW_OPCODE_DP3:
 896    case BRW_OPCODE_DP4:
 897    case BRW_OPCODE_DPH:
 898    case BRW_OPCODE_F16TO32:
 899    case BRW_OPCODE_F32TO16:
 900    case BRW_OPCODE_LINE:
 901    case BRW_OPCODE_LRP:
 902    case BRW_OPCODE_MAC:
 903    case BRW_OPCODE_MAD:
 904    case BRW_OPCODE_MATH:
 905    case BRW_OPCODE_MOV:
 906    case BRW_OPCODE_MUL:
 907    case SHADER_OPCODE_MULH:
 908    case BRW_OPCODE_PLN:
 909    case BRW_OPCODE_RNDD:
 910    case BRW_OPCODE_RNDE:
 911    case BRW_OPCODE_RNDU:
 912    case BRW_OPCODE_RNDZ:
 913    case BRW_OPCODE_SEL:
 914    case BRW_OPCODE_SHL:
 915    case BRW_OPCODE_SHR:
 916    case FS_OPCODE_LINTERP:
 917    case SHADER_OPCODE_COS:
 918    case SHADER_OPCODE_EXP2:
 919    case SHADER_OPCODE_LOG2:
 920    case SHADER_OPCODE_POW:
 921    case SHADER_OPCODE_RCP:
 922    case SHADER_OPCODE_RSQ:
 923    case SHADER_OPCODE_SIN:
 924    case SHADER_OPCODE_SQRT:
 925       return true;
 926    default:
 927       return false;
 928    }
 929 }
 930
 931 bool
 932 backend_instruction::can_do_cmod() const
 933 {
 934    switch (opcode) {
 935    case BRW_OPCODE_ADD:
 936    case BRW_OPCODE_ADDC:
 937    case BRW_OPCODE_AND:
 938    case BRW_OPCODE_ASR:
 939    case BRW_OPCODE_AVG:
 940    case BRW_OPCODE_CMP:
 941    case BRW_OPCODE_CMPN:
 942    case BRW_OPCODE_DP2:
 943    case BRW_OPCODE_DP3:
 944    case BRW_OPCODE_DP4:
 945    case BRW_OPCODE_DPH:
 946    case BRW_OPCODE_F16TO32:
 947    case BRW_OPCODE_F32TO16:
 948    case BRW_OPCODE_FRC:
 949    case BRW_OPCODE_LINE:
 950    case BRW_OPCODE_LRP:
 951    case BRW_OPCODE_LZD:
 952    case BRW_OPCODE_MAC:
 953    case BRW_OPCODE_MACH:
 954    case BRW_OPCODE_MAD:
 955    case BRW_OPCODE_MOV:
 956    case BRW_OPCODE_MUL:
 957    case BRW_OPCODE_NOT:
 958    case BRW_OPCODE_OR:
 959    case BRW_OPCODE_PLN:
 960    case BRW_OPCODE_RNDD:
 961    case BRW_OPCODE_RNDE:
 962    case BRW_OPCODE_RNDU:
 963    case BRW_OPCODE_RNDZ:
 964    case BRW_OPCODE_SAD2:
 965    case BRW_OPCODE_SADA2:
 966    case BRW_OPCODE_SHL:
 967    case BRW_OPCODE_SHR:
 968    case BRW_OPCODE_SUBB:
 969    case BRW_OPCODE_XOR:
 970    case FS_OPCODE_CINTERP:
 971    case FS_OPCODE_LINTERP:
 972       return true;
 973    default:
 974       return false;
 975    }
 976 }
 977
 978 bool
 979 backend_instruction::reads_accumulator_implicitly() const
 980 {
 981    switch (opcode) {
 982    case BRW_OPCODE_MAC:
 983    case BRW_OPCODE_MACH:
 984    case BRW_OPCODE_SADA2:
 985       return true;
 986    default:
 987       return false;
 988    }
 989 }
 990
 991 bool
 992 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 993 {
 994    return writes_accumulator ||
 995           (devinfo->gen < 6 &&
 996            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 997             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 998              opcode != FS_OPCODE_CINTERP)));
 999 }
1000
1001 bool
1002 backend_instruction::has_side_effects() const
1003 {
1004    switch (opcode) {
1005    case SHADER_OPCODE_UNTYPED_ATOMIC:
1006    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1007    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1008    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1009    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1010    case SHADER_OPCODE_TYPED_ATOMIC:
1011    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1012    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1013    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1014    case SHADER_OPCODE_MEMORY_FENCE:
1015    case SHADER_OPCODE_URB_WRITE_SIMD8:
1016    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1017    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1018    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1019    case FS_OPCODE_FB_WRITE:
1020    case SHADER_OPCODE_BARRIER:
1021    case TCS_OPCODE_RELEASE_INPUT:
1022       return true;
1023    default:
1024       return false;
1025    }
1026 }
1027
1028 bool
1029 backend_instruction::is_volatile() const
1030 {
1031    switch (opcode) {
1032    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1033    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1034    case SHADER_OPCODE_TYPED_SURFACE_READ:
1035    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1036       return true;
1037    default:
1038       return false;
1039    }
1040 }
1041
1042 #ifndef NDEBUG
1043 static bool
1044 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1045 {
1046    bool found = false;
1047    foreach_inst_in_block (backend_instruction, i, block) {
1048       if (inst == i) {
1049          found = true;
1050       }
1051    }
1052    return found;
1053 }
1054 #endif
1055
1056 static void
1057 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1058 {
1059    for (bblock_t *block_iter = start_block->next();
1060         !block_iter->link.is_tail_sentinel();
1061         block_iter = block_iter->next()) {
1062       block_iter->start_ip += ip_adjustment;
1063       block_iter->end_ip += ip_adjustment;
1064    }
1065 }
1066
1067 void
1068 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1069 {
1070    if (!this->is_head_sentinel())
1071       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1072
1073    block->end_ip++;
1074
1075    adjust_later_block_ips(block, 1);
1076
1077    exec_node::insert_after(inst);
1078 }
1079
1080 void
1081 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1082 {
1083    if (!this->is_tail_sentinel())
1084       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1085
1086    block->end_ip++;
1087
1088    adjust_later_block_ips(block, 1);
1089
1090    exec_node::insert_before(inst);
1091 }
1092
1093 void
1094 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1095 {
1096    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1097
1098    unsigned num_inst = list->length();
1099
1100    block->end_ip += num_inst;
1101
1102    adjust_later_block_ips(block, num_inst);
1103
1104    exec_node::insert_before(list);
1105 }
1106
1107 void
1108 backend_instruction::remove(bblock_t *block)
1109 {
1110    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1111
1112    adjust_later_block_ips(block, -1);
1113
1114    if (block->start_ip == block->end_ip) {
1115       block->cfg->remove_block(block);
1116    } else {
1117       block->end_ip--;
1118    }
1119
1120    exec_node::remove();
1121 }
1122
1123 void
1124 backend_shader::dump_instructions()
1125 {
1126    dump_instructions(NULL);
1127 }
1128
1129 void
1130 backend_shader::dump_instructions(const char *name)
1131 {
1132    FILE *file = stderr;
1133    if (name && geteuid() != 0) {
1134       file = fopen(name, "w");
1135       if (!file)
1136          file = stderr;
1137    }
1138
1139    if (cfg) {
1140       int ip = 0;
1141       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1142          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1143             fprintf(file, "%4d: ", ip++);
1144          dump_instruction(inst, file);
1145       }
1146    } else {
1147       int ip = 0;
1148       foreach_in_list(backend_instruction, inst, &instructions) {
1149          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1150             fprintf(file, "%4d: ", ip++);
1151          dump_instruction(inst, file);
1152       }
1153    }
1154
1155    if (file != stderr) {
1156       fclose(file);
1157    }
1158 }
1159
1160 void
1161 backend_shader::calculate_cfg()
1162 {
1163    if (this->cfg)
1164       return;
1165    cfg = new(mem_ctx) cfg_t(&this->instructions);
1166 }
1167
1168 void
1169 backend_shader::invalidate_cfg()
1170 {
1171    ralloc_free(this->cfg);
1172    this->cfg = NULL;
1173 }
1174
1175 /**
1176  * Sets up the starting offsets for the groups of binding table entries
1177  * commong to all pipeline stages.
1178  *
1179  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1180  * unused but also make sure that addition of small offsets to them will
1181  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1182  */
1183 void
1184 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1185                                         const struct brw_device_info *devinfo,
1186                                         const struct gl_shader_program *shader_prog,
1187                                         const struct gl_program *prog,
1188                                         struct brw_stage_prog_data *stage_prog_data,
1189                                         uint32_t next_binding_table_offset)
1190 {
1191    const struct gl_shader *shader = NULL;
1192    int num_textures = _mesa_fls(prog->SamplersUsed);
1193
1194    if (shader_prog)
1195       shader = shader_prog->_LinkedShaders[stage];
1196
1197    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1198    next_binding_table_offset += num_textures;
1199
1200    if (shader) {
1201       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1202       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1203       next_binding_table_offset += shader->NumUniformBlocks;
1204
1205       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1206       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1207       next_binding_table_offset += shader->NumShaderStorageBlocks;
1208    } else {
1209       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1210       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1211    }
1212
1213    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1214       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1215       next_binding_table_offset++;
1216    } else {
1217       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1218    }
1219
1220    if (prog->UsesGather) {
1221       if (devinfo->gen >= 8) {
1222          stage_prog_data->binding_table.gather_texture_start =
1223             stage_prog_data->binding_table.texture_start;
1224       } else {
1225          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1226          next_binding_table_offset += num_textures;
1227       }
1228    } else {
1229       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1230    }
1231
1232    if (shader && shader->NumAtomicBuffers) {
1233       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1234       next_binding_table_offset += shader->NumAtomicBuffers;
1235    } else {
1236       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1237    }
1238
1239    if (shader && shader->NumImages) {
1240       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1241       next_binding_table_offset += shader->NumImages;
1242    } else {
1243       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1244    }
1245
1246    /* This may or may not be used depending on how the compile goes. */
1247    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1248    next_binding_table_offset++;
1249
1250    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1251
1252    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1253 }
1254
1255 static void
1256 setup_vec4_uniform_value(const gl_constant_value **params,
1257                          const gl_constant_value *values,
1258                          unsigned n)
1259 {
1260    static const gl_constant_value zero = { 0 };
1261
1262    for (unsigned i = 0; i < n; ++i)
1263       params[i] = &values[i];
1264
1265    for (unsigned i = n; i < 4; ++i)
1266       params[i] = &zero;
1267 }
1268
1269 void
1270 brw_setup_image_uniform_values(gl_shader_stage stage,
1271                                struct brw_stage_prog_data *stage_prog_data,
1272                                unsigned param_start_index,
1273                                const gl_uniform_storage *storage)
1274 {
1275    const gl_constant_value **param =
1276       &stage_prog_data->param[param_start_index];
1277
1278    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1279       const unsigned image_idx = storage->opaque[stage].index + i;
1280       const brw_image_param *image_param =
1281          &stage_prog_data->image_param[image_idx];
1282
1283       /* Upload the brw_image_param structure.  The order is expected to match
1284        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1285        */
1286       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1287          (const gl_constant_value *)&image_param->surface_idx, 1);
1288       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1289          (const gl_constant_value *)image_param->offset, 2);
1290       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1291          (const gl_constant_value *)image_param->size, 3);
1292       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1293          (const gl_constant_value *)image_param->stride, 4);
1294       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1295          (const gl_constant_value *)image_param->tiling, 3);
1296       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1297          (const gl_constant_value *)image_param->swizzling, 2);
1298       param += BRW_IMAGE_PARAM_SIZE;
1299
1300       brw_mark_surface_used(
1301          stage_prog_data,
1302          stage_prog_data->binding_table.image_start + image_idx);
1303    }
1304 }
1305
1306 /**
1307  * Decide which set of clip planes should be used when clipping via
1308  * gl_Position or gl_ClipVertex.
1309  */
1310 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1311 {
1312    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1313       /* There is currently a GLSL vertex shader, so clip according to GLSL
1314        * rules, which means compare gl_ClipVertex (or gl_Position, if
1315        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1316        * that were stored in EyeUserPlane at the time the clip planes were
1317        * specified.
1318        */
1319       return ctx->Transform.EyeUserPlane;
1320    } else {
1321       /* Either we are using fixed function or an ARB vertex program.  In
1322        * either case the clip planes are going to be compared against
1323        * gl_Position (which is in clip coordinates) so we have to clip using
1324        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1325        * core.
1326        */
1327       return ctx->Transform._ClipUserPlane;
1328    }
1329 }
1330
1331 extern "C" const unsigned *
1332 brw_compile_tes(const struct brw_compiler *compiler,
1333                 void *log_data,
1334                 void *mem_ctx,
1335                 const struct brw_tes_prog_key *key,
1336                 struct brw_tes_prog_data *prog_data,
1337                 const nir_shader *src_shader,
1338                 struct gl_shader_program *shader_prog,
1339                 int shader_time_index,
1340                 unsigned *final_assembly_size,
1341                 char **error_str)
1342 {
1343    const struct brw_device_info *devinfo = compiler->devinfo;
1344    struct gl_shader *shader =
1345       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1346    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1347
1348    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1349    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1350    nir->info.inputs_read = key->inputs_read;
1351    nir->info.patch_inputs_read = key->patch_inputs_read;
1352    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
1353    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1354
1355    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1356                        nir->info.outputs_written,
1357                        nir->info.separate_shader);
1358
1359    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1360
1361    assert(output_size_bytes >= 1);
1362    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1363       if (error_str)
1364          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1365       return NULL;
1366    }
1367
1368    /* URB entry sizes are stored as a multiple of 64 bytes. */
1369    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1370
1371    struct brw_vue_map input_vue_map;
1372    brw_compute_tess_vue_map(&input_vue_map,
1373                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1374                             nir->info.patch_inputs_read);
1375
1376    bool need_patch_header = nir->info.system_values_read &
1377       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1378        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1379
1380    /* The TES will pull most inputs using URB read messages.
1381     *
1382     * However, we push the patch header for TessLevel factors when required,
1383     * as it's a tiny amount of extra data.
1384     */
1385    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1386
1387    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1388       fprintf(stderr, "TES Input ");
1389       brw_print_vue_map(stderr, &input_vue_map);
1390       fprintf(stderr, "TES Output ");
1391       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1392    }
1393
1394    if (is_scalar) {
1395       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1396                    &prog_data->base.base, shader->Program, nir, 8,
1397                    shader_time_index, &input_vue_map);
1398       if (!v.run_tes()) {
1399          if (error_str)
1400             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1401          return NULL;
1402       }
1403
1404       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1405
1406       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1407                      &prog_data->base.base, v.promoted_constants, false,
1408                      "TES");
1409       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1410          g.enable_debug(ralloc_asprintf(mem_ctx,
1411                                         "%s tessellation evaluation shader %s",
1412                                         nir->info.label ? nir->info.label
1413                                                         : "unnamed",
1414                                         nir->info.name));
1415       }
1416
1417       g.generate_code(v.cfg, 8);
1418
1419       return g.get_assembly(final_assembly_size);
1420    } else {
1421       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1422                               nir, mem_ctx, shader_time_index);
1423       if (!v.run()) {
1424          if (error_str)
1425             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1426          return NULL;
1427       }
1428
1429       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1430          v.dump_instructions();
1431
1432       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1433                                         &prog_data->base, v.cfg,
1434                                         final_assembly_size);
1435    }
1436 }