src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "glsl/glsl_parser_extras.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32 #include "util/debug.h"
  33
  34 static void
  35 shader_debug_log_mesa(void *data, const char *fmt, ...)
  36 {
  37    struct brw_context *brw = (struct brw_context *)data;
  38    va_list args;
  39
  40    va_start(args, fmt);
  41    GLuint msg_id = 0;
  42    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  43                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  44                    MESA_DEBUG_TYPE_OTHER,
  45                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  46    va_end(args);
  47 }
  48
  49 static void
  50 shader_perf_log_mesa(void *data, const char *fmt, ...)
  51 {
  52    struct brw_context *brw = (struct brw_context *)data;
  53
  54    va_list args;
  55    va_start(args, fmt);
  56
  57    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  58       va_list args_copy;
  59       va_copy(args_copy, args);
  60       vfprintf(stderr, fmt, args_copy);
  61       va_end(args_copy);
  62    }
  63
  64    if (brw->perf_debug) {
  65       GLuint msg_id = 0;
  66       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  67                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  68                       MESA_DEBUG_TYPE_PERFORMANCE,
  69                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  70    }
  71    va_end(args);
  72 }
  73
  74 struct brw_compiler *
  75 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  76 {
  77    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  78
  79    compiler->devinfo = devinfo;
  80    compiler->shader_debug_log = shader_debug_log_mesa;
  81    compiler->shader_perf_log = shader_perf_log_mesa;
  82
  83    brw_fs_alloc_reg_sets(compiler);
  84    brw_vec4_alloc_reg_set(compiler);
  85
  86    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  87       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  88    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] = true;
  89    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  90       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  91    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  92    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  93
  94    nir_shader_compiler_options *nir_options =
  95       rzalloc(compiler, nir_shader_compiler_options);
  96    nir_options->native_integers = true;
  97    /* In order to help allow for better CSE at the NIR level we tell NIR
  98     * to split all ffma instructions during opt_algebraic and we then
  99     * re-combine them as a later step.
 100     */
 101    nir_options->lower_ffma = true;
 102    nir_options->lower_sub = true;
 103    /* In the vec4 backend, our dpN instruction replicates its result to all
 104     * the components of a vec4.  We would like NIR to give us replicated fdot
 105     * instructions because it can optimize better for us.
 106     *
 107     * For the FS backend, it should be lowered away by the scalarizing pass so
 108     * we should never see fdot anyway.
 109     */
 110    nir_options->fdot_replicates = true;
 111
 112    /* We want the GLSL compiler to emit code that uses condition codes */
 113    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 114       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 115       compiler->glsl_compiler_options[i].MaxIfDepth =
 116          devinfo->gen < 6 ? 16 : UINT_MAX;
 117
 118       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 119       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 120       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 121       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 122       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 123       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 124
 125       bool is_scalar = compiler->scalar_stage[i];
 126
 127       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 128       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 129       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 130
 131       /* !ARB_gpu_shader5 */
 132       if (devinfo->gen < 7)
 133          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 134
 135       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 136
 137       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 138    }
 139
 140    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 141
 142    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 143       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 144
 145    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 146       .LowerShaderSharedVariables = true;
 147
 148    return compiler;
 149 }
 150
 151 extern "C" struct gl_shader *
 152 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 153 {
 154    struct brw_shader *shader;
 155
 156    shader = rzalloc(NULL, struct brw_shader);
 157    if (shader) {
 158       shader->base.Type = type;
 159       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 160       shader->base.Name = name;
 161       _mesa_init_shader(ctx, &shader->base);
 162    }
 163
 164    return &shader->base;
 165 }
 166
 167 extern "C" void
 168 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 169                       unsigned surf_index)
 170 {
 171    assert(surf_index < BRW_MAX_SURFACES);
 172
 173    prog_data->binding_table.size_bytes =
 174       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 175 }
 176
 177 enum brw_reg_type
 178 brw_type_for_base_type(const struct glsl_type *type)
 179 {
 180    switch (type->base_type) {
 181    case GLSL_TYPE_FLOAT:
 182       return BRW_REGISTER_TYPE_F;
 183    case GLSL_TYPE_INT:
 184    case GLSL_TYPE_BOOL:
 185    case GLSL_TYPE_SUBROUTINE:
 186       return BRW_REGISTER_TYPE_D;
 187    case GLSL_TYPE_UINT:
 188       return BRW_REGISTER_TYPE_UD;
 189    case GLSL_TYPE_ARRAY:
 190       return brw_type_for_base_type(type->fields.array);
 191    case GLSL_TYPE_STRUCT:
 192    case GLSL_TYPE_SAMPLER:
 193    case GLSL_TYPE_ATOMIC_UINT:
 194       /* These should be overridden with the type of the member when
 195        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 196        * way to trip up if we don't.
 197        */
 198       return BRW_REGISTER_TYPE_UD;
 199    case GLSL_TYPE_IMAGE:
 200       return BRW_REGISTER_TYPE_UD;
 201    case GLSL_TYPE_VOID:
 202    case GLSL_TYPE_ERROR:
 203    case GLSL_TYPE_INTERFACE:
 204    case GLSL_TYPE_DOUBLE:
 205       unreachable("not reached");
 206    }
 207
 208    return BRW_REGISTER_TYPE_F;
 209 }
 210
 211 enum brw_conditional_mod
 212 brw_conditional_for_comparison(unsigned int op)
 213 {
 214    switch (op) {
 215    case ir_binop_less:
 216       return BRW_CONDITIONAL_L;
 217    case ir_binop_greater:
 218       return BRW_CONDITIONAL_G;
 219    case ir_binop_lequal:
 220       return BRW_CONDITIONAL_LE;
 221    case ir_binop_gequal:
 222       return BRW_CONDITIONAL_GE;
 223    case ir_binop_equal:
 224    case ir_binop_all_equal: /* same as equal for scalars */
 225       return BRW_CONDITIONAL_Z;
 226    case ir_binop_nequal:
 227    case ir_binop_any_nequal: /* same as nequal for scalars */
 228       return BRW_CONDITIONAL_NZ;
 229    default:
 230       unreachable("not reached: bad operation for comparison");
 231    }
 232 }
 233
 234 uint32_t
 235 brw_math_function(enum opcode op)
 236 {
 237    switch (op) {
 238    case SHADER_OPCODE_RCP:
 239       return BRW_MATH_FUNCTION_INV;
 240    case SHADER_OPCODE_RSQ:
 241       return BRW_MATH_FUNCTION_RSQ;
 242    case SHADER_OPCODE_SQRT:
 243       return BRW_MATH_FUNCTION_SQRT;
 244    case SHADER_OPCODE_EXP2:
 245       return BRW_MATH_FUNCTION_EXP;
 246    case SHADER_OPCODE_LOG2:
 247       return BRW_MATH_FUNCTION_LOG;
 248    case SHADER_OPCODE_POW:
 249       return BRW_MATH_FUNCTION_POW;
 250    case SHADER_OPCODE_SIN:
 251       return BRW_MATH_FUNCTION_SIN;
 252    case SHADER_OPCODE_COS:
 253       return BRW_MATH_FUNCTION_COS;
 254    case SHADER_OPCODE_INT_QUOTIENT:
 255       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 256    case SHADER_OPCODE_INT_REMAINDER:
 257       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 258    default:
 259       unreachable("not reached: unknown math function");
 260    }
 261 }
 262
 263 uint32_t
 264 brw_texture_offset(int *offsets, unsigned num_components)
 265 {
 266    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 267
 268    /* Combine all three offsets into a single unsigned dword:
 269     *
 270     *    bits 11:8 - U Offset (X component)
 271     *    bits  7:4 - V Offset (Y component)
 272     *    bits  3:0 - R Offset (Z component)
 273     */
 274    unsigned offset_bits = 0;
 275    for (unsigned i = 0; i < num_components; i++) {
 276       const unsigned shift = 4 * (2 - i);
 277       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 278    }
 279    return offset_bits;
 280 }
 281
 282 const char *
 283 brw_instruction_name(enum opcode op)
 284 {
 285    switch (op) {
 286    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 287       assert(opcode_descs[op].name);
 288       return opcode_descs[op].name;
 289    case FS_OPCODE_FB_WRITE:
 290       return "fb_write";
 291    case FS_OPCODE_FB_WRITE_LOGICAL:
 292       return "fb_write_logical";
 293    case FS_OPCODE_PACK_STENCIL_REF:
 294       return "pack_stencil_ref";
 295    case FS_OPCODE_BLORP_FB_WRITE:
 296       return "blorp_fb_write";
 297    case FS_OPCODE_REP_FB_WRITE:
 298       return "rep_fb_write";
 299
 300    case SHADER_OPCODE_RCP:
 301       return "rcp";
 302    case SHADER_OPCODE_RSQ:
 303       return "rsq";
 304    case SHADER_OPCODE_SQRT:
 305       return "sqrt";
 306    case SHADER_OPCODE_EXP2:
 307       return "exp2";
 308    case SHADER_OPCODE_LOG2:
 309       return "log2";
 310    case SHADER_OPCODE_POW:
 311       return "pow";
 312    case SHADER_OPCODE_INT_QUOTIENT:
 313       return "int_quot";
 314    case SHADER_OPCODE_INT_REMAINDER:
 315       return "int_rem";
 316    case SHADER_OPCODE_SIN:
 317       return "sin";
 318    case SHADER_OPCODE_COS:
 319       return "cos";
 320
 321    case SHADER_OPCODE_TEX:
 322       return "tex";
 323    case SHADER_OPCODE_TEX_LOGICAL:
 324       return "tex_logical";
 325    case SHADER_OPCODE_TXD:
 326       return "txd";
 327    case SHADER_OPCODE_TXD_LOGICAL:
 328       return "txd_logical";
 329    case SHADER_OPCODE_TXF:
 330       return "txf";
 331    case SHADER_OPCODE_TXF_LOGICAL:
 332       return "txf_logical";
 333    case SHADER_OPCODE_TXL:
 334       return "txl";
 335    case SHADER_OPCODE_TXL_LOGICAL:
 336       return "txl_logical";
 337    case SHADER_OPCODE_TXS:
 338       return "txs";
 339    case SHADER_OPCODE_TXS_LOGICAL:
 340       return "txs_logical";
 341    case FS_OPCODE_TXB:
 342       return "txb";
 343    case FS_OPCODE_TXB_LOGICAL:
 344       return "txb_logical";
 345    case SHADER_OPCODE_TXF_CMS:
 346       return "txf_cms";
 347    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 348       return "txf_cms_logical";
 349    case SHADER_OPCODE_TXF_CMS_W:
 350       return "txf_cms_w";
 351    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 352       return "txf_cms_w_logical";
 353    case SHADER_OPCODE_TXF_UMS:
 354       return "txf_ums";
 355    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 356       return "txf_ums_logical";
 357    case SHADER_OPCODE_TXF_MCS:
 358       return "txf_mcs";
 359    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 360       return "txf_mcs_logical";
 361    case SHADER_OPCODE_LOD:
 362       return "lod";
 363    case SHADER_OPCODE_LOD_LOGICAL:
 364       return "lod_logical";
 365    case SHADER_OPCODE_TG4:
 366       return "tg4";
 367    case SHADER_OPCODE_TG4_LOGICAL:
 368       return "tg4_logical";
 369    case SHADER_OPCODE_TG4_OFFSET:
 370       return "tg4_offset";
 371    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 372       return "tg4_offset_logical";
 373    case SHADER_OPCODE_SAMPLEINFO:
 374       return "sampleinfo";
 375
 376    case SHADER_OPCODE_SHADER_TIME_ADD:
 377       return "shader_time_add";
 378
 379    case SHADER_OPCODE_UNTYPED_ATOMIC:
 380       return "untyped_atomic";
 381    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 382       return "untyped_atomic_logical";
 383    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 384       return "untyped_surface_read";
 385    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 386       return "untyped_surface_read_logical";
 387    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 388       return "untyped_surface_write";
 389    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 390       return "untyped_surface_write_logical";
 391    case SHADER_OPCODE_TYPED_ATOMIC:
 392       return "typed_atomic";
 393    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 394       return "typed_atomic_logical";
 395    case SHADER_OPCODE_TYPED_SURFACE_READ:
 396       return "typed_surface_read";
 397    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 398       return "typed_surface_read_logical";
 399    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 400       return "typed_surface_write";
 401    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 402       return "typed_surface_write_logical";
 403    case SHADER_OPCODE_MEMORY_FENCE:
 404       return "memory_fence";
 405
 406    case SHADER_OPCODE_LOAD_PAYLOAD:
 407       return "load_payload";
 408
 409    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 410       return "gen4_scratch_read";
 411    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 412       return "gen4_scratch_write";
 413    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 414       return "gen7_scratch_read";
 415    case SHADER_OPCODE_URB_WRITE_SIMD8:
 416       return "gen8_urb_write_simd8";
 417    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 418       return "gen8_urb_write_simd8_per_slot";
 419    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 420       return "gen8_urb_write_simd8_masked";
 421    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 422       return "gen8_urb_write_simd8_masked_per_slot";
 423    case SHADER_OPCODE_URB_READ_SIMD8:
 424       return "urb_read_simd8";
 425    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 426       return "urb_read_simd8_per_slot";
 427
 428    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 429       return "find_live_channel";
 430    case SHADER_OPCODE_BROADCAST:
 431       return "broadcast";
 432
 433    case VEC4_OPCODE_MOV_BYTES:
 434       return "mov_bytes";
 435    case VEC4_OPCODE_PACK_BYTES:
 436       return "pack_bytes";
 437    case VEC4_OPCODE_UNPACK_UNIFORM:
 438       return "unpack_uniform";
 439
 440    case FS_OPCODE_DDX_COARSE:
 441       return "ddx_coarse";
 442    case FS_OPCODE_DDX_FINE:
 443       return "ddx_fine";
 444    case FS_OPCODE_DDY_COARSE:
 445       return "ddy_coarse";
 446    case FS_OPCODE_DDY_FINE:
 447       return "ddy_fine";
 448
 449    case FS_OPCODE_CINTERP:
 450       return "cinterp";
 451    case FS_OPCODE_LINTERP:
 452       return "linterp";
 453
 454    case FS_OPCODE_PIXEL_X:
 455       return "pixel_x";
 456    case FS_OPCODE_PIXEL_Y:
 457       return "pixel_y";
 458
 459    case FS_OPCODE_GET_BUFFER_SIZE:
 460       return "fs_get_buffer_size";
 461
 462    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 463       return "uniform_pull_const";
 464    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 465       return "uniform_pull_const_gen7";
 466    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 467       return "varying_pull_const";
 468    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 469       return "varying_pull_const_gen7";
 470
 471    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 472       return "mov_dispatch_to_flags";
 473    case FS_OPCODE_DISCARD_JUMP:
 474       return "discard_jump";
 475
 476    case FS_OPCODE_SET_SAMPLE_ID:
 477       return "set_sample_id";
 478    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 479       return "set_simd4x2_offset";
 480
 481    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 482       return "pack_half_2x16_split";
 483    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 484       return "unpack_half_2x16_split_x";
 485    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 486       return "unpack_half_2x16_split_y";
 487
 488    case FS_OPCODE_PLACEHOLDER_HALT:
 489       return "placeholder_halt";
 490
 491    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 492       return "interp_centroid";
 493    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 494       return "interp_sample";
 495    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 496       return "interp_shared_offset";
 497    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 498       return "interp_per_slot_offset";
 499
 500    case VS_OPCODE_URB_WRITE:
 501       return "vs_urb_write";
 502    case VS_OPCODE_PULL_CONSTANT_LOAD:
 503       return "pull_constant_load";
 504    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 505       return "pull_constant_load_gen7";
 506
 507    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 508       return "set_simd4x2_header_gen9";
 509
 510    case VS_OPCODE_GET_BUFFER_SIZE:
 511       return "vs_get_buffer_size";
 512
 513    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 514       return "unpack_flags_simd4x2";
 515
 516    case GS_OPCODE_URB_WRITE:
 517       return "gs_urb_write";
 518    case GS_OPCODE_URB_WRITE_ALLOCATE:
 519       return "gs_urb_write_allocate";
 520    case GS_OPCODE_THREAD_END:
 521       return "gs_thread_end";
 522    case GS_OPCODE_SET_WRITE_OFFSET:
 523       return "set_write_offset";
 524    case GS_OPCODE_SET_VERTEX_COUNT:
 525       return "set_vertex_count";
 526    case GS_OPCODE_SET_DWORD_2:
 527       return "set_dword_2";
 528    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 529       return "prepare_channel_masks";
 530    case GS_OPCODE_SET_CHANNEL_MASKS:
 531       return "set_channel_masks";
 532    case GS_OPCODE_GET_INSTANCE_ID:
 533       return "get_instance_id";
 534    case GS_OPCODE_FF_SYNC:
 535       return "ff_sync";
 536    case GS_OPCODE_SET_PRIMITIVE_ID:
 537       return "set_primitive_id";
 538    case GS_OPCODE_SVB_WRITE:
 539       return "gs_svb_write";
 540    case GS_OPCODE_SVB_SET_DST_INDEX:
 541       return "gs_svb_set_dst_index";
 542    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 543       return "gs_ff_sync_set_primitives";
 544    case CS_OPCODE_CS_TERMINATE:
 545       return "cs_terminate";
 546    case SHADER_OPCODE_BARRIER:
 547       return "barrier";
 548    case SHADER_OPCODE_MULH:
 549       return "mulh";
 550    case SHADER_OPCODE_MOV_INDIRECT:
 551       return "mov_indirect";
 552    }
 553
 554    unreachable("not reached");
 555 }
 556
 557 bool
 558 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 559 {
 560    union {
 561       unsigned ud;
 562       int d;
 563       float f;
 564    } imm = { reg->ud }, sat_imm = { 0 };
 565
 566    switch (type) {
 567    case BRW_REGISTER_TYPE_UD:
 568    case BRW_REGISTER_TYPE_D:
 569    case BRW_REGISTER_TYPE_UW:
 570    case BRW_REGISTER_TYPE_W:
 571    case BRW_REGISTER_TYPE_UQ:
 572    case BRW_REGISTER_TYPE_Q:
 573       /* Nothing to do. */
 574       return false;
 575    case BRW_REGISTER_TYPE_F:
 576       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 577       break;
 578    case BRW_REGISTER_TYPE_UB:
 579    case BRW_REGISTER_TYPE_B:
 580       unreachable("no UB/B immediates");
 581    case BRW_REGISTER_TYPE_V:
 582    case BRW_REGISTER_TYPE_UV:
 583    case BRW_REGISTER_TYPE_VF:
 584       unreachable("unimplemented: saturate vector immediate");
 585    case BRW_REGISTER_TYPE_DF:
 586    case BRW_REGISTER_TYPE_HF:
 587       unreachable("unimplemented: saturate DF/HF immediate");
 588    }
 589
 590    if (imm.ud != sat_imm.ud) {
 591       reg->ud = sat_imm.ud;
 592       return true;
 593    }
 594    return false;
 595 }
 596
 597 bool
 598 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 599 {
 600    switch (type) {
 601    case BRW_REGISTER_TYPE_D:
 602    case BRW_REGISTER_TYPE_UD:
 603       reg->d = -reg->d;
 604       return true;
 605    case BRW_REGISTER_TYPE_W:
 606    case BRW_REGISTER_TYPE_UW:
 607       reg->d = -(int16_t)reg->ud;
 608       return true;
 609    case BRW_REGISTER_TYPE_F:
 610       reg->f = -reg->f;
 611       return true;
 612    case BRW_REGISTER_TYPE_VF:
 613       reg->ud ^= 0x80808080;
 614       return true;
 615    case BRW_REGISTER_TYPE_UB:
 616    case BRW_REGISTER_TYPE_B:
 617       unreachable("no UB/B immediates");
 618    case BRW_REGISTER_TYPE_UV:
 619    case BRW_REGISTER_TYPE_V:
 620       assert(!"unimplemented: negate UV/V immediate");
 621    case BRW_REGISTER_TYPE_UQ:
 622    case BRW_REGISTER_TYPE_Q:
 623       assert(!"unimplemented: negate UQ/Q immediate");
 624    case BRW_REGISTER_TYPE_DF:
 625    case BRW_REGISTER_TYPE_HF:
 626       assert(!"unimplemented: negate DF/HF immediate");
 627    }
 628
 629    return false;
 630 }
 631
 632 bool
 633 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 634 {
 635    switch (type) {
 636    case BRW_REGISTER_TYPE_D:
 637       reg->d = abs(reg->d);
 638       return true;
 639    case BRW_REGISTER_TYPE_W:
 640       reg->d = abs((int16_t)reg->ud);
 641       return true;
 642    case BRW_REGISTER_TYPE_F:
 643       reg->f = fabsf(reg->f);
 644       return true;
 645    case BRW_REGISTER_TYPE_VF:
 646       reg->ud &= ~0x80808080;
 647       return true;
 648    case BRW_REGISTER_TYPE_UB:
 649    case BRW_REGISTER_TYPE_B:
 650       unreachable("no UB/B immediates");
 651    case BRW_REGISTER_TYPE_UQ:
 652    case BRW_REGISTER_TYPE_UD:
 653    case BRW_REGISTER_TYPE_UW:
 654    case BRW_REGISTER_TYPE_UV:
 655       /* Presumably the absolute value modifier on an unsigned source is a
 656        * nop, but it would be nice to confirm.
 657        */
 658       assert(!"unimplemented: abs unsigned immediate");
 659    case BRW_REGISTER_TYPE_V:
 660       assert(!"unimplemented: abs V immediate");
 661    case BRW_REGISTER_TYPE_Q:
 662       assert(!"unimplemented: abs Q immediate");
 663    case BRW_REGISTER_TYPE_DF:
 664    case BRW_REGISTER_TYPE_HF:
 665       assert(!"unimplemented: abs DF/HF immediate");
 666    }
 667
 668    return false;
 669 }
 670
 671 backend_shader::backend_shader(const struct brw_compiler *compiler,
 672                                void *log_data,
 673                                void *mem_ctx,
 674                                const nir_shader *shader,
 675                                struct brw_stage_prog_data *stage_prog_data)
 676    : compiler(compiler),
 677      log_data(log_data),
 678      devinfo(compiler->devinfo),
 679      nir(shader),
 680      stage_prog_data(stage_prog_data),
 681      mem_ctx(mem_ctx),
 682      cfg(NULL),
 683      stage(shader->stage)
 684 {
 685    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 686    stage_name = _mesa_shader_stage_to_string(stage);
 687    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 688 }
 689
 690 bool
 691 backend_reg::equals(const backend_reg &r) const
 692 {
 693    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 694           reg_offset == r.reg_offset;
 695 }
 696
 697 bool
 698 backend_reg::is_zero() const
 699 {
 700    if (file != IMM)
 701       return false;
 702
 703    return d == 0;
 704 }
 705
 706 bool
 707 backend_reg::is_one() const
 708 {
 709    if (file != IMM)
 710       return false;
 711
 712    return type == BRW_REGISTER_TYPE_F
 713           ? f == 1.0
 714           : d == 1;
 715 }
 716
 717 bool
 718 backend_reg::is_negative_one() const
 719 {
 720    if (file != IMM)
 721       return false;
 722
 723    switch (type) {
 724    case BRW_REGISTER_TYPE_F:
 725       return f == -1.0;
 726    case BRW_REGISTER_TYPE_D:
 727       return d == -1;
 728    default:
 729       return false;
 730    }
 731 }
 732
 733 bool
 734 backend_reg::is_null() const
 735 {
 736    return file == ARF && nr == BRW_ARF_NULL;
 737 }
 738
 739
 740 bool
 741 backend_reg::is_accumulator() const
 742 {
 743    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 744 }
 745
 746 bool
 747 backend_reg::in_range(const backend_reg &r, unsigned n) const
 748 {
 749    return (file == r.file &&
 750            nr == r.nr &&
 751            reg_offset >= r.reg_offset &&
 752            reg_offset < r.reg_offset + n);
 753 }
 754
 755 bool
 756 backend_instruction::is_commutative() const
 757 {
 758    switch (opcode) {
 759    case BRW_OPCODE_AND:
 760    case BRW_OPCODE_OR:
 761    case BRW_OPCODE_XOR:
 762    case BRW_OPCODE_ADD:
 763    case BRW_OPCODE_MUL:
 764    case SHADER_OPCODE_MULH:
 765       return true;
 766    case BRW_OPCODE_SEL:
 767       /* MIN and MAX are commutative. */
 768       if (conditional_mod == BRW_CONDITIONAL_GE ||
 769           conditional_mod == BRW_CONDITIONAL_L) {
 770          return true;
 771       }
 772       /* fallthrough */
 773    default:
 774       return false;
 775    }
 776 }
 777
 778 bool
 779 backend_instruction::is_3src() const
 780 {
 781    return ::is_3src(opcode);
 782 }
 783
 784 bool
 785 backend_instruction::is_tex() const
 786 {
 787    return (opcode == SHADER_OPCODE_TEX ||
 788            opcode == FS_OPCODE_TXB ||
 789            opcode == SHADER_OPCODE_TXD ||
 790            opcode == SHADER_OPCODE_TXF ||
 791            opcode == SHADER_OPCODE_TXF_CMS ||
 792            opcode == SHADER_OPCODE_TXF_CMS_W ||
 793            opcode == SHADER_OPCODE_TXF_UMS ||
 794            opcode == SHADER_OPCODE_TXF_MCS ||
 795            opcode == SHADER_OPCODE_TXL ||
 796            opcode == SHADER_OPCODE_TXS ||
 797            opcode == SHADER_OPCODE_LOD ||
 798            opcode == SHADER_OPCODE_TG4 ||
 799            opcode == SHADER_OPCODE_TG4_OFFSET);
 800 }
 801
 802 bool
 803 backend_instruction::is_math() const
 804 {
 805    return (opcode == SHADER_OPCODE_RCP ||
 806            opcode == SHADER_OPCODE_RSQ ||
 807            opcode == SHADER_OPCODE_SQRT ||
 808            opcode == SHADER_OPCODE_EXP2 ||
 809            opcode == SHADER_OPCODE_LOG2 ||
 810            opcode == SHADER_OPCODE_SIN ||
 811            opcode == SHADER_OPCODE_COS ||
 812            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 813            opcode == SHADER_OPCODE_INT_REMAINDER ||
 814            opcode == SHADER_OPCODE_POW);
 815 }
 816
 817 bool
 818 backend_instruction::is_control_flow() const
 819 {
 820    switch (opcode) {
 821    case BRW_OPCODE_DO:
 822    case BRW_OPCODE_WHILE:
 823    case BRW_OPCODE_IF:
 824    case BRW_OPCODE_ELSE:
 825    case BRW_OPCODE_ENDIF:
 826    case BRW_OPCODE_BREAK:
 827    case BRW_OPCODE_CONTINUE:
 828       return true;
 829    default:
 830       return false;
 831    }
 832 }
 833
 834 bool
 835 backend_instruction::can_do_source_mods() const
 836 {
 837    switch (opcode) {
 838    case BRW_OPCODE_ADDC:
 839    case BRW_OPCODE_BFE:
 840    case BRW_OPCODE_BFI1:
 841    case BRW_OPCODE_BFI2:
 842    case BRW_OPCODE_BFREV:
 843    case BRW_OPCODE_CBIT:
 844    case BRW_OPCODE_FBH:
 845    case BRW_OPCODE_FBL:
 846    case BRW_OPCODE_SUBB:
 847       return false;
 848    default:
 849       return true;
 850    }
 851 }
 852
 853 bool
 854 backend_instruction::can_do_saturate() const
 855 {
 856    switch (opcode) {
 857    case BRW_OPCODE_ADD:
 858    case BRW_OPCODE_ASR:
 859    case BRW_OPCODE_AVG:
 860    case BRW_OPCODE_DP2:
 861    case BRW_OPCODE_DP3:
 862    case BRW_OPCODE_DP4:
 863    case BRW_OPCODE_DPH:
 864    case BRW_OPCODE_F16TO32:
 865    case BRW_OPCODE_F32TO16:
 866    case BRW_OPCODE_LINE:
 867    case BRW_OPCODE_LRP:
 868    case BRW_OPCODE_MAC:
 869    case BRW_OPCODE_MAD:
 870    case BRW_OPCODE_MATH:
 871    case BRW_OPCODE_MOV:
 872    case BRW_OPCODE_MUL:
 873    case SHADER_OPCODE_MULH:
 874    case BRW_OPCODE_PLN:
 875    case BRW_OPCODE_RNDD:
 876    case BRW_OPCODE_RNDE:
 877    case BRW_OPCODE_RNDU:
 878    case BRW_OPCODE_RNDZ:
 879    case BRW_OPCODE_SEL:
 880    case BRW_OPCODE_SHL:
 881    case BRW_OPCODE_SHR:
 882    case FS_OPCODE_LINTERP:
 883    case SHADER_OPCODE_COS:
 884    case SHADER_OPCODE_EXP2:
 885    case SHADER_OPCODE_LOG2:
 886    case SHADER_OPCODE_POW:
 887    case SHADER_OPCODE_RCP:
 888    case SHADER_OPCODE_RSQ:
 889    case SHADER_OPCODE_SIN:
 890    case SHADER_OPCODE_SQRT:
 891       return true;
 892    default:
 893       return false;
 894    }
 895 }
 896
 897 bool
 898 backend_instruction::can_do_cmod() const
 899 {
 900    switch (opcode) {
 901    case BRW_OPCODE_ADD:
 902    case BRW_OPCODE_ADDC:
 903    case BRW_OPCODE_AND:
 904    case BRW_OPCODE_ASR:
 905    case BRW_OPCODE_AVG:
 906    case BRW_OPCODE_CMP:
 907    case BRW_OPCODE_CMPN:
 908    case BRW_OPCODE_DP2:
 909    case BRW_OPCODE_DP3:
 910    case BRW_OPCODE_DP4:
 911    case BRW_OPCODE_DPH:
 912    case BRW_OPCODE_F16TO32:
 913    case BRW_OPCODE_F32TO16:
 914    case BRW_OPCODE_FRC:
 915    case BRW_OPCODE_LINE:
 916    case BRW_OPCODE_LRP:
 917    case BRW_OPCODE_LZD:
 918    case BRW_OPCODE_MAC:
 919    case BRW_OPCODE_MACH:
 920    case BRW_OPCODE_MAD:
 921    case BRW_OPCODE_MOV:
 922    case BRW_OPCODE_MUL:
 923    case BRW_OPCODE_NOT:
 924    case BRW_OPCODE_OR:
 925    case BRW_OPCODE_PLN:
 926    case BRW_OPCODE_RNDD:
 927    case BRW_OPCODE_RNDE:
 928    case BRW_OPCODE_RNDU:
 929    case BRW_OPCODE_RNDZ:
 930    case BRW_OPCODE_SAD2:
 931    case BRW_OPCODE_SADA2:
 932    case BRW_OPCODE_SHL:
 933    case BRW_OPCODE_SHR:
 934    case BRW_OPCODE_SUBB:
 935    case BRW_OPCODE_XOR:
 936    case FS_OPCODE_CINTERP:
 937    case FS_OPCODE_LINTERP:
 938       return true;
 939    default:
 940       return false;
 941    }
 942 }
 943
 944 bool
 945 backend_instruction::reads_accumulator_implicitly() const
 946 {
 947    switch (opcode) {
 948    case BRW_OPCODE_MAC:
 949    case BRW_OPCODE_MACH:
 950    case BRW_OPCODE_SADA2:
 951       return true;
 952    default:
 953       return false;
 954    }
 955 }
 956
 957 bool
 958 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 959 {
 960    return writes_accumulator ||
 961           (devinfo->gen < 6 &&
 962            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 963             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 964              opcode != FS_OPCODE_CINTERP)));
 965 }
 966
 967 bool
 968 backend_instruction::has_side_effects() const
 969 {
 970    switch (opcode) {
 971    case SHADER_OPCODE_UNTYPED_ATOMIC:
 972    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 973    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 974    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 975    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 976    case SHADER_OPCODE_TYPED_ATOMIC:
 977    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 978    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 979    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 980    case SHADER_OPCODE_MEMORY_FENCE:
 981    case SHADER_OPCODE_URB_WRITE_SIMD8:
 982    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 983    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 984    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 985    case FS_OPCODE_FB_WRITE:
 986    case SHADER_OPCODE_BARRIER:
 987       return true;
 988    default:
 989       return false;
 990    }
 991 }
 992
 993 bool
 994 backend_instruction::is_volatile() const
 995 {
 996    switch (opcode) {
 997    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 998    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 999    case SHADER_OPCODE_TYPED_SURFACE_READ:
1000    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1001       return true;
1002    default:
1003       return false;
1004    }
1005 }
1006
1007 #ifndef NDEBUG
1008 static bool
1009 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1010 {
1011    bool found = false;
1012    foreach_inst_in_block (backend_instruction, i, block) {
1013       if (inst == i) {
1014          found = true;
1015       }
1016    }
1017    return found;
1018 }
1019 #endif
1020
1021 static void
1022 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1023 {
1024    for (bblock_t *block_iter = start_block->next();
1025         !block_iter->link.is_tail_sentinel();
1026         block_iter = block_iter->next()) {
1027       block_iter->start_ip += ip_adjustment;
1028       block_iter->end_ip += ip_adjustment;
1029    }
1030 }
1031
1032 void
1033 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1034 {
1035    if (!this->is_head_sentinel())
1036       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1037
1038    block->end_ip++;
1039
1040    adjust_later_block_ips(block, 1);
1041
1042    exec_node::insert_after(inst);
1043 }
1044
1045 void
1046 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1047 {
1048    if (!this->is_tail_sentinel())
1049       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1050
1051    block->end_ip++;
1052
1053    adjust_later_block_ips(block, 1);
1054
1055    exec_node::insert_before(inst);
1056 }
1057
1058 void
1059 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1060 {
1061    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1062
1063    unsigned num_inst = list->length();
1064
1065    block->end_ip += num_inst;
1066
1067    adjust_later_block_ips(block, num_inst);
1068
1069    exec_node::insert_before(list);
1070 }
1071
1072 void
1073 backend_instruction::remove(bblock_t *block)
1074 {
1075    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1076
1077    adjust_later_block_ips(block, -1);
1078
1079    if (block->start_ip == block->end_ip) {
1080       block->cfg->remove_block(block);
1081    } else {
1082       block->end_ip--;
1083    }
1084
1085    exec_node::remove();
1086 }
1087
1088 void
1089 backend_shader::dump_instructions()
1090 {
1091    dump_instructions(NULL);
1092 }
1093
1094 void
1095 backend_shader::dump_instructions(const char *name)
1096 {
1097    FILE *file = stderr;
1098    if (name && geteuid() != 0) {
1099       file = fopen(name, "w");
1100       if (!file)
1101          file = stderr;
1102    }
1103
1104    if (cfg) {
1105       int ip = 0;
1106       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1107          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1108             fprintf(file, "%4d: ", ip++);
1109          dump_instruction(inst, file);
1110       }
1111    } else {
1112       int ip = 0;
1113       foreach_in_list(backend_instruction, inst, &instructions) {
1114          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1115             fprintf(file, "%4d: ", ip++);
1116          dump_instruction(inst, file);
1117       }
1118    }
1119
1120    if (file != stderr) {
1121       fclose(file);
1122    }
1123 }
1124
1125 void
1126 backend_shader::calculate_cfg()
1127 {
1128    if (this->cfg)
1129       return;
1130    cfg = new(mem_ctx) cfg_t(&this->instructions);
1131 }
1132
1133 void
1134 backend_shader::invalidate_cfg()
1135 {
1136    ralloc_free(this->cfg);
1137    this->cfg = NULL;
1138 }
1139
1140 /**
1141  * Sets up the starting offsets for the groups of binding table entries
1142  * commong to all pipeline stages.
1143  *
1144  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1145  * unused but also make sure that addition of small offsets to them will
1146  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1147  */
1148 void
1149 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1150                                         const struct brw_device_info *devinfo,
1151                                         const struct gl_shader_program *shader_prog,
1152                                         const struct gl_program *prog,
1153                                         struct brw_stage_prog_data *stage_prog_data,
1154                                         uint32_t next_binding_table_offset)
1155 {
1156    const struct gl_shader *shader = NULL;
1157    int num_textures = _mesa_fls(prog->SamplersUsed);
1158
1159    if (shader_prog)
1160       shader = shader_prog->_LinkedShaders[stage];
1161
1162    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1163    next_binding_table_offset += num_textures;
1164
1165    if (shader) {
1166       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1167       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1168       next_binding_table_offset += shader->NumUniformBlocks;
1169
1170       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1171       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1172       next_binding_table_offset += shader->NumShaderStorageBlocks;
1173    } else {
1174       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1175       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1176    }
1177
1178    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1179       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1180       next_binding_table_offset++;
1181    } else {
1182       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1183    }
1184
1185    if (prog->UsesGather) {
1186       if (devinfo->gen >= 8) {
1187          stage_prog_data->binding_table.gather_texture_start =
1188             stage_prog_data->binding_table.texture_start;
1189       } else {
1190          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1191          next_binding_table_offset += num_textures;
1192       }
1193    } else {
1194       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1195    }
1196
1197    if (shader && shader->NumAtomicBuffers) {
1198       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1199       next_binding_table_offset += shader->NumAtomicBuffers;
1200    } else {
1201       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1202    }
1203
1204    if (shader && shader->NumImages) {
1205       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1206       next_binding_table_offset += shader->NumImages;
1207    } else {
1208       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1209    }
1210
1211    /* This may or may not be used depending on how the compile goes. */
1212    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1213    next_binding_table_offset++;
1214
1215    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1216
1217    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1218 }
1219
1220 static void
1221 setup_vec4_uniform_value(const gl_constant_value **params,
1222                          const gl_constant_value *values,
1223                          unsigned n)
1224 {
1225    static const gl_constant_value zero = { 0 };
1226
1227    for (unsigned i = 0; i < n; ++i)
1228       params[i] = &values[i];
1229
1230    for (unsigned i = n; i < 4; ++i)
1231       params[i] = &zero;
1232 }
1233
1234 void
1235 brw_setup_image_uniform_values(gl_shader_stage stage,
1236                                struct brw_stage_prog_data *stage_prog_data,
1237                                unsigned param_start_index,
1238                                const gl_uniform_storage *storage)
1239 {
1240    const gl_constant_value **param =
1241       &stage_prog_data->param[param_start_index];
1242
1243    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1244       const unsigned image_idx = storage->opaque[stage].index + i;
1245       const brw_image_param *image_param =
1246          &stage_prog_data->image_param[image_idx];
1247
1248       /* Upload the brw_image_param structure.  The order is expected to match
1249        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1250        */
1251       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1252          (const gl_constant_value *)&image_param->surface_idx, 1);
1253       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1254          (const gl_constant_value *)image_param->offset, 2);
1255       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1256          (const gl_constant_value *)image_param->size, 3);
1257       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1258          (const gl_constant_value *)image_param->stride, 4);
1259       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1260          (const gl_constant_value *)image_param->tiling, 3);
1261       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1262          (const gl_constant_value *)image_param->swizzling, 2);
1263       param += BRW_IMAGE_PARAM_SIZE;
1264
1265       brw_mark_surface_used(
1266          stage_prog_data,
1267          stage_prog_data->binding_table.image_start + image_idx);
1268    }
1269 }
1270
1271 /**
1272  * Decide which set of clip planes should be used when clipping via
1273  * gl_Position or gl_ClipVertex.
1274  */
1275 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1276 {
1277    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1278       /* There is currently a GLSL vertex shader, so clip according to GLSL
1279        * rules, which means compare gl_ClipVertex (or gl_Position, if
1280        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1281        * that were stored in EyeUserPlane at the time the clip planes were
1282        * specified.
1283        */
1284       return ctx->Transform.EyeUserPlane;
1285    } else {
1286       /* Either we are using fixed function or an ARB vertex program.  In
1287        * either case the clip planes are going to be compared against
1288        * gl_Position (which is in clip coordinates) so we have to clip using
1289        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1290        * core.
1291        */
1292       return ctx->Transform._ClipUserPlane;
1293    }
1294 }
1295
1296 extern "C" const unsigned *
1297 brw_compile_tes(const struct brw_compiler *compiler,
1298                 void *log_data,
1299                 void *mem_ctx,
1300                 const struct brw_tes_prog_key *key,
1301                 struct brw_tes_prog_data *prog_data,
1302                 const nir_shader *src_shader,
1303                 struct gl_shader_program *shader_prog,
1304                 int shader_time_index,
1305                 unsigned *final_assembly_size,
1306                 char **error_str)
1307 {
1308    const struct brw_device_info *devinfo = compiler->devinfo;
1309    struct gl_shader *shader =
1310       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1311    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1312
1313    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1314    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1315    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1316
1317    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1318                        nir->info.outputs_written,
1319                        nir->info.separate_shader);
1320
1321    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1322
1323    assert(output_size_bytes >= 1);
1324    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1325       if (error_str)
1326          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1327       return NULL;
1328    }
1329
1330    /* URB entry sizes are stored as a multiple of 64 bytes. */
1331    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1332
1333    struct brw_vue_map input_vue_map;
1334    brw_compute_tess_vue_map(&input_vue_map,
1335                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1336                             nir->info.patch_inputs_read);
1337
1338    bool need_patch_header = nir->info.system_values_read &
1339       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1340        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1341
1342    /* The TES will pull most inputs using URB read messages.
1343     *
1344     * However, we push the patch header for TessLevel factors when required,
1345     * as it's a tiny amount of extra data.
1346     */
1347    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1348
1349    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1350       fprintf(stderr, "TES Input ");
1351       brw_print_vue_map(stderr, &input_vue_map);
1352       fprintf(stderr, "TES Output ");
1353       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1354    }
1355
1356    if (is_scalar) {
1357       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1358                    &prog_data->base.base, shader->Program, nir, 8,
1359                    shader_time_index, &input_vue_map);
1360       if (!v.run_tes()) {
1361          if (error_str)
1362             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1363          return NULL;
1364       }
1365
1366       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1367
1368       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1369                      &prog_data->base.base, v.promoted_constants, false,
1370                      "TES");
1371       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1372          g.enable_debug(ralloc_asprintf(mem_ctx,
1373                                         "%s tessellation evaluation shader %s",
1374                                         nir->info.label ? nir->info.label
1375                                                         : "unnamed",
1376                                         nir->info.name));
1377       }
1378
1379       g.generate_code(v.cfg, 8);
1380
1381       return g.get_assembly(final_assembly_size);
1382    } else {
1383       unreachable("XXX: vec4 tessellation evalation shaders not merged yet.");
1384    }
1385 }