src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/uniforms.h"
  31
  32 extern "C" void
  33 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  34                       unsigned surf_index)
  35 {
  36    assert(surf_index < BRW_MAX_SURFACES);
  37
  38    prog_data->binding_table.size_bytes =
  39       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  40 }
  41
  42 enum brw_reg_type
  43 brw_type_for_base_type(const struct glsl_type *type)
  44 {
  45    switch (type->base_type) {
  46    case GLSL_TYPE_FLOAT:
  47       return BRW_REGISTER_TYPE_F;
  48    case GLSL_TYPE_INT:
  49    case GLSL_TYPE_BOOL:
  50    case GLSL_TYPE_SUBROUTINE:
  51       return BRW_REGISTER_TYPE_D;
  52    case GLSL_TYPE_UINT:
  53       return BRW_REGISTER_TYPE_UD;
  54    case GLSL_TYPE_ARRAY:
  55       return brw_type_for_base_type(type->fields.array);
  56    case GLSL_TYPE_STRUCT:
  57    case GLSL_TYPE_SAMPLER:
  58    case GLSL_TYPE_ATOMIC_UINT:
  59       /* These should be overridden with the type of the member when
  60        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  61        * way to trip up if we don't.
  62        */
  63       return BRW_REGISTER_TYPE_UD;
  64    case GLSL_TYPE_IMAGE:
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_DOUBLE:
  67       return BRW_REGISTER_TYPE_DF;
  68    case GLSL_TYPE_VOID:
  69    case GLSL_TYPE_ERROR:
  70    case GLSL_TYPE_INTERFACE:
  71    case GLSL_TYPE_FUNCTION:
  72       unreachable("not reached");
  73    }
  74
  75    return BRW_REGISTER_TYPE_F;
  76 }
  77
  78 enum brw_conditional_mod
  79 brw_conditional_for_comparison(unsigned int op)
  80 {
  81    switch (op) {
  82    case ir_binop_less:
  83       return BRW_CONDITIONAL_L;
  84    case ir_binop_greater:
  85       return BRW_CONDITIONAL_G;
  86    case ir_binop_lequal:
  87       return BRW_CONDITIONAL_LE;
  88    case ir_binop_gequal:
  89       return BRW_CONDITIONAL_GE;
  90    case ir_binop_equal:
  91    case ir_binop_all_equal: /* same as equal for scalars */
  92       return BRW_CONDITIONAL_Z;
  93    case ir_binop_nequal:
  94    case ir_binop_any_nequal: /* same as nequal for scalars */
  95       return BRW_CONDITIONAL_NZ;
  96    default:
  97       unreachable("not reached: bad operation for comparison");
  98    }
  99 }
 100
 101 uint32_t
 102 brw_math_function(enum opcode op)
 103 {
 104    switch (op) {
 105    case SHADER_OPCODE_RCP:
 106       return BRW_MATH_FUNCTION_INV;
 107    case SHADER_OPCODE_RSQ:
 108       return BRW_MATH_FUNCTION_RSQ;
 109    case SHADER_OPCODE_SQRT:
 110       return BRW_MATH_FUNCTION_SQRT;
 111    case SHADER_OPCODE_EXP2:
 112       return BRW_MATH_FUNCTION_EXP;
 113    case SHADER_OPCODE_LOG2:
 114       return BRW_MATH_FUNCTION_LOG;
 115    case SHADER_OPCODE_POW:
 116       return BRW_MATH_FUNCTION_POW;
 117    case SHADER_OPCODE_SIN:
 118       return BRW_MATH_FUNCTION_SIN;
 119    case SHADER_OPCODE_COS:
 120       return BRW_MATH_FUNCTION_COS;
 121    case SHADER_OPCODE_INT_QUOTIENT:
 122       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 123    case SHADER_OPCODE_INT_REMAINDER:
 124       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 125    default:
 126       unreachable("not reached: unknown math function");
 127    }
 128 }
 129
 130 uint32_t
 131 brw_texture_offset(int *offsets, unsigned num_components)
 132 {
 133    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 134
 135    /* Combine all three offsets into a single unsigned dword:
 136     *
 137     *    bits 11:8 - U Offset (X component)
 138     *    bits  7:4 - V Offset (Y component)
 139     *    bits  3:0 - R Offset (Z component)
 140     */
 141    unsigned offset_bits = 0;
 142    for (unsigned i = 0; i < num_components; i++) {
 143       const unsigned shift = 4 * (2 - i);
 144       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 145    }
 146    return offset_bits;
 147 }
 148
 149 const char *
 150 brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
 151 {
 152    switch (op) {
 153    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 154       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 155        * start of a loop in the IR.
 156        */
 157       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 158          return "do";
 159
 160       assert(brw_opcode_desc(devinfo, op)->name);
 161       return brw_opcode_desc(devinfo, op)->name;
 162    case FS_OPCODE_FB_WRITE:
 163       return "fb_write";
 164    case FS_OPCODE_FB_WRITE_LOGICAL:
 165       return "fb_write_logical";
 166    case FS_OPCODE_PACK_STENCIL_REF:
 167       return "pack_stencil_ref";
 168    case FS_OPCODE_REP_FB_WRITE:
 169       return "rep_fb_write";
 170
 171    case SHADER_OPCODE_RCP:
 172       return "rcp";
 173    case SHADER_OPCODE_RSQ:
 174       return "rsq";
 175    case SHADER_OPCODE_SQRT:
 176       return "sqrt";
 177    case SHADER_OPCODE_EXP2:
 178       return "exp2";
 179    case SHADER_OPCODE_LOG2:
 180       return "log2";
 181    case SHADER_OPCODE_POW:
 182       return "pow";
 183    case SHADER_OPCODE_INT_QUOTIENT:
 184       return "int_quot";
 185    case SHADER_OPCODE_INT_REMAINDER:
 186       return "int_rem";
 187    case SHADER_OPCODE_SIN:
 188       return "sin";
 189    case SHADER_OPCODE_COS:
 190       return "cos";
 191
 192    case SHADER_OPCODE_TEX:
 193       return "tex";
 194    case SHADER_OPCODE_TEX_LOGICAL:
 195       return "tex_logical";
 196    case SHADER_OPCODE_TXD:
 197       return "txd";
 198    case SHADER_OPCODE_TXD_LOGICAL:
 199       return "txd_logical";
 200    case SHADER_OPCODE_TXF:
 201       return "txf";
 202    case SHADER_OPCODE_TXF_LOGICAL:
 203       return "txf_logical";
 204    case SHADER_OPCODE_TXF_LZ:
 205       return "txf_lz";
 206    case SHADER_OPCODE_TXL:
 207       return "txl";
 208    case SHADER_OPCODE_TXL_LOGICAL:
 209       return "txl_logical";
 210    case SHADER_OPCODE_TXL_LZ:
 211       return "txl_lz";
 212    case SHADER_OPCODE_TXS:
 213       return "txs";
 214    case SHADER_OPCODE_TXS_LOGICAL:
 215       return "txs_logical";
 216    case FS_OPCODE_TXB:
 217       return "txb";
 218    case FS_OPCODE_TXB_LOGICAL:
 219       return "txb_logical";
 220    case SHADER_OPCODE_TXF_CMS:
 221       return "txf_cms";
 222    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 223       return "txf_cms_logical";
 224    case SHADER_OPCODE_TXF_CMS_W:
 225       return "txf_cms_w";
 226    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 227       return "txf_cms_w_logical";
 228    case SHADER_OPCODE_TXF_UMS:
 229       return "txf_ums";
 230    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 231       return "txf_ums_logical";
 232    case SHADER_OPCODE_TXF_MCS:
 233       return "txf_mcs";
 234    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 235       return "txf_mcs_logical";
 236    case SHADER_OPCODE_LOD:
 237       return "lod";
 238    case SHADER_OPCODE_LOD_LOGICAL:
 239       return "lod_logical";
 240    case SHADER_OPCODE_TG4:
 241       return "tg4";
 242    case SHADER_OPCODE_TG4_LOGICAL:
 243       return "tg4_logical";
 244    case SHADER_OPCODE_TG4_OFFSET:
 245       return "tg4_offset";
 246    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 247       return "tg4_offset_logical";
 248    case SHADER_OPCODE_SAMPLEINFO:
 249       return "sampleinfo";
 250    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 251       return "sampleinfo_logical";
 252
 253    case SHADER_OPCODE_SHADER_TIME_ADD:
 254       return "shader_time_add";
 255
 256    case SHADER_OPCODE_UNTYPED_ATOMIC:
 257       return "untyped_atomic";
 258    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 259       return "untyped_atomic_logical";
 260    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 261       return "untyped_surface_read";
 262    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 263       return "untyped_surface_read_logical";
 264    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 265       return "untyped_surface_write";
 266    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 267       return "untyped_surface_write_logical";
 268    case SHADER_OPCODE_TYPED_ATOMIC:
 269       return "typed_atomic";
 270    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 271       return "typed_atomic_logical";
 272    case SHADER_OPCODE_TYPED_SURFACE_READ:
 273       return "typed_surface_read";
 274    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 275       return "typed_surface_read_logical";
 276    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 277       return "typed_surface_write";
 278    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 279       return "typed_surface_write_logical";
 280    case SHADER_OPCODE_MEMORY_FENCE:
 281       return "memory_fence";
 282
 283    case SHADER_OPCODE_LOAD_PAYLOAD:
 284       return "load_payload";
 285    case FS_OPCODE_PACK:
 286       return "pack";
 287
 288    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 289       return "gen4_scratch_read";
 290    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 291       return "gen4_scratch_write";
 292    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 293       return "gen7_scratch_read";
 294    case SHADER_OPCODE_URB_WRITE_SIMD8:
 295       return "gen8_urb_write_simd8";
 296    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 297       return "gen8_urb_write_simd8_per_slot";
 298    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 299       return "gen8_urb_write_simd8_masked";
 300    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 301       return "gen8_urb_write_simd8_masked_per_slot";
 302    case SHADER_OPCODE_URB_READ_SIMD8:
 303       return "urb_read_simd8";
 304    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 305       return "urb_read_simd8_per_slot";
 306
 307    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 308       return "find_live_channel";
 309    case SHADER_OPCODE_BROADCAST:
 310       return "broadcast";
 311
 312    case SHADER_OPCODE_EXTRACT_BYTE:
 313       return "extract_byte";
 314    case SHADER_OPCODE_EXTRACT_WORD:
 315       return "extract_word";
 316    case VEC4_OPCODE_MOV_BYTES:
 317       return "mov_bytes";
 318    case VEC4_OPCODE_PACK_BYTES:
 319       return "pack_bytes";
 320    case VEC4_OPCODE_UNPACK_UNIFORM:
 321       return "unpack_uniform";
 322
 323    case FS_OPCODE_DDX_COARSE:
 324       return "ddx_coarse";
 325    case FS_OPCODE_DDX_FINE:
 326       return "ddx_fine";
 327    case FS_OPCODE_DDY_COARSE:
 328       return "ddy_coarse";
 329    case FS_OPCODE_DDY_FINE:
 330       return "ddy_fine";
 331
 332    case FS_OPCODE_CINTERP:
 333       return "cinterp";
 334    case FS_OPCODE_LINTERP:
 335       return "linterp";
 336
 337    case FS_OPCODE_PIXEL_X:
 338       return "pixel_x";
 339    case FS_OPCODE_PIXEL_Y:
 340       return "pixel_y";
 341
 342    case FS_OPCODE_GET_BUFFER_SIZE:
 343       return "fs_get_buffer_size";
 344
 345    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 346       return "uniform_pull_const";
 347    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 348       return "uniform_pull_const_gen7";
 349    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 350       return "varying_pull_const_gen4";
 351    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 352       return "varying_pull_const_gen7";
 353    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 354       return "varying_pull_const_logical";
 355
 356    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 357       return "mov_dispatch_to_flags";
 358    case FS_OPCODE_DISCARD_JUMP:
 359       return "discard_jump";
 360
 361    case FS_OPCODE_SET_SAMPLE_ID:
 362       return "set_sample_id";
 363    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 364       return "set_simd4x2_offset";
 365
 366    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 367       return "pack_half_2x16_split";
 368    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 369       return "unpack_half_2x16_split_x";
 370    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 371       return "unpack_half_2x16_split_y";
 372
 373    case FS_OPCODE_PLACEHOLDER_HALT:
 374       return "placeholder_halt";
 375
 376    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 377       return "interp_centroid";
 378    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 379       return "interp_sample";
 380    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 381       return "interp_shared_offset";
 382    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 383       return "interp_per_slot_offset";
 384
 385    case VS_OPCODE_URB_WRITE:
 386       return "vs_urb_write";
 387    case VS_OPCODE_PULL_CONSTANT_LOAD:
 388       return "pull_constant_load";
 389    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 390       return "pull_constant_load_gen7";
 391
 392    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 393       return "set_simd4x2_header_gen9";
 394
 395    case VS_OPCODE_GET_BUFFER_SIZE:
 396       return "vs_get_buffer_size";
 397
 398    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 399       return "unpack_flags_simd4x2";
 400
 401    case GS_OPCODE_URB_WRITE:
 402       return "gs_urb_write";
 403    case GS_OPCODE_URB_WRITE_ALLOCATE:
 404       return "gs_urb_write_allocate";
 405    case GS_OPCODE_THREAD_END:
 406       return "gs_thread_end";
 407    case GS_OPCODE_SET_WRITE_OFFSET:
 408       return "set_write_offset";
 409    case GS_OPCODE_SET_VERTEX_COUNT:
 410       return "set_vertex_count";
 411    case GS_OPCODE_SET_DWORD_2:
 412       return "set_dword_2";
 413    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 414       return "prepare_channel_masks";
 415    case GS_OPCODE_SET_CHANNEL_MASKS:
 416       return "set_channel_masks";
 417    case GS_OPCODE_GET_INSTANCE_ID:
 418       return "get_instance_id";
 419    case GS_OPCODE_FF_SYNC:
 420       return "ff_sync";
 421    case GS_OPCODE_SET_PRIMITIVE_ID:
 422       return "set_primitive_id";
 423    case GS_OPCODE_SVB_WRITE:
 424       return "gs_svb_write";
 425    case GS_OPCODE_SVB_SET_DST_INDEX:
 426       return "gs_svb_set_dst_index";
 427    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 428       return "gs_ff_sync_set_primitives";
 429    case CS_OPCODE_CS_TERMINATE:
 430       return "cs_terminate";
 431    case SHADER_OPCODE_BARRIER:
 432       return "barrier";
 433    case SHADER_OPCODE_MULH:
 434       return "mulh";
 435    case SHADER_OPCODE_MOV_INDIRECT:
 436       return "mov_indirect";
 437
 438    case VEC4_OPCODE_URB_READ:
 439       return "urb_read";
 440    case TCS_OPCODE_GET_INSTANCE_ID:
 441       return "tcs_get_instance_id";
 442    case TCS_OPCODE_URB_WRITE:
 443       return "tcs_urb_write";
 444    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 445       return "tcs_set_input_urb_offsets";
 446    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 447       return "tcs_set_output_urb_offsets";
 448    case TCS_OPCODE_GET_PRIMITIVE_ID:
 449       return "tcs_get_primitive_id";
 450    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 451       return "tcs_create_barrier_header";
 452    case TCS_OPCODE_SRC0_010_IS_ZERO:
 453       return "tcs_src0<0,1,0>_is_zero";
 454    case TCS_OPCODE_RELEASE_INPUT:
 455       return "tcs_release_input";
 456    case TCS_OPCODE_THREAD_END:
 457       return "tcs_thread_end";
 458    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 459       return "tes_create_input_read_header";
 460    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 461       return "tes_add_indirect_urb_offset";
 462    case TES_OPCODE_GET_PRIMITIVE_ID:
 463       return "tes_get_primitive_id";
 464    }
 465
 466    unreachable("not reached");
 467 }
 468
 469 bool
 470 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 471 {
 472    union {
 473       unsigned ud;
 474       int d;
 475       float f;
 476       double df;
 477    } imm, sat_imm = { 0 };
 478
 479    const unsigned size = type_sz(type);
 480
 481    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 482     * irrelevant, so just check the size of the type and copy from/to an
 483     * appropriately sized field.
 484     */
 485    if (size < 8)
 486       imm.ud = reg->ud;
 487    else
 488       imm.df = reg->df;
 489
 490    switch (type) {
 491    case BRW_REGISTER_TYPE_UD:
 492    case BRW_REGISTER_TYPE_D:
 493    case BRW_REGISTER_TYPE_UW:
 494    case BRW_REGISTER_TYPE_W:
 495    case BRW_REGISTER_TYPE_UQ:
 496    case BRW_REGISTER_TYPE_Q:
 497       /* Nothing to do. */
 498       return false;
 499    case BRW_REGISTER_TYPE_F:
 500       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 501       break;
 502    case BRW_REGISTER_TYPE_DF:
 503       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 504       break;
 505    case BRW_REGISTER_TYPE_UB:
 506    case BRW_REGISTER_TYPE_B:
 507       unreachable("no UB/B immediates");
 508    case BRW_REGISTER_TYPE_V:
 509    case BRW_REGISTER_TYPE_UV:
 510    case BRW_REGISTER_TYPE_VF:
 511       unreachable("unimplemented: saturate vector immediate");
 512    case BRW_REGISTER_TYPE_HF:
 513       unreachable("unimplemented: saturate HF immediate");
 514    }
 515
 516    if (size < 8) {
 517       if (imm.ud != sat_imm.ud) {
 518          reg->ud = sat_imm.ud;
 519          return true;
 520       }
 521    } else {
 522       if (imm.df != sat_imm.df) {
 523          reg->df = sat_imm.df;
 524          return true;
 525       }
 526    }
 527    return false;
 528 }
 529
 530 bool
 531 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 532 {
 533    switch (type) {
 534    case BRW_REGISTER_TYPE_D:
 535    case BRW_REGISTER_TYPE_UD:
 536       reg->d = -reg->d;
 537       return true;
 538    case BRW_REGISTER_TYPE_W:
 539    case BRW_REGISTER_TYPE_UW:
 540       reg->d = -(int16_t)reg->ud;
 541       return true;
 542    case BRW_REGISTER_TYPE_F:
 543       reg->f = -reg->f;
 544       return true;
 545    case BRW_REGISTER_TYPE_VF:
 546       reg->ud ^= 0x80808080;
 547       return true;
 548    case BRW_REGISTER_TYPE_DF:
 549       reg->df = -reg->df;
 550       return true;
 551    case BRW_REGISTER_TYPE_UB:
 552    case BRW_REGISTER_TYPE_B:
 553       unreachable("no UB/B immediates");
 554    case BRW_REGISTER_TYPE_UV:
 555    case BRW_REGISTER_TYPE_V:
 556       assert(!"unimplemented: negate UV/V immediate");
 557    case BRW_REGISTER_TYPE_UQ:
 558    case BRW_REGISTER_TYPE_Q:
 559       assert(!"unimplemented: negate UQ/Q immediate");
 560    case BRW_REGISTER_TYPE_HF:
 561       assert(!"unimplemented: negate HF immediate");
 562    }
 563
 564    return false;
 565 }
 566
 567 bool
 568 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 569 {
 570    switch (type) {
 571    case BRW_REGISTER_TYPE_D:
 572       reg->d = abs(reg->d);
 573       return true;
 574    case BRW_REGISTER_TYPE_W:
 575       reg->d = abs((int16_t)reg->ud);
 576       return true;
 577    case BRW_REGISTER_TYPE_F:
 578       reg->f = fabsf(reg->f);
 579       return true;
 580    case BRW_REGISTER_TYPE_DF:
 581       reg->df = fabs(reg->df);
 582       return true;
 583    case BRW_REGISTER_TYPE_VF:
 584       reg->ud &= ~0x80808080;
 585       return true;
 586    case BRW_REGISTER_TYPE_UB:
 587    case BRW_REGISTER_TYPE_B:
 588       unreachable("no UB/B immediates");
 589    case BRW_REGISTER_TYPE_UQ:
 590    case BRW_REGISTER_TYPE_UD:
 591    case BRW_REGISTER_TYPE_UW:
 592    case BRW_REGISTER_TYPE_UV:
 593       /* Presumably the absolute value modifier on an unsigned source is a
 594        * nop, but it would be nice to confirm.
 595        */
 596       assert(!"unimplemented: abs unsigned immediate");
 597    case BRW_REGISTER_TYPE_V:
 598       assert(!"unimplemented: abs V immediate");
 599    case BRW_REGISTER_TYPE_Q:
 600       assert(!"unimplemented: abs Q immediate");
 601    case BRW_REGISTER_TYPE_HF:
 602       assert(!"unimplemented: abs HF immediate");
 603    }
 604
 605    return false;
 606 }
 607
 608 unsigned
 609 tesslevel_outer_components(GLenum tes_primitive_mode)
 610 {
 611    switch (tes_primitive_mode) {
 612    case GL_QUADS:
 613       return 4;
 614    case GL_TRIANGLES:
 615       return 3;
 616    case GL_ISOLINES:
 617       return 2;
 618    default:
 619       unreachable("Bogus tessellation domain");
 620    }
 621    return 0;
 622 }
 623
 624 unsigned
 625 tesslevel_inner_components(GLenum tes_primitive_mode)
 626 {
 627    switch (tes_primitive_mode) {
 628    case GL_QUADS:
 629       return 2;
 630    case GL_TRIANGLES:
 631       return 1;
 632    case GL_ISOLINES:
 633       return 0;
 634    default:
 635       unreachable("Bogus tessellation domain");
 636    }
 637    return 0;
 638 }
 639
 640 /**
 641  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 642  * that's stored backwards, i.e. .wzyx.
 643  */
 644 unsigned
 645 writemask_for_backwards_vector(unsigned mask)
 646 {
 647    unsigned new_mask = 0;
 648
 649    for (int i = 0; i < 4; i++)
 650       new_mask |= ((mask >> i) & 1) << (3 - i);
 651
 652    return new_mask;
 653 }
 654
 655 backend_shader::backend_shader(const struct brw_compiler *compiler,
 656                                void *log_data,
 657                                void *mem_ctx,
 658                                const nir_shader *shader,
 659                                struct brw_stage_prog_data *stage_prog_data)
 660    : compiler(compiler),
 661      log_data(log_data),
 662      devinfo(compiler->devinfo),
 663      nir(shader),
 664      stage_prog_data(stage_prog_data),
 665      mem_ctx(mem_ctx),
 666      cfg(NULL),
 667      stage(shader->stage)
 668 {
 669    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 670    stage_name = _mesa_shader_stage_to_string(stage);
 671    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 672    is_passthrough_shader =
 673       nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
 674 }
 675
 676 bool
 677 backend_reg::equals(const backend_reg &r) const
 678 {
 679    return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
 680 }
 681
 682 bool
 683 backend_reg::is_zero() const
 684 {
 685    if (file != IMM)
 686       return false;
 687
 688    switch (type) {
 689    case BRW_REGISTER_TYPE_F:
 690       return f == 0;
 691    case BRW_REGISTER_TYPE_DF:
 692       return df == 0;
 693    case BRW_REGISTER_TYPE_D:
 694    case BRW_REGISTER_TYPE_UD:
 695       return d == 0;
 696    default:
 697       return false;
 698    }
 699 }
 700
 701 bool
 702 backend_reg::is_one() const
 703 {
 704    if (file != IMM)
 705       return false;
 706
 707    switch (type) {
 708    case BRW_REGISTER_TYPE_F:
 709       return f == 1.0f;
 710    case BRW_REGISTER_TYPE_DF:
 711       return df == 1.0;
 712    case BRW_REGISTER_TYPE_D:
 713    case BRW_REGISTER_TYPE_UD:
 714       return d == 1;
 715    default:
 716       return false;
 717    }
 718 }
 719
 720 bool
 721 backend_reg::is_negative_one() const
 722 {
 723    if (file != IMM)
 724       return false;
 725
 726    switch (type) {
 727    case BRW_REGISTER_TYPE_F:
 728       return f == -1.0;
 729    case BRW_REGISTER_TYPE_DF:
 730       return df == -1.0;
 731    case BRW_REGISTER_TYPE_D:
 732       return d == -1;
 733    default:
 734       return false;
 735    }
 736 }
 737
 738 bool
 739 backend_reg::is_null() const
 740 {
 741    return file == ARF && nr == BRW_ARF_NULL;
 742 }
 743
 744
 745 bool
 746 backend_reg::is_accumulator() const
 747 {
 748    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 749 }
 750
 751 bool
 752 backend_reg::in_range(const backend_reg &r, unsigned n) const
 753 {
 754    return (file == r.file &&
 755            nr == r.nr &&
 756            reg_offset >= r.reg_offset &&
 757            reg_offset < r.reg_offset + n);
 758 }
 759
 760 bool
 761 backend_instruction::is_commutative() const
 762 {
 763    switch (opcode) {
 764    case BRW_OPCODE_AND:
 765    case BRW_OPCODE_OR:
 766    case BRW_OPCODE_XOR:
 767    case BRW_OPCODE_ADD:
 768    case BRW_OPCODE_MUL:
 769    case SHADER_OPCODE_MULH:
 770       return true;
 771    case BRW_OPCODE_SEL:
 772       /* MIN and MAX are commutative. */
 773       if (conditional_mod == BRW_CONDITIONAL_GE ||
 774           conditional_mod == BRW_CONDITIONAL_L) {
 775          return true;
 776       }
 777       /* fallthrough */
 778    default:
 779       return false;
 780    }
 781 }
 782
 783 bool
 784 backend_instruction::is_3src(const struct brw_device_info *devinfo) const
 785 {
 786    return ::is_3src(devinfo, opcode);
 787 }
 788
 789 bool
 790 backend_instruction::is_tex() const
 791 {
 792    return (opcode == SHADER_OPCODE_TEX ||
 793            opcode == FS_OPCODE_TXB ||
 794            opcode == SHADER_OPCODE_TXD ||
 795            opcode == SHADER_OPCODE_TXF ||
 796            opcode == SHADER_OPCODE_TXF_LZ ||
 797            opcode == SHADER_OPCODE_TXF_CMS ||
 798            opcode == SHADER_OPCODE_TXF_CMS_W ||
 799            opcode == SHADER_OPCODE_TXF_UMS ||
 800            opcode == SHADER_OPCODE_TXF_MCS ||
 801            opcode == SHADER_OPCODE_TXL ||
 802            opcode == SHADER_OPCODE_TXL_LZ ||
 803            opcode == SHADER_OPCODE_TXS ||
 804            opcode == SHADER_OPCODE_LOD ||
 805            opcode == SHADER_OPCODE_TG4 ||
 806            opcode == SHADER_OPCODE_TG4_OFFSET ||
 807            opcode == SHADER_OPCODE_SAMPLEINFO);
 808 }
 809
 810 bool
 811 backend_instruction::is_math() const
 812 {
 813    return (opcode == SHADER_OPCODE_RCP ||
 814            opcode == SHADER_OPCODE_RSQ ||
 815            opcode == SHADER_OPCODE_SQRT ||
 816            opcode == SHADER_OPCODE_EXP2 ||
 817            opcode == SHADER_OPCODE_LOG2 ||
 818            opcode == SHADER_OPCODE_SIN ||
 819            opcode == SHADER_OPCODE_COS ||
 820            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 821            opcode == SHADER_OPCODE_INT_REMAINDER ||
 822            opcode == SHADER_OPCODE_POW);
 823 }
 824
 825 bool
 826 backend_instruction::is_control_flow() const
 827 {
 828    switch (opcode) {
 829    case BRW_OPCODE_DO:
 830    case BRW_OPCODE_WHILE:
 831    case BRW_OPCODE_IF:
 832    case BRW_OPCODE_ELSE:
 833    case BRW_OPCODE_ENDIF:
 834    case BRW_OPCODE_BREAK:
 835    case BRW_OPCODE_CONTINUE:
 836       return true;
 837    default:
 838       return false;
 839    }
 840 }
 841
 842 bool
 843 backend_instruction::can_do_source_mods() const
 844 {
 845    switch (opcode) {
 846    case BRW_OPCODE_ADDC:
 847    case BRW_OPCODE_BFE:
 848    case BRW_OPCODE_BFI1:
 849    case BRW_OPCODE_BFI2:
 850    case BRW_OPCODE_BFREV:
 851    case BRW_OPCODE_CBIT:
 852    case BRW_OPCODE_FBH:
 853    case BRW_OPCODE_FBL:
 854    case BRW_OPCODE_SUBB:
 855       return false;
 856    default:
 857       return true;
 858    }
 859 }
 860
 861 bool
 862 backend_instruction::can_do_saturate() const
 863 {
 864    switch (opcode) {
 865    case BRW_OPCODE_ADD:
 866    case BRW_OPCODE_ASR:
 867    case BRW_OPCODE_AVG:
 868    case BRW_OPCODE_DP2:
 869    case BRW_OPCODE_DP3:
 870    case BRW_OPCODE_DP4:
 871    case BRW_OPCODE_DPH:
 872    case BRW_OPCODE_F16TO32:
 873    case BRW_OPCODE_F32TO16:
 874    case BRW_OPCODE_LINE:
 875    case BRW_OPCODE_LRP:
 876    case BRW_OPCODE_MAC:
 877    case BRW_OPCODE_MAD:
 878    case BRW_OPCODE_MATH:
 879    case BRW_OPCODE_MOV:
 880    case BRW_OPCODE_MUL:
 881    case SHADER_OPCODE_MULH:
 882    case BRW_OPCODE_PLN:
 883    case BRW_OPCODE_RNDD:
 884    case BRW_OPCODE_RNDE:
 885    case BRW_OPCODE_RNDU:
 886    case BRW_OPCODE_RNDZ:
 887    case BRW_OPCODE_SEL:
 888    case BRW_OPCODE_SHL:
 889    case BRW_OPCODE_SHR:
 890    case FS_OPCODE_LINTERP:
 891    case SHADER_OPCODE_COS:
 892    case SHADER_OPCODE_EXP2:
 893    case SHADER_OPCODE_LOG2:
 894    case SHADER_OPCODE_POW:
 895    case SHADER_OPCODE_RCP:
 896    case SHADER_OPCODE_RSQ:
 897    case SHADER_OPCODE_SIN:
 898    case SHADER_OPCODE_SQRT:
 899       return true;
 900    default:
 901       return false;
 902    }
 903 }
 904
 905 bool
 906 backend_instruction::can_do_cmod() const
 907 {
 908    switch (opcode) {
 909    case BRW_OPCODE_ADD:
 910    case BRW_OPCODE_ADDC:
 911    case BRW_OPCODE_AND:
 912    case BRW_OPCODE_ASR:
 913    case BRW_OPCODE_AVG:
 914    case BRW_OPCODE_CMP:
 915    case BRW_OPCODE_CMPN:
 916    case BRW_OPCODE_DP2:
 917    case BRW_OPCODE_DP3:
 918    case BRW_OPCODE_DP4:
 919    case BRW_OPCODE_DPH:
 920    case BRW_OPCODE_F16TO32:
 921    case BRW_OPCODE_F32TO16:
 922    case BRW_OPCODE_FRC:
 923    case BRW_OPCODE_LINE:
 924    case BRW_OPCODE_LRP:
 925    case BRW_OPCODE_LZD:
 926    case BRW_OPCODE_MAC:
 927    case BRW_OPCODE_MACH:
 928    case BRW_OPCODE_MAD:
 929    case BRW_OPCODE_MOV:
 930    case BRW_OPCODE_MUL:
 931    case BRW_OPCODE_NOT:
 932    case BRW_OPCODE_OR:
 933    case BRW_OPCODE_PLN:
 934    case BRW_OPCODE_RNDD:
 935    case BRW_OPCODE_RNDE:
 936    case BRW_OPCODE_RNDU:
 937    case BRW_OPCODE_RNDZ:
 938    case BRW_OPCODE_SAD2:
 939    case BRW_OPCODE_SADA2:
 940    case BRW_OPCODE_SHL:
 941    case BRW_OPCODE_SHR:
 942    case BRW_OPCODE_SUBB:
 943    case BRW_OPCODE_XOR:
 944    case FS_OPCODE_CINTERP:
 945    case FS_OPCODE_LINTERP:
 946       return true;
 947    default:
 948       return false;
 949    }
 950 }
 951
 952 bool
 953 backend_instruction::reads_accumulator_implicitly() const
 954 {
 955    switch (opcode) {
 956    case BRW_OPCODE_MAC:
 957    case BRW_OPCODE_MACH:
 958    case BRW_OPCODE_SADA2:
 959       return true;
 960    default:
 961       return false;
 962    }
 963 }
 964
 965 bool
 966 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 967 {
 968    return writes_accumulator ||
 969           (devinfo->gen < 6 &&
 970            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 971             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 972              opcode != FS_OPCODE_CINTERP)));
 973 }
 974
 975 bool
 976 backend_instruction::has_side_effects() const
 977 {
 978    switch (opcode) {
 979    case SHADER_OPCODE_UNTYPED_ATOMIC:
 980    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 981    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 982    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 983    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 984    case SHADER_OPCODE_TYPED_ATOMIC:
 985    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 986    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 987    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 988    case SHADER_OPCODE_MEMORY_FENCE:
 989    case SHADER_OPCODE_URB_WRITE_SIMD8:
 990    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 991    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 992    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 993    case FS_OPCODE_FB_WRITE:
 994    case SHADER_OPCODE_BARRIER:
 995    case TCS_OPCODE_URB_WRITE:
 996    case TCS_OPCODE_RELEASE_INPUT:
 997       return true;
 998    default:
 999       return false;
1000    }
1001 }
1002
1003 bool
1004 backend_instruction::is_volatile() const
1005 {
1006    switch (opcode) {
1007    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1008    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1009    case SHADER_OPCODE_TYPED_SURFACE_READ:
1010    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1011    case SHADER_OPCODE_URB_READ_SIMD8:
1012    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1013    case VEC4_OPCODE_URB_READ:
1014       return true;
1015    default:
1016       return false;
1017    }
1018 }
1019
1020 #ifndef NDEBUG
1021 static bool
1022 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1023 {
1024    bool found = false;
1025    foreach_inst_in_block (backend_instruction, i, block) {
1026       if (inst == i) {
1027          found = true;
1028       }
1029    }
1030    return found;
1031 }
1032 #endif
1033
1034 static void
1035 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1036 {
1037    for (bblock_t *block_iter = start_block->next();
1038         block_iter;
1039         block_iter = block_iter->next()) {
1040       block_iter->start_ip += ip_adjustment;
1041       block_iter->end_ip += ip_adjustment;
1042    }
1043 }
1044
1045 void
1046 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1047 {
1048    assert(this != inst);
1049
1050    if (!this->is_head_sentinel())
1051       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1052
1053    block->end_ip++;
1054
1055    adjust_later_block_ips(block, 1);
1056
1057    exec_node::insert_after(inst);
1058 }
1059
1060 void
1061 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1062 {
1063    assert(this != inst);
1064
1065    if (!this->is_tail_sentinel())
1066       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1067
1068    block->end_ip++;
1069
1070    adjust_later_block_ips(block, 1);
1071
1072    exec_node::insert_before(inst);
1073 }
1074
1075 void
1076 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1077 {
1078    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1079
1080    unsigned num_inst = list->length();
1081
1082    block->end_ip += num_inst;
1083
1084    adjust_later_block_ips(block, num_inst);
1085
1086    exec_node::insert_before(list);
1087 }
1088
1089 void
1090 backend_instruction::remove(bblock_t *block)
1091 {
1092    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1093
1094    adjust_later_block_ips(block, -1);
1095
1096    if (block->start_ip == block->end_ip) {
1097       block->cfg->remove_block(block);
1098    } else {
1099       block->end_ip--;
1100    }
1101
1102    exec_node::remove();
1103 }
1104
1105 void
1106 backend_shader::dump_instructions()
1107 {
1108    dump_instructions(NULL);
1109 }
1110
1111 void
1112 backend_shader::dump_instructions(const char *name)
1113 {
1114    FILE *file = stderr;
1115    if (name && geteuid() != 0) {
1116       file = fopen(name, "w");
1117       if (!file)
1118          file = stderr;
1119    }
1120
1121    if (cfg) {
1122       int ip = 0;
1123       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1124          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1125             fprintf(file, "%4d: ", ip++);
1126          dump_instruction(inst, file);
1127       }
1128    } else {
1129       int ip = 0;
1130       foreach_in_list(backend_instruction, inst, &instructions) {
1131          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1132             fprintf(file, "%4d: ", ip++);
1133          dump_instruction(inst, file);
1134       }
1135    }
1136
1137    if (file != stderr) {
1138       fclose(file);
1139    }
1140 }
1141
1142 void
1143 backend_shader::calculate_cfg()
1144 {
1145    if (this->cfg)
1146       return;
1147    cfg = new(mem_ctx) cfg_t(&this->instructions);
1148 }
1149
1150 /**
1151  * Sets up the starting offsets for the groups of binding table entries
1152  * commong to all pipeline stages.
1153  *
1154  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1155  * unused but also make sure that addition of small offsets to them will
1156  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1157  */
1158 void
1159 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1160                                         const struct brw_device_info *devinfo,
1161                                         const struct gl_shader_program *shader_prog,
1162                                         const struct gl_program *prog,
1163                                         struct brw_stage_prog_data *stage_prog_data,
1164                                         uint32_t next_binding_table_offset)
1165 {
1166    const struct gl_shader *shader = NULL;
1167    int num_textures = _mesa_fls(prog->SamplersUsed);
1168
1169    if (shader_prog)
1170       shader = shader_prog->_LinkedShaders[stage];
1171
1172    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1173    next_binding_table_offset += num_textures;
1174
1175    if (shader) {
1176       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1177       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1178       next_binding_table_offset += shader->NumUniformBlocks;
1179
1180       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1181       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1182       next_binding_table_offset += shader->NumShaderStorageBlocks;
1183    } else {
1184       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1185       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1186    }
1187
1188    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1189       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1190       next_binding_table_offset++;
1191    } else {
1192       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1193    }
1194
1195    if (prog->UsesGather) {
1196       if (devinfo->gen >= 8) {
1197          stage_prog_data->binding_table.gather_texture_start =
1198             stage_prog_data->binding_table.texture_start;
1199       } else {
1200          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1201          next_binding_table_offset += num_textures;
1202       }
1203    } else {
1204       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1205    }
1206
1207    if (shader && shader->NumAtomicBuffers) {
1208       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1209       next_binding_table_offset += shader->NumAtomicBuffers;
1210    } else {
1211       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1212    }
1213
1214    if (shader && shader->NumImages) {
1215       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1216       next_binding_table_offset += shader->NumImages;
1217    } else {
1218       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1219    }
1220
1221    /* This may or may not be used depending on how the compile goes. */
1222    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1223    next_binding_table_offset++;
1224
1225    /* Plane 0 is just the regular texture section */
1226    stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
1227
1228    stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
1229    next_binding_table_offset += num_textures;
1230
1231    stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
1232    next_binding_table_offset += num_textures;
1233
1234    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1235
1236    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1237 }
1238
1239 static void
1240 setup_vec4_uniform_value(const gl_constant_value **params,
1241                          const gl_constant_value *values,
1242                          unsigned n)
1243 {
1244    static const gl_constant_value zero = { 0 };
1245
1246    for (unsigned i = 0; i < n; ++i)
1247       params[i] = &values[i];
1248
1249    for (unsigned i = n; i < 4; ++i)
1250       params[i] = &zero;
1251 }
1252
1253 void
1254 brw_setup_image_uniform_values(gl_shader_stage stage,
1255                                struct brw_stage_prog_data *stage_prog_data,
1256                                unsigned param_start_index,
1257                                const gl_uniform_storage *storage)
1258 {
1259    const gl_constant_value **param =
1260       &stage_prog_data->param[param_start_index];
1261
1262    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1263       const unsigned image_idx = storage->opaque[stage].index + i;
1264       const brw_image_param *image_param =
1265          &stage_prog_data->image_param[image_idx];
1266
1267       /* Upload the brw_image_param structure.  The order is expected to match
1268        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1269        */
1270       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1271          (const gl_constant_value *)&image_param->surface_idx, 1);
1272       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1273          (const gl_constant_value *)image_param->offset, 2);
1274       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1275          (const gl_constant_value *)image_param->size, 3);
1276       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1277          (const gl_constant_value *)image_param->stride, 4);
1278       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1279          (const gl_constant_value *)image_param->tiling, 3);
1280       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1281          (const gl_constant_value *)image_param->swizzling, 2);
1282       param += BRW_IMAGE_PARAM_SIZE;
1283
1284       brw_mark_surface_used(
1285          stage_prog_data,
1286          stage_prog_data->binding_table.image_start + image_idx);
1287    }
1288 }
1289
1290 /**
1291  * Decide which set of clip planes should be used when clipping via
1292  * gl_Position or gl_ClipVertex.
1293  */
1294 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1295 {
1296    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1297       /* There is currently a GLSL vertex shader, so clip according to GLSL
1298        * rules, which means compare gl_ClipVertex (or gl_Position, if
1299        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1300        * that were stored in EyeUserPlane at the time the clip planes were
1301        * specified.
1302        */
1303       return ctx->Transform.EyeUserPlane;
1304    } else {
1305       /* Either we are using fixed function or an ARB vertex program.  In
1306        * either case the clip planes are going to be compared against
1307        * gl_Position (which is in clip coordinates) so we have to clip using
1308        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1309        * core.
1310        */
1311       return ctx->Transform._ClipUserPlane;
1312    }
1313 }
1314
1315 extern "C" const unsigned *
1316 brw_compile_tes(const struct brw_compiler *compiler,
1317                 void *log_data,
1318                 void *mem_ctx,
1319                 const struct brw_tes_prog_key *key,
1320                 struct brw_tes_prog_data *prog_data,
1321                 const nir_shader *src_shader,
1322                 struct gl_shader_program *shader_prog,
1323                 int shader_time_index,
1324                 unsigned *final_assembly_size,
1325                 char **error_str)
1326 {
1327    const struct brw_device_info *devinfo = compiler->devinfo;
1328    struct gl_shader *shader =
1329       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1330    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1331
1332    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1333    nir->info.inputs_read = key->inputs_read;
1334    nir->info.patch_inputs_read = key->patch_inputs_read;
1335
1336    struct brw_vue_map input_vue_map;
1337    brw_compute_tess_vue_map(&input_vue_map,
1338                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1339                             nir->info.patch_inputs_read);
1340
1341    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1342    brw_nir_lower_tes_inputs(nir, &input_vue_map);
1343    brw_nir_lower_vue_outputs(nir, is_scalar);
1344    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1345
1346    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1347                        nir->info.outputs_written,
1348                        nir->info.separate_shader);
1349
1350    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1351
1352    assert(output_size_bytes >= 1);
1353    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1354       if (error_str)
1355          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1356       return NULL;
1357    }
1358
1359    /* URB entry sizes are stored as a multiple of 64 bytes. */
1360    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1361
1362    bool need_patch_header = nir->info.system_values_read &
1363       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1364        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1365
1366    /* The TES will pull most inputs using URB read messages.
1367     *
1368     * However, we push the patch header for TessLevel factors when required,
1369     * as it's a tiny amount of extra data.
1370     */
1371    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1372
1373    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1374       fprintf(stderr, "TES Input ");
1375       brw_print_vue_map(stderr, &input_vue_map);
1376       fprintf(stderr, "TES Output ");
1377       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1378    }
1379
1380    if (is_scalar) {
1381       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1382                    &prog_data->base.base, shader->Program, nir, 8,
1383                    shader_time_index, &input_vue_map);
1384       if (!v.run_tes()) {
1385          if (error_str)
1386             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1387          return NULL;
1388       }
1389
1390       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1391       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1392
1393       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1394                      &prog_data->base.base, v.promoted_constants, false,
1395                      MESA_SHADER_TESS_EVAL);
1396       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1397          g.enable_debug(ralloc_asprintf(mem_ctx,
1398                                         "%s tessellation evaluation shader %s",
1399                                         nir->info.label ? nir->info.label
1400                                                         : "unnamed",
1401                                         nir->info.name));
1402       }
1403
1404       g.generate_code(v.cfg, 8);
1405
1406       return g.get_assembly(final_assembly_size);
1407    } else {
1408       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1409                               nir, mem_ctx, shader_time_index);
1410       if (!v.run()) {
1411          if (error_str)
1412             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1413          return NULL;
1414       }
1415
1416       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1417          v.dump_instructions();
1418
1419       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1420                                         &prog_data->base, v.cfg,
1421                                         final_assembly_size);
1422    }
1423 }