src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "glsl/glsl_parser_extras.h"
  31 #include "main/shaderobj.h"
  32 #include "main/uniforms.h"
  33 #include "util/debug.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  88       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  89    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = false;
  90    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
  91       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
  92    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  93       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  94    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  95    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  96
  97    nir_shader_compiler_options *nir_options =
  98       rzalloc(compiler, nir_shader_compiler_options);
  99    nir_options->native_integers = true;
 100    /* In order to help allow for better CSE at the NIR level we tell NIR
 101     * to split all ffma instructions during opt_algebraic and we then
 102     * re-combine them as a later step.
 103     */
 104    nir_options->lower_ffma = true;
 105    nir_options->lower_sub = true;
 106    /* In the vec4 backend, our dpN instruction replicates its result to all
 107     * the components of a vec4.  We would like NIR to give us replicated fdot
 108     * instructions because it can optimize better for us.
 109     *
 110     * For the FS backend, it should be lowered away by the scalarizing pass so
 111     * we should never see fdot anyway.
 112     */
 113    nir_options->fdot_replicates = true;
 114
 115    /* We want the GLSL compiler to emit code that uses condition codes */
 116    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 117       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 118       compiler->glsl_compiler_options[i].MaxIfDepth =
 119          devinfo->gen < 6 ? 16 : UINT_MAX;
 120
 121       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 122       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 123       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 124       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 125       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 126       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 127
 128       bool is_scalar = compiler->scalar_stage[i];
 129
 130       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 131       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 132       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 133
 134       /* !ARB_gpu_shader5 */
 135       if (devinfo->gen < 7)
 136          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 137
 138       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 139
 140       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 141    }
 142
 143    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 144    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 145
 146    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 147       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 148
 149    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 150       .LowerShaderSharedVariables = true;
 151
 152    return compiler;
 153 }
 154
 155 extern "C" struct gl_shader *
 156 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 157 {
 158    struct brw_shader *shader;
 159
 160    shader = rzalloc(NULL, struct brw_shader);
 161    if (shader) {
 162       shader->base.Type = type;
 163       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 164       shader->base.Name = name;
 165       _mesa_init_shader(ctx, &shader->base);
 166    }
 167
 168    return &shader->base;
 169 }
 170
 171 extern "C" void
 172 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 173                       unsigned surf_index)
 174 {
 175    assert(surf_index < BRW_MAX_SURFACES);
 176
 177    prog_data->binding_table.size_bytes =
 178       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 179 }
 180
 181 enum brw_reg_type
 182 brw_type_for_base_type(const struct glsl_type *type)
 183 {
 184    switch (type->base_type) {
 185    case GLSL_TYPE_FLOAT:
 186       return BRW_REGISTER_TYPE_F;
 187    case GLSL_TYPE_INT:
 188    case GLSL_TYPE_BOOL:
 189    case GLSL_TYPE_SUBROUTINE:
 190       return BRW_REGISTER_TYPE_D;
 191    case GLSL_TYPE_UINT:
 192       return BRW_REGISTER_TYPE_UD;
 193    case GLSL_TYPE_ARRAY:
 194       return brw_type_for_base_type(type->fields.array);
 195    case GLSL_TYPE_STRUCT:
 196    case GLSL_TYPE_SAMPLER:
 197    case GLSL_TYPE_ATOMIC_UINT:
 198       /* These should be overridden with the type of the member when
 199        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 200        * way to trip up if we don't.
 201        */
 202       return BRW_REGISTER_TYPE_UD;
 203    case GLSL_TYPE_IMAGE:
 204       return BRW_REGISTER_TYPE_UD;
 205    case GLSL_TYPE_VOID:
 206    case GLSL_TYPE_ERROR:
 207    case GLSL_TYPE_INTERFACE:
 208    case GLSL_TYPE_DOUBLE:
 209       unreachable("not reached");
 210    }
 211
 212    return BRW_REGISTER_TYPE_F;
 213 }
 214
 215 enum brw_conditional_mod
 216 brw_conditional_for_comparison(unsigned int op)
 217 {
 218    switch (op) {
 219    case ir_binop_less:
 220       return BRW_CONDITIONAL_L;
 221    case ir_binop_greater:
 222       return BRW_CONDITIONAL_G;
 223    case ir_binop_lequal:
 224       return BRW_CONDITIONAL_LE;
 225    case ir_binop_gequal:
 226       return BRW_CONDITIONAL_GE;
 227    case ir_binop_equal:
 228    case ir_binop_all_equal: /* same as equal for scalars */
 229       return BRW_CONDITIONAL_Z;
 230    case ir_binop_nequal:
 231    case ir_binop_any_nequal: /* same as nequal for scalars */
 232       return BRW_CONDITIONAL_NZ;
 233    default:
 234       unreachable("not reached: bad operation for comparison");
 235    }
 236 }
 237
 238 uint32_t
 239 brw_math_function(enum opcode op)
 240 {
 241    switch (op) {
 242    case SHADER_OPCODE_RCP:
 243       return BRW_MATH_FUNCTION_INV;
 244    case SHADER_OPCODE_RSQ:
 245       return BRW_MATH_FUNCTION_RSQ;
 246    case SHADER_OPCODE_SQRT:
 247       return BRW_MATH_FUNCTION_SQRT;
 248    case SHADER_OPCODE_EXP2:
 249       return BRW_MATH_FUNCTION_EXP;
 250    case SHADER_OPCODE_LOG2:
 251       return BRW_MATH_FUNCTION_LOG;
 252    case SHADER_OPCODE_POW:
 253       return BRW_MATH_FUNCTION_POW;
 254    case SHADER_OPCODE_SIN:
 255       return BRW_MATH_FUNCTION_SIN;
 256    case SHADER_OPCODE_COS:
 257       return BRW_MATH_FUNCTION_COS;
 258    case SHADER_OPCODE_INT_QUOTIENT:
 259       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 260    case SHADER_OPCODE_INT_REMAINDER:
 261       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 262    default:
 263       unreachable("not reached: unknown math function");
 264    }
 265 }
 266
 267 uint32_t
 268 brw_texture_offset(int *offsets, unsigned num_components)
 269 {
 270    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 271
 272    /* Combine all three offsets into a single unsigned dword:
 273     *
 274     *    bits 11:8 - U Offset (X component)
 275     *    bits  7:4 - V Offset (Y component)
 276     *    bits  3:0 - R Offset (Z component)
 277     */
 278    unsigned offset_bits = 0;
 279    for (unsigned i = 0; i < num_components; i++) {
 280       const unsigned shift = 4 * (2 - i);
 281       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 282    }
 283    return offset_bits;
 284 }
 285
 286 const char *
 287 brw_instruction_name(enum opcode op)
 288 {
 289    switch (op) {
 290    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 291       assert(opcode_descs[op].name);
 292       return opcode_descs[op].name;
 293    case FS_OPCODE_FB_WRITE:
 294       return "fb_write";
 295    case FS_OPCODE_FB_WRITE_LOGICAL:
 296       return "fb_write_logical";
 297    case FS_OPCODE_PACK_STENCIL_REF:
 298       return "pack_stencil_ref";
 299    case FS_OPCODE_BLORP_FB_WRITE:
 300       return "blorp_fb_write";
 301    case FS_OPCODE_REP_FB_WRITE:
 302       return "rep_fb_write";
 303
 304    case SHADER_OPCODE_RCP:
 305       return "rcp";
 306    case SHADER_OPCODE_RSQ:
 307       return "rsq";
 308    case SHADER_OPCODE_SQRT:
 309       return "sqrt";
 310    case SHADER_OPCODE_EXP2:
 311       return "exp2";
 312    case SHADER_OPCODE_LOG2:
 313       return "log2";
 314    case SHADER_OPCODE_POW:
 315       return "pow";
 316    case SHADER_OPCODE_INT_QUOTIENT:
 317       return "int_quot";
 318    case SHADER_OPCODE_INT_REMAINDER:
 319       return "int_rem";
 320    case SHADER_OPCODE_SIN:
 321       return "sin";
 322    case SHADER_OPCODE_COS:
 323       return "cos";
 324
 325    case SHADER_OPCODE_TEX:
 326       return "tex";
 327    case SHADER_OPCODE_TEX_LOGICAL:
 328       return "tex_logical";
 329    case SHADER_OPCODE_TXD:
 330       return "txd";
 331    case SHADER_OPCODE_TXD_LOGICAL:
 332       return "txd_logical";
 333    case SHADER_OPCODE_TXF:
 334       return "txf";
 335    case SHADER_OPCODE_TXF_LOGICAL:
 336       return "txf_logical";
 337    case SHADER_OPCODE_TXL:
 338       return "txl";
 339    case SHADER_OPCODE_TXL_LOGICAL:
 340       return "txl_logical";
 341    case SHADER_OPCODE_TXS:
 342       return "txs";
 343    case SHADER_OPCODE_TXS_LOGICAL:
 344       return "txs_logical";
 345    case FS_OPCODE_TXB:
 346       return "txb";
 347    case FS_OPCODE_TXB_LOGICAL:
 348       return "txb_logical";
 349    case SHADER_OPCODE_TXF_CMS:
 350       return "txf_cms";
 351    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 352       return "txf_cms_logical";
 353    case SHADER_OPCODE_TXF_CMS_W:
 354       return "txf_cms_w";
 355    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 356       return "txf_cms_w_logical";
 357    case SHADER_OPCODE_TXF_UMS:
 358       return "txf_ums";
 359    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 360       return "txf_ums_logical";
 361    case SHADER_OPCODE_TXF_MCS:
 362       return "txf_mcs";
 363    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 364       return "txf_mcs_logical";
 365    case SHADER_OPCODE_LOD:
 366       return "lod";
 367    case SHADER_OPCODE_LOD_LOGICAL:
 368       return "lod_logical";
 369    case SHADER_OPCODE_TG4:
 370       return "tg4";
 371    case SHADER_OPCODE_TG4_LOGICAL:
 372       return "tg4_logical";
 373    case SHADER_OPCODE_TG4_OFFSET:
 374       return "tg4_offset";
 375    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 376       return "tg4_offset_logical";
 377    case SHADER_OPCODE_SAMPLEINFO:
 378       return "sampleinfo";
 379
 380    case SHADER_OPCODE_SHADER_TIME_ADD:
 381       return "shader_time_add";
 382
 383    case SHADER_OPCODE_UNTYPED_ATOMIC:
 384       return "untyped_atomic";
 385    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 386       return "untyped_atomic_logical";
 387    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 388       return "untyped_surface_read";
 389    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 390       return "untyped_surface_read_logical";
 391    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 392       return "untyped_surface_write";
 393    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 394       return "untyped_surface_write_logical";
 395    case SHADER_OPCODE_TYPED_ATOMIC:
 396       return "typed_atomic";
 397    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 398       return "typed_atomic_logical";
 399    case SHADER_OPCODE_TYPED_SURFACE_READ:
 400       return "typed_surface_read";
 401    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 402       return "typed_surface_read_logical";
 403    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 404       return "typed_surface_write";
 405    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 406       return "typed_surface_write_logical";
 407    case SHADER_OPCODE_MEMORY_FENCE:
 408       return "memory_fence";
 409
 410    case SHADER_OPCODE_LOAD_PAYLOAD:
 411       return "load_payload";
 412
 413    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 414       return "gen4_scratch_read";
 415    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 416       return "gen4_scratch_write";
 417    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 418       return "gen7_scratch_read";
 419    case SHADER_OPCODE_URB_WRITE_SIMD8:
 420       return "gen8_urb_write_simd8";
 421    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 422       return "gen8_urb_write_simd8_per_slot";
 423    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 424       return "gen8_urb_write_simd8_masked";
 425    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 426       return "gen8_urb_write_simd8_masked_per_slot";
 427    case SHADER_OPCODE_URB_READ_SIMD8:
 428       return "urb_read_simd8";
 429    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 430       return "urb_read_simd8_per_slot";
 431
 432    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 433       return "find_live_channel";
 434    case SHADER_OPCODE_BROADCAST:
 435       return "broadcast";
 436
 437    case VEC4_OPCODE_MOV_BYTES:
 438       return "mov_bytes";
 439    case VEC4_OPCODE_PACK_BYTES:
 440       return "pack_bytes";
 441    case VEC4_OPCODE_UNPACK_UNIFORM:
 442       return "unpack_uniform";
 443
 444    case FS_OPCODE_DDX_COARSE:
 445       return "ddx_coarse";
 446    case FS_OPCODE_DDX_FINE:
 447       return "ddx_fine";
 448    case FS_OPCODE_DDY_COARSE:
 449       return "ddy_coarse";
 450    case FS_OPCODE_DDY_FINE:
 451       return "ddy_fine";
 452
 453    case FS_OPCODE_CINTERP:
 454       return "cinterp";
 455    case FS_OPCODE_LINTERP:
 456       return "linterp";
 457
 458    case FS_OPCODE_PIXEL_X:
 459       return "pixel_x";
 460    case FS_OPCODE_PIXEL_Y:
 461       return "pixel_y";
 462
 463    case FS_OPCODE_GET_BUFFER_SIZE:
 464       return "fs_get_buffer_size";
 465
 466    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 467       return "uniform_pull_const";
 468    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 469       return "uniform_pull_const_gen7";
 470    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 471       return "varying_pull_const";
 472    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 473       return "varying_pull_const_gen7";
 474
 475    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 476       return "mov_dispatch_to_flags";
 477    case FS_OPCODE_DISCARD_JUMP:
 478       return "discard_jump";
 479
 480    case FS_OPCODE_SET_SAMPLE_ID:
 481       return "set_sample_id";
 482    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 483       return "set_simd4x2_offset";
 484
 485    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 486       return "pack_half_2x16_split";
 487    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 488       return "unpack_half_2x16_split_x";
 489    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 490       return "unpack_half_2x16_split_y";
 491
 492    case FS_OPCODE_PLACEHOLDER_HALT:
 493       return "placeholder_halt";
 494
 495    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 496       return "interp_centroid";
 497    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 498       return "interp_sample";
 499    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 500       return "interp_shared_offset";
 501    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 502       return "interp_per_slot_offset";
 503
 504    case VS_OPCODE_URB_WRITE:
 505       return "vs_urb_write";
 506    case VS_OPCODE_PULL_CONSTANT_LOAD:
 507       return "pull_constant_load";
 508    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 509       return "pull_constant_load_gen7";
 510
 511    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 512       return "set_simd4x2_header_gen9";
 513
 514    case VS_OPCODE_GET_BUFFER_SIZE:
 515       return "vs_get_buffer_size";
 516
 517    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 518       return "unpack_flags_simd4x2";
 519
 520    case GS_OPCODE_URB_WRITE:
 521       return "gs_urb_write";
 522    case GS_OPCODE_URB_WRITE_ALLOCATE:
 523       return "gs_urb_write_allocate";
 524    case GS_OPCODE_THREAD_END:
 525       return "gs_thread_end";
 526    case GS_OPCODE_SET_WRITE_OFFSET:
 527       return "set_write_offset";
 528    case GS_OPCODE_SET_VERTEX_COUNT:
 529       return "set_vertex_count";
 530    case GS_OPCODE_SET_DWORD_2:
 531       return "set_dword_2";
 532    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 533       return "prepare_channel_masks";
 534    case GS_OPCODE_SET_CHANNEL_MASKS:
 535       return "set_channel_masks";
 536    case GS_OPCODE_GET_INSTANCE_ID:
 537       return "get_instance_id";
 538    case GS_OPCODE_FF_SYNC:
 539       return "ff_sync";
 540    case GS_OPCODE_SET_PRIMITIVE_ID:
 541       return "set_primitive_id";
 542    case GS_OPCODE_SVB_WRITE:
 543       return "gs_svb_write";
 544    case GS_OPCODE_SVB_SET_DST_INDEX:
 545       return "gs_svb_set_dst_index";
 546    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 547       return "gs_ff_sync_set_primitives";
 548    case CS_OPCODE_CS_TERMINATE:
 549       return "cs_terminate";
 550    case SHADER_OPCODE_BARRIER:
 551       return "barrier";
 552    case SHADER_OPCODE_MULH:
 553       return "mulh";
 554    case SHADER_OPCODE_MOV_INDIRECT:
 555       return "mov_indirect";
 556
 557    case VEC4_OPCODE_URB_READ:
 558       return "urb_read";
 559    case TCS_OPCODE_GET_INSTANCE_ID:
 560       return "tcs_get_instance_id";
 561    case TCS_OPCODE_URB_WRITE:
 562       return "tcs_urb_write";
 563    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 564       return "tcs_set_input_urb_offsets";
 565    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 566       return "tcs_set_output_urb_offsets";
 567    case TCS_OPCODE_GET_PRIMITIVE_ID:
 568       return "tcs_get_primitive_id";
 569    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 570       return "tcs_create_barrier_header";
 571    case TCS_OPCODE_SRC0_010_IS_ZERO:
 572       return "tcs_src0<0,1,0>_is_zero";
 573    case TCS_OPCODE_RELEASE_INPUT:
 574       return "tcs_release_input";
 575    case TCS_OPCODE_THREAD_END:
 576       return "tcs_thread_end";
 577    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 578       return "tes_create_input_read_header";
 579    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 580       return "tes_add_indirect_urb_offset";
 581    case TES_OPCODE_GET_PRIMITIVE_ID:
 582       return "tes_get_primitive_id";
 583    }
 584
 585    unreachable("not reached");
 586 }
 587
 588 bool
 589 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 590 {
 591    union {
 592       unsigned ud;
 593       int d;
 594       float f;
 595    } imm = { reg->ud }, sat_imm = { 0 };
 596
 597    switch (type) {
 598    case BRW_REGISTER_TYPE_UD:
 599    case BRW_REGISTER_TYPE_D:
 600    case BRW_REGISTER_TYPE_UW:
 601    case BRW_REGISTER_TYPE_W:
 602    case BRW_REGISTER_TYPE_UQ:
 603    case BRW_REGISTER_TYPE_Q:
 604       /* Nothing to do. */
 605       return false;
 606    case BRW_REGISTER_TYPE_F:
 607       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 608       break;
 609    case BRW_REGISTER_TYPE_UB:
 610    case BRW_REGISTER_TYPE_B:
 611       unreachable("no UB/B immediates");
 612    case BRW_REGISTER_TYPE_V:
 613    case BRW_REGISTER_TYPE_UV:
 614    case BRW_REGISTER_TYPE_VF:
 615       unreachable("unimplemented: saturate vector immediate");
 616    case BRW_REGISTER_TYPE_DF:
 617    case BRW_REGISTER_TYPE_HF:
 618       unreachable("unimplemented: saturate DF/HF immediate");
 619    }
 620
 621    if (imm.ud != sat_imm.ud) {
 622       reg->ud = sat_imm.ud;
 623       return true;
 624    }
 625    return false;
 626 }
 627
 628 bool
 629 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 630 {
 631    switch (type) {
 632    case BRW_REGISTER_TYPE_D:
 633    case BRW_REGISTER_TYPE_UD:
 634       reg->d = -reg->d;
 635       return true;
 636    case BRW_REGISTER_TYPE_W:
 637    case BRW_REGISTER_TYPE_UW:
 638       reg->d = -(int16_t)reg->ud;
 639       return true;
 640    case BRW_REGISTER_TYPE_F:
 641       reg->f = -reg->f;
 642       return true;
 643    case BRW_REGISTER_TYPE_VF:
 644       reg->ud ^= 0x80808080;
 645       return true;
 646    case BRW_REGISTER_TYPE_UB:
 647    case BRW_REGISTER_TYPE_B:
 648       unreachable("no UB/B immediates");
 649    case BRW_REGISTER_TYPE_UV:
 650    case BRW_REGISTER_TYPE_V:
 651       assert(!"unimplemented: negate UV/V immediate");
 652    case BRW_REGISTER_TYPE_UQ:
 653    case BRW_REGISTER_TYPE_Q:
 654       assert(!"unimplemented: negate UQ/Q immediate");
 655    case BRW_REGISTER_TYPE_DF:
 656    case BRW_REGISTER_TYPE_HF:
 657       assert(!"unimplemented: negate DF/HF immediate");
 658    }
 659
 660    return false;
 661 }
 662
 663 bool
 664 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 665 {
 666    switch (type) {
 667    case BRW_REGISTER_TYPE_D:
 668       reg->d = abs(reg->d);
 669       return true;
 670    case BRW_REGISTER_TYPE_W:
 671       reg->d = abs((int16_t)reg->ud);
 672       return true;
 673    case BRW_REGISTER_TYPE_F:
 674       reg->f = fabsf(reg->f);
 675       return true;
 676    case BRW_REGISTER_TYPE_VF:
 677       reg->ud &= ~0x80808080;
 678       return true;
 679    case BRW_REGISTER_TYPE_UB:
 680    case BRW_REGISTER_TYPE_B:
 681       unreachable("no UB/B immediates");
 682    case BRW_REGISTER_TYPE_UQ:
 683    case BRW_REGISTER_TYPE_UD:
 684    case BRW_REGISTER_TYPE_UW:
 685    case BRW_REGISTER_TYPE_UV:
 686       /* Presumably the absolute value modifier on an unsigned source is a
 687        * nop, but it would be nice to confirm.
 688        */
 689       assert(!"unimplemented: abs unsigned immediate");
 690    case BRW_REGISTER_TYPE_V:
 691       assert(!"unimplemented: abs V immediate");
 692    case BRW_REGISTER_TYPE_Q:
 693       assert(!"unimplemented: abs Q immediate");
 694    case BRW_REGISTER_TYPE_DF:
 695    case BRW_REGISTER_TYPE_HF:
 696       assert(!"unimplemented: abs DF/HF immediate");
 697    }
 698
 699    return false;
 700 }
 701
 702 backend_shader::backend_shader(const struct brw_compiler *compiler,
 703                                void *log_data,
 704                                void *mem_ctx,
 705                                const nir_shader *shader,
 706                                struct brw_stage_prog_data *stage_prog_data)
 707    : compiler(compiler),
 708      log_data(log_data),
 709      devinfo(compiler->devinfo),
 710      nir(shader),
 711      stage_prog_data(stage_prog_data),
 712      mem_ctx(mem_ctx),
 713      cfg(NULL),
 714      stage(shader->stage)
 715 {
 716    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 717    stage_name = _mesa_shader_stage_to_string(stage);
 718    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 719 }
 720
 721 bool
 722 backend_reg::equals(const backend_reg &r) const
 723 {
 724    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 725           reg_offset == r.reg_offset;
 726 }
 727
 728 bool
 729 backend_reg::is_zero() const
 730 {
 731    if (file != IMM)
 732       return false;
 733
 734    return d == 0;
 735 }
 736
 737 bool
 738 backend_reg::is_one() const
 739 {
 740    if (file != IMM)
 741       return false;
 742
 743    return type == BRW_REGISTER_TYPE_F
 744           ? f == 1.0
 745           : d == 1;
 746 }
 747
 748 bool
 749 backend_reg::is_negative_one() const
 750 {
 751    if (file != IMM)
 752       return false;
 753
 754    switch (type) {
 755    case BRW_REGISTER_TYPE_F:
 756       return f == -1.0;
 757    case BRW_REGISTER_TYPE_D:
 758       return d == -1;
 759    default:
 760       return false;
 761    }
 762 }
 763
 764 bool
 765 backend_reg::is_null() const
 766 {
 767    return file == ARF && nr == BRW_ARF_NULL;
 768 }
 769
 770
 771 bool
 772 backend_reg::is_accumulator() const
 773 {
 774    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 775 }
 776
 777 bool
 778 backend_reg::in_range(const backend_reg &r, unsigned n) const
 779 {
 780    return (file == r.file &&
 781            nr == r.nr &&
 782            reg_offset >= r.reg_offset &&
 783            reg_offset < r.reg_offset + n);
 784 }
 785
 786 bool
 787 backend_instruction::is_commutative() const
 788 {
 789    switch (opcode) {
 790    case BRW_OPCODE_AND:
 791    case BRW_OPCODE_OR:
 792    case BRW_OPCODE_XOR:
 793    case BRW_OPCODE_ADD:
 794    case BRW_OPCODE_MUL:
 795    case SHADER_OPCODE_MULH:
 796       return true;
 797    case BRW_OPCODE_SEL:
 798       /* MIN and MAX are commutative. */
 799       if (conditional_mod == BRW_CONDITIONAL_GE ||
 800           conditional_mod == BRW_CONDITIONAL_L) {
 801          return true;
 802       }
 803       /* fallthrough */
 804    default:
 805       return false;
 806    }
 807 }
 808
 809 bool
 810 backend_instruction::is_3src() const
 811 {
 812    return ::is_3src(opcode);
 813 }
 814
 815 bool
 816 backend_instruction::is_tex() const
 817 {
 818    return (opcode == SHADER_OPCODE_TEX ||
 819            opcode == FS_OPCODE_TXB ||
 820            opcode == SHADER_OPCODE_TXD ||
 821            opcode == SHADER_OPCODE_TXF ||
 822            opcode == SHADER_OPCODE_TXF_CMS ||
 823            opcode == SHADER_OPCODE_TXF_CMS_W ||
 824            opcode == SHADER_OPCODE_TXF_UMS ||
 825            opcode == SHADER_OPCODE_TXF_MCS ||
 826            opcode == SHADER_OPCODE_TXL ||
 827            opcode == SHADER_OPCODE_TXS ||
 828            opcode == SHADER_OPCODE_LOD ||
 829            opcode == SHADER_OPCODE_TG4 ||
 830            opcode == SHADER_OPCODE_TG4_OFFSET);
 831 }
 832
 833 bool
 834 backend_instruction::is_math() const
 835 {
 836    return (opcode == SHADER_OPCODE_RCP ||
 837            opcode == SHADER_OPCODE_RSQ ||
 838            opcode == SHADER_OPCODE_SQRT ||
 839            opcode == SHADER_OPCODE_EXP2 ||
 840            opcode == SHADER_OPCODE_LOG2 ||
 841            opcode == SHADER_OPCODE_SIN ||
 842            opcode == SHADER_OPCODE_COS ||
 843            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 844            opcode == SHADER_OPCODE_INT_REMAINDER ||
 845            opcode == SHADER_OPCODE_POW);
 846 }
 847
 848 bool
 849 backend_instruction::is_control_flow() const
 850 {
 851    switch (opcode) {
 852    case BRW_OPCODE_DO:
 853    case BRW_OPCODE_WHILE:
 854    case BRW_OPCODE_IF:
 855    case BRW_OPCODE_ELSE:
 856    case BRW_OPCODE_ENDIF:
 857    case BRW_OPCODE_BREAK:
 858    case BRW_OPCODE_CONTINUE:
 859       return true;
 860    default:
 861       return false;
 862    }
 863 }
 864
 865 bool
 866 backend_instruction::can_do_source_mods() const
 867 {
 868    switch (opcode) {
 869    case BRW_OPCODE_ADDC:
 870    case BRW_OPCODE_BFE:
 871    case BRW_OPCODE_BFI1:
 872    case BRW_OPCODE_BFI2:
 873    case BRW_OPCODE_BFREV:
 874    case BRW_OPCODE_CBIT:
 875    case BRW_OPCODE_FBH:
 876    case BRW_OPCODE_FBL:
 877    case BRW_OPCODE_SUBB:
 878       return false;
 879    default:
 880       return true;
 881    }
 882 }
 883
 884 bool
 885 backend_instruction::can_do_saturate() const
 886 {
 887    switch (opcode) {
 888    case BRW_OPCODE_ADD:
 889    case BRW_OPCODE_ASR:
 890    case BRW_OPCODE_AVG:
 891    case BRW_OPCODE_DP2:
 892    case BRW_OPCODE_DP3:
 893    case BRW_OPCODE_DP4:
 894    case BRW_OPCODE_DPH:
 895    case BRW_OPCODE_F16TO32:
 896    case BRW_OPCODE_F32TO16:
 897    case BRW_OPCODE_LINE:
 898    case BRW_OPCODE_LRP:
 899    case BRW_OPCODE_MAC:
 900    case BRW_OPCODE_MAD:
 901    case BRW_OPCODE_MATH:
 902    case BRW_OPCODE_MOV:
 903    case BRW_OPCODE_MUL:
 904    case SHADER_OPCODE_MULH:
 905    case BRW_OPCODE_PLN:
 906    case BRW_OPCODE_RNDD:
 907    case BRW_OPCODE_RNDE:
 908    case BRW_OPCODE_RNDU:
 909    case BRW_OPCODE_RNDZ:
 910    case BRW_OPCODE_SEL:
 911    case BRW_OPCODE_SHL:
 912    case BRW_OPCODE_SHR:
 913    case FS_OPCODE_LINTERP:
 914    case SHADER_OPCODE_COS:
 915    case SHADER_OPCODE_EXP2:
 916    case SHADER_OPCODE_LOG2:
 917    case SHADER_OPCODE_POW:
 918    case SHADER_OPCODE_RCP:
 919    case SHADER_OPCODE_RSQ:
 920    case SHADER_OPCODE_SIN:
 921    case SHADER_OPCODE_SQRT:
 922       return true;
 923    default:
 924       return false;
 925    }
 926 }
 927
 928 bool
 929 backend_instruction::can_do_cmod() const
 930 {
 931    switch (opcode) {
 932    case BRW_OPCODE_ADD:
 933    case BRW_OPCODE_ADDC:
 934    case BRW_OPCODE_AND:
 935    case BRW_OPCODE_ASR:
 936    case BRW_OPCODE_AVG:
 937    case BRW_OPCODE_CMP:
 938    case BRW_OPCODE_CMPN:
 939    case BRW_OPCODE_DP2:
 940    case BRW_OPCODE_DP3:
 941    case BRW_OPCODE_DP4:
 942    case BRW_OPCODE_DPH:
 943    case BRW_OPCODE_F16TO32:
 944    case BRW_OPCODE_F32TO16:
 945    case BRW_OPCODE_FRC:
 946    case BRW_OPCODE_LINE:
 947    case BRW_OPCODE_LRP:
 948    case BRW_OPCODE_LZD:
 949    case BRW_OPCODE_MAC:
 950    case BRW_OPCODE_MACH:
 951    case BRW_OPCODE_MAD:
 952    case BRW_OPCODE_MOV:
 953    case BRW_OPCODE_MUL:
 954    case BRW_OPCODE_NOT:
 955    case BRW_OPCODE_OR:
 956    case BRW_OPCODE_PLN:
 957    case BRW_OPCODE_RNDD:
 958    case BRW_OPCODE_RNDE:
 959    case BRW_OPCODE_RNDU:
 960    case BRW_OPCODE_RNDZ:
 961    case BRW_OPCODE_SAD2:
 962    case BRW_OPCODE_SADA2:
 963    case BRW_OPCODE_SHL:
 964    case BRW_OPCODE_SHR:
 965    case BRW_OPCODE_SUBB:
 966    case BRW_OPCODE_XOR:
 967    case FS_OPCODE_CINTERP:
 968    case FS_OPCODE_LINTERP:
 969       return true;
 970    default:
 971       return false;
 972    }
 973 }
 974
 975 bool
 976 backend_instruction::reads_accumulator_implicitly() const
 977 {
 978    switch (opcode) {
 979    case BRW_OPCODE_MAC:
 980    case BRW_OPCODE_MACH:
 981    case BRW_OPCODE_SADA2:
 982       return true;
 983    default:
 984       return false;
 985    }
 986 }
 987
 988 bool
 989 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 990 {
 991    return writes_accumulator ||
 992           (devinfo->gen < 6 &&
 993            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 994             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 995              opcode != FS_OPCODE_CINTERP)));
 996 }
 997
 998 bool
 999 backend_instruction::has_side_effects() const
1000 {
1001    switch (opcode) {
1002    case SHADER_OPCODE_UNTYPED_ATOMIC:
1003    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1004    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1005    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1006    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1007    case SHADER_OPCODE_TYPED_ATOMIC:
1008    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1009    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1010    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1011    case SHADER_OPCODE_MEMORY_FENCE:
1012    case SHADER_OPCODE_URB_WRITE_SIMD8:
1013    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1014    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1015    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1016    case FS_OPCODE_FB_WRITE:
1017    case SHADER_OPCODE_BARRIER:
1018    case TCS_OPCODE_RELEASE_INPUT:
1019       return true;
1020    default:
1021       return false;
1022    }
1023 }
1024
1025 bool
1026 backend_instruction::is_volatile() const
1027 {
1028    switch (opcode) {
1029    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1030    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1031    case SHADER_OPCODE_TYPED_SURFACE_READ:
1032    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1033       return true;
1034    default:
1035       return false;
1036    }
1037 }
1038
1039 #ifndef NDEBUG
1040 static bool
1041 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1042 {
1043    bool found = false;
1044    foreach_inst_in_block (backend_instruction, i, block) {
1045       if (inst == i) {
1046          found = true;
1047       }
1048    }
1049    return found;
1050 }
1051 #endif
1052
1053 static void
1054 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1055 {
1056    for (bblock_t *block_iter = start_block->next();
1057         !block_iter->link.is_tail_sentinel();
1058         block_iter = block_iter->next()) {
1059       block_iter->start_ip += ip_adjustment;
1060       block_iter->end_ip += ip_adjustment;
1061    }
1062 }
1063
1064 void
1065 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1066 {
1067    if (!this->is_head_sentinel())
1068       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1069
1070    block->end_ip++;
1071
1072    adjust_later_block_ips(block, 1);
1073
1074    exec_node::insert_after(inst);
1075 }
1076
1077 void
1078 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1079 {
1080    if (!this->is_tail_sentinel())
1081       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1082
1083    block->end_ip++;
1084
1085    adjust_later_block_ips(block, 1);
1086
1087    exec_node::insert_before(inst);
1088 }
1089
1090 void
1091 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1092 {
1093    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1094
1095    unsigned num_inst = list->length();
1096
1097    block->end_ip += num_inst;
1098
1099    adjust_later_block_ips(block, num_inst);
1100
1101    exec_node::insert_before(list);
1102 }
1103
1104 void
1105 backend_instruction::remove(bblock_t *block)
1106 {
1107    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1108
1109    adjust_later_block_ips(block, -1);
1110
1111    if (block->start_ip == block->end_ip) {
1112       block->cfg->remove_block(block);
1113    } else {
1114       block->end_ip--;
1115    }
1116
1117    exec_node::remove();
1118 }
1119
1120 void
1121 backend_shader::dump_instructions()
1122 {
1123    dump_instructions(NULL);
1124 }
1125
1126 void
1127 backend_shader::dump_instructions(const char *name)
1128 {
1129    FILE *file = stderr;
1130    if (name && geteuid() != 0) {
1131       file = fopen(name, "w");
1132       if (!file)
1133          file = stderr;
1134    }
1135
1136    if (cfg) {
1137       int ip = 0;
1138       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1139          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1140             fprintf(file, "%4d: ", ip++);
1141          dump_instruction(inst, file);
1142       }
1143    } else {
1144       int ip = 0;
1145       foreach_in_list(backend_instruction, inst, &instructions) {
1146          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1147             fprintf(file, "%4d: ", ip++);
1148          dump_instruction(inst, file);
1149       }
1150    }
1151
1152    if (file != stderr) {
1153       fclose(file);
1154    }
1155 }
1156
1157 void
1158 backend_shader::calculate_cfg()
1159 {
1160    if (this->cfg)
1161       return;
1162    cfg = new(mem_ctx) cfg_t(&this->instructions);
1163 }
1164
1165 void
1166 backend_shader::invalidate_cfg()
1167 {
1168    ralloc_free(this->cfg);
1169    this->cfg = NULL;
1170 }
1171
1172 /**
1173  * Sets up the starting offsets for the groups of binding table entries
1174  * commong to all pipeline stages.
1175  *
1176  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1177  * unused but also make sure that addition of small offsets to them will
1178  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1179  */
1180 void
1181 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1182                                         const struct brw_device_info *devinfo,
1183                                         const struct gl_shader_program *shader_prog,
1184                                         const struct gl_program *prog,
1185                                         struct brw_stage_prog_data *stage_prog_data,
1186                                         uint32_t next_binding_table_offset)
1187 {
1188    const struct gl_shader *shader = NULL;
1189    int num_textures = _mesa_fls(prog->SamplersUsed);
1190
1191    if (shader_prog)
1192       shader = shader_prog->_LinkedShaders[stage];
1193
1194    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1195    next_binding_table_offset += num_textures;
1196
1197    if (shader) {
1198       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1199       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1200       next_binding_table_offset += shader->NumUniformBlocks;
1201
1202       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1203       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1204       next_binding_table_offset += shader->NumShaderStorageBlocks;
1205    } else {
1206       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1207       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1208    }
1209
1210    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1211       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1212       next_binding_table_offset++;
1213    } else {
1214       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1215    }
1216
1217    if (prog->UsesGather) {
1218       if (devinfo->gen >= 8) {
1219          stage_prog_data->binding_table.gather_texture_start =
1220             stage_prog_data->binding_table.texture_start;
1221       } else {
1222          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1223          next_binding_table_offset += num_textures;
1224       }
1225    } else {
1226       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1227    }
1228
1229    if (shader && shader->NumAtomicBuffers) {
1230       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1231       next_binding_table_offset += shader->NumAtomicBuffers;
1232    } else {
1233       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1234    }
1235
1236    if (shader && shader->NumImages) {
1237       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1238       next_binding_table_offset += shader->NumImages;
1239    } else {
1240       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1241    }
1242
1243    /* This may or may not be used depending on how the compile goes. */
1244    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1245    next_binding_table_offset++;
1246
1247    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1248
1249    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1250 }
1251
1252 static void
1253 setup_vec4_uniform_value(const gl_constant_value **params,
1254                          const gl_constant_value *values,
1255                          unsigned n)
1256 {
1257    static const gl_constant_value zero = { 0 };
1258
1259    for (unsigned i = 0; i < n; ++i)
1260       params[i] = &values[i];
1261
1262    for (unsigned i = n; i < 4; ++i)
1263       params[i] = &zero;
1264 }
1265
1266 void
1267 brw_setup_image_uniform_values(gl_shader_stage stage,
1268                                struct brw_stage_prog_data *stage_prog_data,
1269                                unsigned param_start_index,
1270                                const gl_uniform_storage *storage)
1271 {
1272    const gl_constant_value **param =
1273       &stage_prog_data->param[param_start_index];
1274
1275    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1276       const unsigned image_idx = storage->opaque[stage].index + i;
1277       const brw_image_param *image_param =
1278          &stage_prog_data->image_param[image_idx];
1279
1280       /* Upload the brw_image_param structure.  The order is expected to match
1281        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1282        */
1283       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1284          (const gl_constant_value *)&image_param->surface_idx, 1);
1285       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1286          (const gl_constant_value *)image_param->offset, 2);
1287       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1288          (const gl_constant_value *)image_param->size, 3);
1289       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1290          (const gl_constant_value *)image_param->stride, 4);
1291       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1292          (const gl_constant_value *)image_param->tiling, 3);
1293       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1294          (const gl_constant_value *)image_param->swizzling, 2);
1295       param += BRW_IMAGE_PARAM_SIZE;
1296
1297       brw_mark_surface_used(
1298          stage_prog_data,
1299          stage_prog_data->binding_table.image_start + image_idx);
1300    }
1301 }
1302
1303 /**
1304  * Decide which set of clip planes should be used when clipping via
1305  * gl_Position or gl_ClipVertex.
1306  */
1307 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1308 {
1309    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1310       /* There is currently a GLSL vertex shader, so clip according to GLSL
1311        * rules, which means compare gl_ClipVertex (or gl_Position, if
1312        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1313        * that were stored in EyeUserPlane at the time the clip planes were
1314        * specified.
1315        */
1316       return ctx->Transform.EyeUserPlane;
1317    } else {
1318       /* Either we are using fixed function or an ARB vertex program.  In
1319        * either case the clip planes are going to be compared against
1320        * gl_Position (which is in clip coordinates) so we have to clip using
1321        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1322        * core.
1323        */
1324       return ctx->Transform._ClipUserPlane;
1325    }
1326 }
1327
1328 extern "C" const unsigned *
1329 brw_compile_tes(const struct brw_compiler *compiler,
1330                 void *log_data,
1331                 void *mem_ctx,
1332                 const struct brw_tes_prog_key *key,
1333                 struct brw_tes_prog_data *prog_data,
1334                 const nir_shader *src_shader,
1335                 struct gl_shader_program *shader_prog,
1336                 int shader_time_index,
1337                 unsigned *final_assembly_size,
1338                 char **error_str)
1339 {
1340    const struct brw_device_info *devinfo = compiler->devinfo;
1341    struct gl_shader *shader =
1342       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1343    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1344
1345    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1346    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1347    nir->info.inputs_read = key->inputs_read;
1348    nir->info.patch_inputs_read = key->patch_inputs_read;
1349    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
1350    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1351
1352    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1353                        nir->info.outputs_written,
1354                        nir->info.separate_shader);
1355
1356    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1357
1358    assert(output_size_bytes >= 1);
1359    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1360       if (error_str)
1361          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1362       return NULL;
1363    }
1364
1365    /* URB entry sizes are stored as a multiple of 64 bytes. */
1366    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1367
1368    struct brw_vue_map input_vue_map;
1369    brw_compute_tess_vue_map(&input_vue_map,
1370                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1371                             nir->info.patch_inputs_read);
1372
1373    bool need_patch_header = nir->info.system_values_read &
1374       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1375        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1376
1377    /* The TES will pull most inputs using URB read messages.
1378     *
1379     * However, we push the patch header for TessLevel factors when required,
1380     * as it's a tiny amount of extra data.
1381     */
1382    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1383
1384    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1385       fprintf(stderr, "TES Input ");
1386       brw_print_vue_map(stderr, &input_vue_map);
1387       fprintf(stderr, "TES Output ");
1388       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1389    }
1390
1391    if (is_scalar) {
1392       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1393                    &prog_data->base.base, shader->Program, nir, 8,
1394                    shader_time_index, &input_vue_map);
1395       if (!v.run_tes()) {
1396          if (error_str)
1397             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1398          return NULL;
1399       }
1400
1401       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1402
1403       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1404                      &prog_data->base.base, v.promoted_constants, false,
1405                      "TES");
1406       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1407          g.enable_debug(ralloc_asprintf(mem_ctx,
1408                                         "%s tessellation evaluation shader %s",
1409                                         nir->info.label ? nir->info.label
1410                                                         : "unnamed",
1411                                         nir->info.name));
1412       }
1413
1414       g.generate_code(v.cfg, 8);
1415
1416       return g.get_assembly(final_assembly_size);
1417    } else {
1418       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1419                               nir, mem_ctx, shader_time_index);
1420       if (!v.run()) {
1421          if (error_str)
1422             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1423          return NULL;
1424       }
1425
1426       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1427          v.dump_instructions();
1428
1429       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1430                                         &prog_data->base, v.cfg,
1431                                         final_assembly_size);
1432    }
1433 }