src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 bool
  76 is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
  77 {
  78    switch (stage) {
  79    case MESA_SHADER_FRAGMENT:
  80    case MESA_SHADER_COMPUTE:
  81       return true;
  82    case MESA_SHADER_VERTEX:
  83       return compiler->scalar_vs;
  84    default:
  85       return false;
  86    }
  87 }
  88
  89 struct brw_compiler *
  90 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  91 {
  92    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  93
  94    compiler->devinfo = devinfo;
  95    compiler->shader_debug_log = shader_debug_log_mesa;
  96    compiler->shader_perf_log = shader_perf_log_mesa;
  97
  98    brw_fs_alloc_reg_sets(compiler);
  99    brw_vec4_alloc_reg_set(compiler);
 100
 101    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
 102       compiler->scalar_vs = true;
 103
 104    nir_shader_compiler_options *nir_options =
 105       rzalloc(compiler, nir_shader_compiler_options);
 106    nir_options->native_integers = true;
 107    /* In order to help allow for better CSE at the NIR level we tell NIR
 108     * to split all ffma instructions during opt_algebraic and we then
 109     * re-combine them as a later step.
 110     */
 111    nir_options->lower_ffma = true;
 112    nir_options->lower_sub = true;
 113    /* In the vec4 backend, our dpN instruction replicates its result to all
 114     * the components of a vec4.  We would like NIR to give us replicated fdot
 115     * instructions because it can optimize better for us.
 116     *
 117     * For the FS backend, it should be lowered away by the scalarizing pass so
 118     * we should never see fdot anyway.
 119     */
 120    nir_options->fdot_replicates = true;
 121
 122    /* We want the GLSL compiler to emit code that uses condition codes */
 123    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 124       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 125       compiler->glsl_compiler_options[i].MaxIfDepth =
 126          devinfo->gen < 6 ? 16 : UINT_MAX;
 127
 128       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 129       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 130       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 131       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 132       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 133       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 134
 135       bool is_scalar = is_scalar_shader_stage(compiler, i);
 136
 137       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 138       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 139       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 140
 141       /* !ARB_gpu_shader5 */
 142       if (devinfo->gen < 7)
 143          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 144
 145       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 146    }
 147
 148    return compiler;
 149 }
 150
 151 struct gl_shader *
 152 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 153 {
 154    struct brw_shader *shader;
 155
 156    shader = rzalloc(NULL, struct brw_shader);
 157    if (shader) {
 158       shader->base.Type = type;
 159       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 160       shader->base.Name = name;
 161       _mesa_init_shader(ctx, &shader->base);
 162    }
 163
 164    return &shader->base;
 165 }
 166
 167 void
 168 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 169                       unsigned surf_index)
 170 {
 171    assert(surf_index < BRW_MAX_SURFACES);
 172
 173    prog_data->binding_table.size_bytes =
 174       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 175 }
 176
 177 enum brw_reg_type
 178 brw_type_for_base_type(const struct glsl_type *type)
 179 {
 180    switch (type->base_type) {
 181    case GLSL_TYPE_FLOAT:
 182       return BRW_REGISTER_TYPE_F;
 183    case GLSL_TYPE_INT:
 184    case GLSL_TYPE_BOOL:
 185    case GLSL_TYPE_SUBROUTINE:
 186       return BRW_REGISTER_TYPE_D;
 187    case GLSL_TYPE_UINT:
 188       return BRW_REGISTER_TYPE_UD;
 189    case GLSL_TYPE_ARRAY:
 190       return brw_type_for_base_type(type->fields.array);
 191    case GLSL_TYPE_STRUCT:
 192    case GLSL_TYPE_SAMPLER:
 193    case GLSL_TYPE_ATOMIC_UINT:
 194       /* These should be overridden with the type of the member when
 195        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 196        * way to trip up if we don't.
 197        */
 198       return BRW_REGISTER_TYPE_UD;
 199    case GLSL_TYPE_IMAGE:
 200       return BRW_REGISTER_TYPE_UD;
 201    case GLSL_TYPE_VOID:
 202    case GLSL_TYPE_ERROR:
 203    case GLSL_TYPE_INTERFACE:
 204    case GLSL_TYPE_DOUBLE:
 205       unreachable("not reached");
 206    }
 207
 208    return BRW_REGISTER_TYPE_F;
 209 }
 210
 211 enum brw_conditional_mod
 212 brw_conditional_for_comparison(unsigned int op)
 213 {
 214    switch (op) {
 215    case ir_binop_less:
 216       return BRW_CONDITIONAL_L;
 217    case ir_binop_greater:
 218       return BRW_CONDITIONAL_G;
 219    case ir_binop_lequal:
 220       return BRW_CONDITIONAL_LE;
 221    case ir_binop_gequal:
 222       return BRW_CONDITIONAL_GE;
 223    case ir_binop_equal:
 224    case ir_binop_all_equal: /* same as equal for scalars */
 225       return BRW_CONDITIONAL_Z;
 226    case ir_binop_nequal:
 227    case ir_binop_any_nequal: /* same as nequal for scalars */
 228       return BRW_CONDITIONAL_NZ;
 229    default:
 230       unreachable("not reached: bad operation for comparison");
 231    }
 232 }
 233
 234 uint32_t
 235 brw_math_function(enum opcode op)
 236 {
 237    switch (op) {
 238    case SHADER_OPCODE_RCP:
 239       return BRW_MATH_FUNCTION_INV;
 240    case SHADER_OPCODE_RSQ:
 241       return BRW_MATH_FUNCTION_RSQ;
 242    case SHADER_OPCODE_SQRT:
 243       return BRW_MATH_FUNCTION_SQRT;
 244    case SHADER_OPCODE_EXP2:
 245       return BRW_MATH_FUNCTION_EXP;
 246    case SHADER_OPCODE_LOG2:
 247       return BRW_MATH_FUNCTION_LOG;
 248    case SHADER_OPCODE_POW:
 249       return BRW_MATH_FUNCTION_POW;
 250    case SHADER_OPCODE_SIN:
 251       return BRW_MATH_FUNCTION_SIN;
 252    case SHADER_OPCODE_COS:
 253       return BRW_MATH_FUNCTION_COS;
 254    case SHADER_OPCODE_INT_QUOTIENT:
 255       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 256    case SHADER_OPCODE_INT_REMAINDER:
 257       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 258    default:
 259       unreachable("not reached: unknown math function");
 260    }
 261 }
 262
 263 uint32_t
 264 brw_texture_offset(int *offsets, unsigned num_components)
 265 {
 266    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 267
 268    /* Combine all three offsets into a single unsigned dword:
 269     *
 270     *    bits 11:8 - U Offset (X component)
 271     *    bits  7:4 - V Offset (Y component)
 272     *    bits  3:0 - R Offset (Z component)
 273     */
 274    unsigned offset_bits = 0;
 275    for (unsigned i = 0; i < num_components; i++) {
 276       const unsigned shift = 4 * (2 - i);
 277       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 278    }
 279    return offset_bits;
 280 }
 281
 282 const char *
 283 brw_instruction_name(enum opcode op)
 284 {
 285    switch (op) {
 286    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 287       assert(opcode_descs[op].name);
 288       return opcode_descs[op].name;
 289    case FS_OPCODE_FB_WRITE:
 290       return "fb_write";
 291    case FS_OPCODE_FB_WRITE_LOGICAL:
 292       return "fb_write_logical";
 293    case FS_OPCODE_BLORP_FB_WRITE:
 294       return "blorp_fb_write";
 295    case FS_OPCODE_REP_FB_WRITE:
 296       return "rep_fb_write";
 297
 298    case SHADER_OPCODE_RCP:
 299       return "rcp";
 300    case SHADER_OPCODE_RSQ:
 301       return "rsq";
 302    case SHADER_OPCODE_SQRT:
 303       return "sqrt";
 304    case SHADER_OPCODE_EXP2:
 305       return "exp2";
 306    case SHADER_OPCODE_LOG2:
 307       return "log2";
 308    case SHADER_OPCODE_POW:
 309       return "pow";
 310    case SHADER_OPCODE_INT_QUOTIENT:
 311       return "int_quot";
 312    case SHADER_OPCODE_INT_REMAINDER:
 313       return "int_rem";
 314    case SHADER_OPCODE_SIN:
 315       return "sin";
 316    case SHADER_OPCODE_COS:
 317       return "cos";
 318
 319    case SHADER_OPCODE_TEX:
 320       return "tex";
 321    case SHADER_OPCODE_TEX_LOGICAL:
 322       return "tex_logical";
 323    case SHADER_OPCODE_TXD:
 324       return "txd";
 325    case SHADER_OPCODE_TXD_LOGICAL:
 326       return "txd_logical";
 327    case SHADER_OPCODE_TXF:
 328       return "txf";
 329    case SHADER_OPCODE_TXF_LOGICAL:
 330       return "txf_logical";
 331    case SHADER_OPCODE_TXL:
 332       return "txl";
 333    case SHADER_OPCODE_TXL_LOGICAL:
 334       return "txl_logical";
 335    case SHADER_OPCODE_TXS:
 336       return "txs";
 337    case SHADER_OPCODE_TXS_LOGICAL:
 338       return "txs_logical";
 339    case FS_OPCODE_TXB:
 340       return "txb";
 341    case FS_OPCODE_TXB_LOGICAL:
 342       return "txb_logical";
 343    case SHADER_OPCODE_TXF_CMS:
 344       return "txf_cms";
 345    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 346       return "txf_cms_logical";
 347    case SHADER_OPCODE_TXF_UMS:
 348       return "txf_ums";
 349    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 350       return "txf_ums_logical";
 351    case SHADER_OPCODE_TXF_MCS:
 352       return "txf_mcs";
 353    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 354       return "txf_mcs_logical";
 355    case SHADER_OPCODE_LOD:
 356       return "lod";
 357    case SHADER_OPCODE_LOD_LOGICAL:
 358       return "lod_logical";
 359    case SHADER_OPCODE_TG4:
 360       return "tg4";
 361    case SHADER_OPCODE_TG4_LOGICAL:
 362       return "tg4_logical";
 363    case SHADER_OPCODE_TG4_OFFSET:
 364       return "tg4_offset";
 365    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 366       return "tg4_offset_logical";
 367    case SHADER_OPCODE_SAMPLEINFO:
 368       return "sampleinfo";
 369
 370    case SHADER_OPCODE_SHADER_TIME_ADD:
 371       return "shader_time_add";
 372
 373    case SHADER_OPCODE_UNTYPED_ATOMIC:
 374       return "untyped_atomic";
 375    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 376       return "untyped_atomic_logical";
 377    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 378       return "untyped_surface_read";
 379    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 380       return "untyped_surface_read_logical";
 381    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 382       return "untyped_surface_write";
 383    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 384       return "untyped_surface_write_logical";
 385    case SHADER_OPCODE_TYPED_ATOMIC:
 386       return "typed_atomic";
 387    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 388       return "typed_atomic_logical";
 389    case SHADER_OPCODE_TYPED_SURFACE_READ:
 390       return "typed_surface_read";
 391    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 392       return "typed_surface_read_logical";
 393    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 394       return "typed_surface_write";
 395    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 396       return "typed_surface_write_logical";
 397    case SHADER_OPCODE_MEMORY_FENCE:
 398       return "memory_fence";
 399
 400    case SHADER_OPCODE_LOAD_PAYLOAD:
 401       return "load_payload";
 402
 403    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 404       return "gen4_scratch_read";
 405    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 406       return "gen4_scratch_write";
 407    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 408       return "gen7_scratch_read";
 409    case SHADER_OPCODE_URB_WRITE_SIMD8:
 410       return "gen8_urb_write_simd8";
 411    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 412       return "gen8_urb_write_simd8_per_slot";
 413    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 414       return "gen8_urb_write_simd8_masked";
 415    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 416       return "gen8_urb_write_simd8_masked_per_slot";
 417
 418    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 419       return "find_live_channel";
 420    case SHADER_OPCODE_BROADCAST:
 421       return "broadcast";
 422
 423    case VEC4_OPCODE_MOV_BYTES:
 424       return "mov_bytes";
 425    case VEC4_OPCODE_PACK_BYTES:
 426       return "pack_bytes";
 427    case VEC4_OPCODE_UNPACK_UNIFORM:
 428       return "unpack_uniform";
 429
 430    case FS_OPCODE_DDX_COARSE:
 431       return "ddx_coarse";
 432    case FS_OPCODE_DDX_FINE:
 433       return "ddx_fine";
 434    case FS_OPCODE_DDY_COARSE:
 435       return "ddy_coarse";
 436    case FS_OPCODE_DDY_FINE:
 437       return "ddy_fine";
 438
 439    case FS_OPCODE_CINTERP:
 440       return "cinterp";
 441    case FS_OPCODE_LINTERP:
 442       return "linterp";
 443
 444    case FS_OPCODE_PIXEL_X:
 445       return "pixel_x";
 446    case FS_OPCODE_PIXEL_Y:
 447       return "pixel_y";
 448
 449    case FS_OPCODE_GET_BUFFER_SIZE:
 450       return "fs_get_buffer_size";
 451
 452    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 453       return "uniform_pull_const";
 454    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 455       return "uniform_pull_const_gen7";
 456    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 457       return "varying_pull_const";
 458    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 459       return "varying_pull_const_gen7";
 460
 461    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 462       return "mov_dispatch_to_flags";
 463    case FS_OPCODE_DISCARD_JUMP:
 464       return "discard_jump";
 465
 466    case FS_OPCODE_SET_SAMPLE_ID:
 467       return "set_sample_id";
 468    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 469       return "set_simd4x2_offset";
 470
 471    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 472       return "pack_half_2x16_split";
 473    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 474       return "unpack_half_2x16_split_x";
 475    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 476       return "unpack_half_2x16_split_y";
 477
 478    case FS_OPCODE_PLACEHOLDER_HALT:
 479       return "placeholder_halt";
 480
 481    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 482       return "interp_centroid";
 483    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 484       return "interp_sample";
 485    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 486       return "interp_shared_offset";
 487    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 488       return "interp_per_slot_offset";
 489
 490    case VS_OPCODE_URB_WRITE:
 491       return "vs_urb_write";
 492    case VS_OPCODE_PULL_CONSTANT_LOAD:
 493       return "pull_constant_load";
 494    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 495       return "pull_constant_load_gen7";
 496
 497    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 498       return "set_simd4x2_header_gen9";
 499
 500    case VS_OPCODE_GET_BUFFER_SIZE:
 501       return "vs_get_buffer_size";
 502
 503    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 504       return "unpack_flags_simd4x2";
 505
 506    case GS_OPCODE_URB_WRITE:
 507       return "gs_urb_write";
 508    case GS_OPCODE_URB_WRITE_ALLOCATE:
 509       return "gs_urb_write_allocate";
 510    case GS_OPCODE_THREAD_END:
 511       return "gs_thread_end";
 512    case GS_OPCODE_SET_WRITE_OFFSET:
 513       return "set_write_offset";
 514    case GS_OPCODE_SET_VERTEX_COUNT:
 515       return "set_vertex_count";
 516    case GS_OPCODE_SET_DWORD_2:
 517       return "set_dword_2";
 518    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 519       return "prepare_channel_masks";
 520    case GS_OPCODE_SET_CHANNEL_MASKS:
 521       return "set_channel_masks";
 522    case GS_OPCODE_GET_INSTANCE_ID:
 523       return "get_instance_id";
 524    case GS_OPCODE_FF_SYNC:
 525       return "ff_sync";
 526    case GS_OPCODE_SET_PRIMITIVE_ID:
 527       return "set_primitive_id";
 528    case GS_OPCODE_SVB_WRITE:
 529       return "gs_svb_write";
 530    case GS_OPCODE_SVB_SET_DST_INDEX:
 531       return "gs_svb_set_dst_index";
 532    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 533       return "gs_ff_sync_set_primitives";
 534    case CS_OPCODE_CS_TERMINATE:
 535       return "cs_terminate";
 536    case SHADER_OPCODE_BARRIER:
 537       return "barrier";
 538    case SHADER_OPCODE_MULH:
 539       return "mulh";
 540    }
 541
 542    unreachable("not reached");
 543 }
 544
 545 bool
 546 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 547 {
 548    union {
 549       unsigned ud;
 550       int d;
 551       float f;
 552    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 553
 554    switch (type) {
 555    case BRW_REGISTER_TYPE_UD:
 556    case BRW_REGISTER_TYPE_D:
 557    case BRW_REGISTER_TYPE_UQ:
 558    case BRW_REGISTER_TYPE_Q:
 559       /* Nothing to do. */
 560       return false;
 561    case BRW_REGISTER_TYPE_UW:
 562       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 563       break;
 564    case BRW_REGISTER_TYPE_W:
 565       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 566       break;
 567    case BRW_REGISTER_TYPE_F:
 568       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 569       break;
 570    case BRW_REGISTER_TYPE_UB:
 571    case BRW_REGISTER_TYPE_B:
 572       unreachable("no UB/B immediates");
 573    case BRW_REGISTER_TYPE_V:
 574    case BRW_REGISTER_TYPE_UV:
 575    case BRW_REGISTER_TYPE_VF:
 576       unreachable("unimplemented: saturate vector immediate");
 577    case BRW_REGISTER_TYPE_DF:
 578    case BRW_REGISTER_TYPE_HF:
 579       unreachable("unimplemented: saturate DF/HF immediate");
 580    }
 581
 582    if (imm.ud != sat_imm.ud) {
 583       reg->dw1.ud = sat_imm.ud;
 584       return true;
 585    }
 586    return false;
 587 }
 588
 589 bool
 590 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 591 {
 592    switch (type) {
 593    case BRW_REGISTER_TYPE_D:
 594    case BRW_REGISTER_TYPE_UD:
 595       reg->dw1.d = -reg->dw1.d;
 596       return true;
 597    case BRW_REGISTER_TYPE_W:
 598    case BRW_REGISTER_TYPE_UW:
 599       reg->dw1.d = -(int16_t)reg->dw1.ud;
 600       return true;
 601    case BRW_REGISTER_TYPE_F:
 602       reg->dw1.f = -reg->dw1.f;
 603       return true;
 604    case BRW_REGISTER_TYPE_VF:
 605       reg->dw1.ud ^= 0x80808080;
 606       return true;
 607    case BRW_REGISTER_TYPE_UB:
 608    case BRW_REGISTER_TYPE_B:
 609       unreachable("no UB/B immediates");
 610    case BRW_REGISTER_TYPE_UV:
 611    case BRW_REGISTER_TYPE_V:
 612       assert(!"unimplemented: negate UV/V immediate");
 613    case BRW_REGISTER_TYPE_UQ:
 614    case BRW_REGISTER_TYPE_Q:
 615       assert(!"unimplemented: negate UQ/Q immediate");
 616    case BRW_REGISTER_TYPE_DF:
 617    case BRW_REGISTER_TYPE_HF:
 618       assert(!"unimplemented: negate DF/HF immediate");
 619    }
 620
 621    return false;
 622 }
 623
 624 bool
 625 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 626 {
 627    switch (type) {
 628    case BRW_REGISTER_TYPE_D:
 629       reg->dw1.d = abs(reg->dw1.d);
 630       return true;
 631    case BRW_REGISTER_TYPE_W:
 632       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 633       return true;
 634    case BRW_REGISTER_TYPE_F:
 635       reg->dw1.f = fabsf(reg->dw1.f);
 636       return true;
 637    case BRW_REGISTER_TYPE_VF:
 638       reg->dw1.ud &= ~0x80808080;
 639       return true;
 640    case BRW_REGISTER_TYPE_UB:
 641    case BRW_REGISTER_TYPE_B:
 642       unreachable("no UB/B immediates");
 643    case BRW_REGISTER_TYPE_UQ:
 644    case BRW_REGISTER_TYPE_UD:
 645    case BRW_REGISTER_TYPE_UW:
 646    case BRW_REGISTER_TYPE_UV:
 647       /* Presumably the absolute value modifier on an unsigned source is a
 648        * nop, but it would be nice to confirm.
 649        */
 650       assert(!"unimplemented: abs unsigned immediate");
 651    case BRW_REGISTER_TYPE_V:
 652       assert(!"unimplemented: abs V immediate");
 653    case BRW_REGISTER_TYPE_Q:
 654       assert(!"unimplemented: abs Q immediate");
 655    case BRW_REGISTER_TYPE_DF:
 656    case BRW_REGISTER_TYPE_HF:
 657       assert(!"unimplemented: abs DF/HF immediate");
 658    }
 659
 660    return false;
 661 }
 662
 663 backend_shader::backend_shader(const struct brw_compiler *compiler,
 664                                void *log_data,
 665                                void *mem_ctx,
 666                                const nir_shader *shader,
 667                                struct brw_stage_prog_data *stage_prog_data)
 668    : compiler(compiler),
 669      log_data(log_data),
 670      devinfo(compiler->devinfo),
 671      nir(shader),
 672      stage_prog_data(stage_prog_data),
 673      mem_ctx(mem_ctx),
 674      cfg(NULL),
 675      stage(shader->stage)
 676 {
 677    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 678    stage_name = _mesa_shader_stage_to_string(stage);
 679    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 680 }
 681
 682 bool
 683 backend_reg::is_zero() const
 684 {
 685    if (file != IMM)
 686       return false;
 687
 688    return fixed_hw_reg.dw1.d == 0;
 689 }
 690
 691 bool
 692 backend_reg::is_one() const
 693 {
 694    if (file != IMM)
 695       return false;
 696
 697    return type == BRW_REGISTER_TYPE_F
 698           ? fixed_hw_reg.dw1.f == 1.0
 699           : fixed_hw_reg.dw1.d == 1;
 700 }
 701
 702 bool
 703 backend_reg::is_negative_one() const
 704 {
 705    if (file != IMM)
 706       return false;
 707
 708    switch (type) {
 709    case BRW_REGISTER_TYPE_F:
 710       return fixed_hw_reg.dw1.f == -1.0;
 711    case BRW_REGISTER_TYPE_D:
 712       return fixed_hw_reg.dw1.d == -1;
 713    default:
 714       return false;
 715    }
 716 }
 717
 718 bool
 719 backend_reg::is_null() const
 720 {
 721    return file == HW_REG &&
 722           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 723           fixed_hw_reg.nr == BRW_ARF_NULL;
 724 }
 725
 726
 727 bool
 728 backend_reg::is_accumulator() const
 729 {
 730    return file == HW_REG &&
 731           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 732           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 733 }
 734
 735 bool
 736 backend_reg::in_range(const backend_reg &r, unsigned n) const
 737 {
 738    return (file == r.file &&
 739            reg == r.reg &&
 740            reg_offset >= r.reg_offset &&
 741            reg_offset < r.reg_offset + n);
 742 }
 743
 744 bool
 745 backend_instruction::is_commutative() const
 746 {
 747    switch (opcode) {
 748    case BRW_OPCODE_AND:
 749    case BRW_OPCODE_OR:
 750    case BRW_OPCODE_XOR:
 751    case BRW_OPCODE_ADD:
 752    case BRW_OPCODE_MUL:
 753    case SHADER_OPCODE_MULH:
 754       return true;
 755    case BRW_OPCODE_SEL:
 756       /* MIN and MAX are commutative. */
 757       if (conditional_mod == BRW_CONDITIONAL_GE ||
 758           conditional_mod == BRW_CONDITIONAL_L) {
 759          return true;
 760       }
 761       /* fallthrough */
 762    default:
 763       return false;
 764    }
 765 }
 766
 767 bool
 768 backend_instruction::is_3src() const
 769 {
 770    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 771 }
 772
 773 bool
 774 backend_instruction::is_tex() const
 775 {
 776    return (opcode == SHADER_OPCODE_TEX ||
 777            opcode == FS_OPCODE_TXB ||
 778            opcode == SHADER_OPCODE_TXD ||
 779            opcode == SHADER_OPCODE_TXF ||
 780            opcode == SHADER_OPCODE_TXF_CMS ||
 781            opcode == SHADER_OPCODE_TXF_UMS ||
 782            opcode == SHADER_OPCODE_TXF_MCS ||
 783            opcode == SHADER_OPCODE_TXL ||
 784            opcode == SHADER_OPCODE_TXS ||
 785            opcode == SHADER_OPCODE_LOD ||
 786            opcode == SHADER_OPCODE_TG4 ||
 787            opcode == SHADER_OPCODE_TG4_OFFSET);
 788 }
 789
 790 bool
 791 backend_instruction::is_math() const
 792 {
 793    return (opcode == SHADER_OPCODE_RCP ||
 794            opcode == SHADER_OPCODE_RSQ ||
 795            opcode == SHADER_OPCODE_SQRT ||
 796            opcode == SHADER_OPCODE_EXP2 ||
 797            opcode == SHADER_OPCODE_LOG2 ||
 798            opcode == SHADER_OPCODE_SIN ||
 799            opcode == SHADER_OPCODE_COS ||
 800            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 801            opcode == SHADER_OPCODE_INT_REMAINDER ||
 802            opcode == SHADER_OPCODE_POW);
 803 }
 804
 805 bool
 806 backend_instruction::is_control_flow() const
 807 {
 808    switch (opcode) {
 809    case BRW_OPCODE_DO:
 810    case BRW_OPCODE_WHILE:
 811    case BRW_OPCODE_IF:
 812    case BRW_OPCODE_ELSE:
 813    case BRW_OPCODE_ENDIF:
 814    case BRW_OPCODE_BREAK:
 815    case BRW_OPCODE_CONTINUE:
 816       return true;
 817    default:
 818       return false;
 819    }
 820 }
 821
 822 bool
 823 backend_instruction::can_do_source_mods() const
 824 {
 825    switch (opcode) {
 826    case BRW_OPCODE_ADDC:
 827    case BRW_OPCODE_BFE:
 828    case BRW_OPCODE_BFI1:
 829    case BRW_OPCODE_BFI2:
 830    case BRW_OPCODE_BFREV:
 831    case BRW_OPCODE_CBIT:
 832    case BRW_OPCODE_FBH:
 833    case BRW_OPCODE_FBL:
 834    case BRW_OPCODE_SUBB:
 835       return false;
 836    default:
 837       return true;
 838    }
 839 }
 840
 841 bool
 842 backend_instruction::can_do_saturate() const
 843 {
 844    switch (opcode) {
 845    case BRW_OPCODE_ADD:
 846    case BRW_OPCODE_ASR:
 847    case BRW_OPCODE_AVG:
 848    case BRW_OPCODE_DP2:
 849    case BRW_OPCODE_DP3:
 850    case BRW_OPCODE_DP4:
 851    case BRW_OPCODE_DPH:
 852    case BRW_OPCODE_F16TO32:
 853    case BRW_OPCODE_F32TO16:
 854    case BRW_OPCODE_LINE:
 855    case BRW_OPCODE_LRP:
 856    case BRW_OPCODE_MAC:
 857    case BRW_OPCODE_MAD:
 858    case BRW_OPCODE_MATH:
 859    case BRW_OPCODE_MOV:
 860    case BRW_OPCODE_MUL:
 861    case SHADER_OPCODE_MULH:
 862    case BRW_OPCODE_PLN:
 863    case BRW_OPCODE_RNDD:
 864    case BRW_OPCODE_RNDE:
 865    case BRW_OPCODE_RNDU:
 866    case BRW_OPCODE_RNDZ:
 867    case BRW_OPCODE_SEL:
 868    case BRW_OPCODE_SHL:
 869    case BRW_OPCODE_SHR:
 870    case FS_OPCODE_LINTERP:
 871    case SHADER_OPCODE_COS:
 872    case SHADER_OPCODE_EXP2:
 873    case SHADER_OPCODE_LOG2:
 874    case SHADER_OPCODE_POW:
 875    case SHADER_OPCODE_RCP:
 876    case SHADER_OPCODE_RSQ:
 877    case SHADER_OPCODE_SIN:
 878    case SHADER_OPCODE_SQRT:
 879       return true;
 880    default:
 881       return false;
 882    }
 883 }
 884
 885 bool
 886 backend_instruction::can_do_cmod() const
 887 {
 888    switch (opcode) {
 889    case BRW_OPCODE_ADD:
 890    case BRW_OPCODE_ADDC:
 891    case BRW_OPCODE_AND:
 892    case BRW_OPCODE_ASR:
 893    case BRW_OPCODE_AVG:
 894    case BRW_OPCODE_CMP:
 895    case BRW_OPCODE_CMPN:
 896    case BRW_OPCODE_DP2:
 897    case BRW_OPCODE_DP3:
 898    case BRW_OPCODE_DP4:
 899    case BRW_OPCODE_DPH:
 900    case BRW_OPCODE_F16TO32:
 901    case BRW_OPCODE_F32TO16:
 902    case BRW_OPCODE_FRC:
 903    case BRW_OPCODE_LINE:
 904    case BRW_OPCODE_LRP:
 905    case BRW_OPCODE_LZD:
 906    case BRW_OPCODE_MAC:
 907    case BRW_OPCODE_MACH:
 908    case BRW_OPCODE_MAD:
 909    case BRW_OPCODE_MOV:
 910    case BRW_OPCODE_MUL:
 911    case BRW_OPCODE_NOT:
 912    case BRW_OPCODE_OR:
 913    case BRW_OPCODE_PLN:
 914    case BRW_OPCODE_RNDD:
 915    case BRW_OPCODE_RNDE:
 916    case BRW_OPCODE_RNDU:
 917    case BRW_OPCODE_RNDZ:
 918    case BRW_OPCODE_SAD2:
 919    case BRW_OPCODE_SADA2:
 920    case BRW_OPCODE_SHL:
 921    case BRW_OPCODE_SHR:
 922    case BRW_OPCODE_SUBB:
 923    case BRW_OPCODE_XOR:
 924    case FS_OPCODE_CINTERP:
 925    case FS_OPCODE_LINTERP:
 926       return true;
 927    default:
 928       return false;
 929    }
 930 }
 931
 932 bool
 933 backend_instruction::reads_accumulator_implicitly() const
 934 {
 935    switch (opcode) {
 936    case BRW_OPCODE_MAC:
 937    case BRW_OPCODE_MACH:
 938    case BRW_OPCODE_SADA2:
 939       return true;
 940    default:
 941       return false;
 942    }
 943 }
 944
 945 bool
 946 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 947 {
 948    return writes_accumulator ||
 949           (devinfo->gen < 6 &&
 950            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 951             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 952              opcode != FS_OPCODE_CINTERP)));
 953 }
 954
 955 bool
 956 backend_instruction::has_side_effects() const
 957 {
 958    switch (opcode) {
 959    case SHADER_OPCODE_UNTYPED_ATOMIC:
 960    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 961    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 962    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 963    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 964    case SHADER_OPCODE_TYPED_ATOMIC:
 965    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 966    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 967    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 968    case SHADER_OPCODE_MEMORY_FENCE:
 969    case SHADER_OPCODE_URB_WRITE_SIMD8:
 970    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 971    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 972    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 973    case FS_OPCODE_FB_WRITE:
 974    case SHADER_OPCODE_BARRIER:
 975       return true;
 976    default:
 977       return false;
 978    }
 979 }
 980
 981 #ifndef NDEBUG
 982 static bool
 983 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 984 {
 985    bool found = false;
 986    foreach_inst_in_block (backend_instruction, i, block) {
 987       if (inst == i) {
 988          found = true;
 989       }
 990    }
 991    return found;
 992 }
 993 #endif
 994
 995 static void
 996 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 997 {
 998    for (bblock_t *block_iter = start_block->next();
 999         !block_iter->link.is_tail_sentinel();
1000         block_iter = block_iter->next()) {
1001       block_iter->start_ip += ip_adjustment;
1002       block_iter->end_ip += ip_adjustment;
1003    }
1004 }
1005
1006 void
1007 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1008 {
1009    if (!this->is_head_sentinel())
1010       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1011
1012    block->end_ip++;
1013
1014    adjust_later_block_ips(block, 1);
1015
1016    exec_node::insert_after(inst);
1017 }
1018
1019 void
1020 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1021 {
1022    if (!this->is_tail_sentinel())
1023       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1024
1025    block->end_ip++;
1026
1027    adjust_later_block_ips(block, 1);
1028
1029    exec_node::insert_before(inst);
1030 }
1031
1032 void
1033 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1034 {
1035    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1036
1037    unsigned num_inst = list->length();
1038
1039    block->end_ip += num_inst;
1040
1041    adjust_later_block_ips(block, num_inst);
1042
1043    exec_node::insert_before(list);
1044 }
1045
1046 void
1047 backend_instruction::remove(bblock_t *block)
1048 {
1049    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1050
1051    adjust_later_block_ips(block, -1);
1052
1053    if (block->start_ip == block->end_ip) {
1054       block->cfg->remove_block(block);
1055    } else {
1056       block->end_ip--;
1057    }
1058
1059    exec_node::remove();
1060 }
1061
1062 void
1063 backend_shader::dump_instructions()
1064 {
1065    dump_instructions(NULL);
1066 }
1067
1068 void
1069 backend_shader::dump_instructions(const char *name)
1070 {
1071    FILE *file = stderr;
1072    if (name && geteuid() != 0) {
1073       file = fopen(name, "w");
1074       if (!file)
1075          file = stderr;
1076    }
1077
1078    if (cfg) {
1079       int ip = 0;
1080       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1081          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1082             fprintf(file, "%4d: ", ip++);
1083          dump_instruction(inst, file);
1084       }
1085    } else {
1086       int ip = 0;
1087       foreach_in_list(backend_instruction, inst, &instructions) {
1088          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1089             fprintf(file, "%4d: ", ip++);
1090          dump_instruction(inst, file);
1091       }
1092    }
1093
1094    if (file != stderr) {
1095       fclose(file);
1096    }
1097 }
1098
1099 void
1100 backend_shader::calculate_cfg()
1101 {
1102    if (this->cfg)
1103       return;
1104    cfg = new(mem_ctx) cfg_t(&this->instructions);
1105 }
1106
1107 void
1108 backend_shader::invalidate_cfg()
1109 {
1110    ralloc_free(this->cfg);
1111    this->cfg = NULL;
1112 }
1113
1114 /**
1115  * Sets up the starting offsets for the groups of binding table entries
1116  * commong to all pipeline stages.
1117  *
1118  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1119  * unused but also make sure that addition of small offsets to them will
1120  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1121  */
1122 void
1123 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1124                                         const struct brw_device_info *devinfo,
1125                                         const struct gl_shader_program *shader_prog,
1126                                         const struct gl_program *prog,
1127                                         struct brw_stage_prog_data *stage_prog_data,
1128                                         uint32_t next_binding_table_offset)
1129 {
1130    const struct gl_shader *shader = NULL;
1131    int num_textures = _mesa_fls(prog->SamplersUsed);
1132
1133    if (shader_prog)
1134       shader = shader_prog->_LinkedShaders[stage];
1135
1136    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1137    next_binding_table_offset += num_textures;
1138
1139    if (shader) {
1140       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1141       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1142       next_binding_table_offset += shader->NumUniformBlocks;
1143
1144       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1145       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1146       next_binding_table_offset += shader->NumShaderStorageBlocks;
1147    } else {
1148       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1149       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1150    }
1151
1152    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1153       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1154       next_binding_table_offset++;
1155    } else {
1156       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1157    }
1158
1159    if (prog->UsesGather) {
1160       if (devinfo->gen >= 8) {
1161          stage_prog_data->binding_table.gather_texture_start =
1162             stage_prog_data->binding_table.texture_start;
1163       } else {
1164          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1165          next_binding_table_offset += num_textures;
1166       }
1167    } else {
1168       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1169    }
1170
1171    if (shader_prog && shader_prog->NumAtomicBuffers) {
1172       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1173       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1174    } else {
1175       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1176    }
1177
1178    if (shader && shader->NumImages) {
1179       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1180       next_binding_table_offset += shader->NumImages;
1181    } else {
1182       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1183    }
1184
1185    /* This may or may not be used depending on how the compile goes. */
1186    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1187    next_binding_table_offset++;
1188
1189    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1190
1191    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1192 }
1193
1194 static void
1195 setup_vec4_uniform_value(const gl_constant_value **params,
1196                          const gl_constant_value *values,
1197                          unsigned n)
1198 {
1199    static const gl_constant_value zero = { 0 };
1200
1201    for (unsigned i = 0; i < n; ++i)
1202       params[i] = &values[i];
1203
1204    for (unsigned i = n; i < 4; ++i)
1205       params[i] = &zero;
1206 }
1207
1208 void
1209 brw_setup_image_uniform_values(gl_shader_stage stage,
1210                                struct brw_stage_prog_data *stage_prog_data,
1211                                unsigned param_start_index,
1212                                const gl_uniform_storage *storage)
1213 {
1214    const gl_constant_value **param =
1215       &stage_prog_data->param[param_start_index];
1216
1217    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1218       const unsigned image_idx = storage->opaque[stage].index + i;
1219       const brw_image_param *image_param =
1220          &stage_prog_data->image_param[image_idx];
1221
1222       /* Upload the brw_image_param structure.  The order is expected to match
1223        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1224        */
1225       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1226          (const gl_constant_value *)&image_param->surface_idx, 1);
1227       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1228          (const gl_constant_value *)image_param->offset, 2);
1229       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1230          (const gl_constant_value *)image_param->size, 3);
1231       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1232          (const gl_constant_value *)image_param->stride, 4);
1233       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1234          (const gl_constant_value *)image_param->tiling, 3);
1235       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1236          (const gl_constant_value *)image_param->swizzling, 2);
1237       param += BRW_IMAGE_PARAM_SIZE;
1238
1239       brw_mark_surface_used(
1240          stage_prog_data,
1241          stage_prog_data->binding_table.image_start + image_idx);
1242    }
1243 }
1244
1245 /**
1246  * Decide which set of clip planes should be used when clipping via
1247  * gl_Position or gl_ClipVertex.
1248  */
1249 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1250 {
1251    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1252       /* There is currently a GLSL vertex shader, so clip according to GLSL
1253        * rules, which means compare gl_ClipVertex (or gl_Position, if
1254        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1255        * that were stored in EyeUserPlane at the time the clip planes were
1256        * specified.
1257        */
1258       return ctx->Transform.EyeUserPlane;
1259    } else {
1260       /* Either we are using fixed function or an ARB vertex program.  In
1261        * either case the clip planes are going to be compared against
1262        * gl_Position (which is in clip coordinates) so we have to clip using
1263        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1264        * core.
1265        */
1266       return ctx->Transform._ClipUserPlane;
1267    }
1268 }
1269