src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/uniforms.h"
  31
  32 extern "C" void
  33 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
  34                       unsigned surf_index)
  35 {
  36    assert(surf_index < BRW_MAX_SURFACES);
  37
  38    prog_data->binding_table.size_bytes =
  39       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
  40 }
  41
  42 enum brw_reg_type
  43 brw_type_for_base_type(const struct glsl_type *type)
  44 {
  45    switch (type->base_type) {
  46    case GLSL_TYPE_FLOAT:
  47       return BRW_REGISTER_TYPE_F;
  48    case GLSL_TYPE_INT:
  49    case GLSL_TYPE_BOOL:
  50    case GLSL_TYPE_SUBROUTINE:
  51       return BRW_REGISTER_TYPE_D;
  52    case GLSL_TYPE_UINT:
  53       return BRW_REGISTER_TYPE_UD;
  54    case GLSL_TYPE_ARRAY:
  55       return brw_type_for_base_type(type->fields.array);
  56    case GLSL_TYPE_STRUCT:
  57    case GLSL_TYPE_SAMPLER:
  58    case GLSL_TYPE_ATOMIC_UINT:
  59       /* These should be overridden with the type of the member when
  60        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  61        * way to trip up if we don't.
  62        */
  63       return BRW_REGISTER_TYPE_UD;
  64    case GLSL_TYPE_IMAGE:
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_DOUBLE:
  67       return BRW_REGISTER_TYPE_DF;
  68    case GLSL_TYPE_VOID:
  69    case GLSL_TYPE_ERROR:
  70    case GLSL_TYPE_INTERFACE:
  71    case GLSL_TYPE_FUNCTION:
  72       unreachable("not reached");
  73    }
  74
  75    return BRW_REGISTER_TYPE_F;
  76 }
  77
  78 enum brw_conditional_mod
  79 brw_conditional_for_comparison(unsigned int op)
  80 {
  81    switch (op) {
  82    case ir_binop_less:
  83       return BRW_CONDITIONAL_L;
  84    case ir_binop_greater:
  85       return BRW_CONDITIONAL_G;
  86    case ir_binop_lequal:
  87       return BRW_CONDITIONAL_LE;
  88    case ir_binop_gequal:
  89       return BRW_CONDITIONAL_GE;
  90    case ir_binop_equal:
  91    case ir_binop_all_equal: /* same as equal for scalars */
  92       return BRW_CONDITIONAL_Z;
  93    case ir_binop_nequal:
  94    case ir_binop_any_nequal: /* same as nequal for scalars */
  95       return BRW_CONDITIONAL_NZ;
  96    default:
  97       unreachable("not reached: bad operation for comparison");
  98    }
  99 }
 100
 101 uint32_t
 102 brw_math_function(enum opcode op)
 103 {
 104    switch (op) {
 105    case SHADER_OPCODE_RCP:
 106       return BRW_MATH_FUNCTION_INV;
 107    case SHADER_OPCODE_RSQ:
 108       return BRW_MATH_FUNCTION_RSQ;
 109    case SHADER_OPCODE_SQRT:
 110       return BRW_MATH_FUNCTION_SQRT;
 111    case SHADER_OPCODE_EXP2:
 112       return BRW_MATH_FUNCTION_EXP;
 113    case SHADER_OPCODE_LOG2:
 114       return BRW_MATH_FUNCTION_LOG;
 115    case SHADER_OPCODE_POW:
 116       return BRW_MATH_FUNCTION_POW;
 117    case SHADER_OPCODE_SIN:
 118       return BRW_MATH_FUNCTION_SIN;
 119    case SHADER_OPCODE_COS:
 120       return BRW_MATH_FUNCTION_COS;
 121    case SHADER_OPCODE_INT_QUOTIENT:
 122       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 123    case SHADER_OPCODE_INT_REMAINDER:
 124       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 125    default:
 126       unreachable("not reached: unknown math function");
 127    }
 128 }
 129
 130 bool
 131 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 132 {
 133    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 134
 135    /* offset out of bounds; caller will handle it. */
 136    for (unsigned i = 0; i < num_components; i++)
 137       if (offsets[i] > 7 || offsets[i] < -8)
 138          return false;
 139
 140    /* Combine all three offsets into a single unsigned dword:
 141     *
 142     *    bits 11:8 - U Offset (X component)
 143     *    bits  7:4 - V Offset (Y component)
 144     *    bits  3:0 - R Offset (Z component)
 145     */
 146    *offset_bits = 0;
 147    for (unsigned i = 0; i < num_components; i++) {
 148       const unsigned shift = 4 * (2 - i);
 149       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 150    }
 151    return true;
 152 }
 153
 154 const char *
 155 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 156 {
 157    switch (op) {
 158    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 159       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 160        * start of a loop in the IR.
 161        */
 162       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 163          return "do";
 164
 165       assert(brw_opcode_desc(devinfo, op)->name);
 166       return brw_opcode_desc(devinfo, op)->name;
 167    case FS_OPCODE_FB_WRITE:
 168       return "fb_write";
 169    case FS_OPCODE_FB_WRITE_LOGICAL:
 170       return "fb_write_logical";
 171    case FS_OPCODE_REP_FB_WRITE:
 172       return "rep_fb_write";
 173    case FS_OPCODE_FB_READ:
 174       return "fb_read";
 175    case FS_OPCODE_FB_READ_LOGICAL:
 176       return "fb_read_logical";
 177
 178    case SHADER_OPCODE_RCP:
 179       return "rcp";
 180    case SHADER_OPCODE_RSQ:
 181       return "rsq";
 182    case SHADER_OPCODE_SQRT:
 183       return "sqrt";
 184    case SHADER_OPCODE_EXP2:
 185       return "exp2";
 186    case SHADER_OPCODE_LOG2:
 187       return "log2";
 188    case SHADER_OPCODE_POW:
 189       return "pow";
 190    case SHADER_OPCODE_INT_QUOTIENT:
 191       return "int_quot";
 192    case SHADER_OPCODE_INT_REMAINDER:
 193       return "int_rem";
 194    case SHADER_OPCODE_SIN:
 195       return "sin";
 196    case SHADER_OPCODE_COS:
 197       return "cos";
 198
 199    case SHADER_OPCODE_TEX:
 200       return "tex";
 201    case SHADER_OPCODE_TEX_LOGICAL:
 202       return "tex_logical";
 203    case SHADER_OPCODE_TXD:
 204       return "txd";
 205    case SHADER_OPCODE_TXD_LOGICAL:
 206       return "txd_logical";
 207    case SHADER_OPCODE_TXF:
 208       return "txf";
 209    case SHADER_OPCODE_TXF_LOGICAL:
 210       return "txf_logical";
 211    case SHADER_OPCODE_TXF_LZ:
 212       return "txf_lz";
 213    case SHADER_OPCODE_TXL:
 214       return "txl";
 215    case SHADER_OPCODE_TXL_LOGICAL:
 216       return "txl_logical";
 217    case SHADER_OPCODE_TXL_LZ:
 218       return "txl_lz";
 219    case SHADER_OPCODE_TXS:
 220       return "txs";
 221    case SHADER_OPCODE_TXS_LOGICAL:
 222       return "txs_logical";
 223    case FS_OPCODE_TXB:
 224       return "txb";
 225    case FS_OPCODE_TXB_LOGICAL:
 226       return "txb_logical";
 227    case SHADER_OPCODE_TXF_CMS:
 228       return "txf_cms";
 229    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 230       return "txf_cms_logical";
 231    case SHADER_OPCODE_TXF_CMS_W:
 232       return "txf_cms_w";
 233    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 234       return "txf_cms_w_logical";
 235    case SHADER_OPCODE_TXF_UMS:
 236       return "txf_ums";
 237    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 238       return "txf_ums_logical";
 239    case SHADER_OPCODE_TXF_MCS:
 240       return "txf_mcs";
 241    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 242       return "txf_mcs_logical";
 243    case SHADER_OPCODE_LOD:
 244       return "lod";
 245    case SHADER_OPCODE_LOD_LOGICAL:
 246       return "lod_logical";
 247    case SHADER_OPCODE_TG4:
 248       return "tg4";
 249    case SHADER_OPCODE_TG4_LOGICAL:
 250       return "tg4_logical";
 251    case SHADER_OPCODE_TG4_OFFSET:
 252       return "tg4_offset";
 253    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 254       return "tg4_offset_logical";
 255    case SHADER_OPCODE_SAMPLEINFO:
 256       return "sampleinfo";
 257    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 258       return "sampleinfo_logical";
 259
 260    case SHADER_OPCODE_SHADER_TIME_ADD:
 261       return "shader_time_add";
 262
 263    case SHADER_OPCODE_UNTYPED_ATOMIC:
 264       return "untyped_atomic";
 265    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 266       return "untyped_atomic_logical";
 267    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 268       return "untyped_surface_read";
 269    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 270       return "untyped_surface_read_logical";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 272       return "untyped_surface_write";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 274       return "untyped_surface_write_logical";
 275    case SHADER_OPCODE_TYPED_ATOMIC:
 276       return "typed_atomic";
 277    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 278       return "typed_atomic_logical";
 279    case SHADER_OPCODE_TYPED_SURFACE_READ:
 280       return "typed_surface_read";
 281    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 282       return "typed_surface_read_logical";
 283    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 284       return "typed_surface_write";
 285    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 286       return "typed_surface_write_logical";
 287    case SHADER_OPCODE_MEMORY_FENCE:
 288       return "memory_fence";
 289
 290    case SHADER_OPCODE_LOAD_PAYLOAD:
 291       return "load_payload";
 292    case FS_OPCODE_PACK:
 293       return "pack";
 294
 295    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 296       return "gen4_scratch_read";
 297    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 298       return "gen4_scratch_write";
 299    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 300       return "gen7_scratch_read";
 301    case SHADER_OPCODE_URB_WRITE_SIMD8:
 302       return "gen8_urb_write_simd8";
 303    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 304       return "gen8_urb_write_simd8_per_slot";
 305    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 306       return "gen8_urb_write_simd8_masked";
 307    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 308       return "gen8_urb_write_simd8_masked_per_slot";
 309    case SHADER_OPCODE_URB_READ_SIMD8:
 310       return "urb_read_simd8";
 311    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 312       return "urb_read_simd8_per_slot";
 313
 314    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 315       return "find_live_channel";
 316    case SHADER_OPCODE_BROADCAST:
 317       return "broadcast";
 318
 319    case VEC4_OPCODE_MOV_BYTES:
 320       return "mov_bytes";
 321    case VEC4_OPCODE_PACK_BYTES:
 322       return "pack_bytes";
 323    case VEC4_OPCODE_UNPACK_UNIFORM:
 324       return "unpack_uniform";
 325    case VEC4_OPCODE_FROM_DOUBLE:
 326       return "double_to_single";
 327    case VEC4_OPCODE_TO_DOUBLE:
 328       return "single_to_double";
 329    case VEC4_OPCODE_PICK_LOW_32BIT:
 330       return "pick_low_32bit";
 331    case VEC4_OPCODE_PICK_HIGH_32BIT:
 332       return "pick_high_32bit";
 333    case VEC4_OPCODE_SET_LOW_32BIT:
 334       return "set_low_32bit";
 335    case VEC4_OPCODE_SET_HIGH_32BIT:
 336       return "set_high_32bit";
 337
 338    case FS_OPCODE_DDX_COARSE:
 339       return "ddx_coarse";
 340    case FS_OPCODE_DDX_FINE:
 341       return "ddx_fine";
 342    case FS_OPCODE_DDY_COARSE:
 343       return "ddy_coarse";
 344    case FS_OPCODE_DDY_FINE:
 345       return "ddy_fine";
 346
 347    case FS_OPCODE_CINTERP:
 348       return "cinterp";
 349    case FS_OPCODE_LINTERP:
 350       return "linterp";
 351
 352    case FS_OPCODE_PIXEL_X:
 353       return "pixel_x";
 354    case FS_OPCODE_PIXEL_Y:
 355       return "pixel_y";
 356
 357    case FS_OPCODE_GET_BUFFER_SIZE:
 358       return "fs_get_buffer_size";
 359
 360    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 361       return "uniform_pull_const";
 362    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 363       return "uniform_pull_const_gen7";
 364    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 365       return "varying_pull_const_gen4";
 366    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 367       return "varying_pull_const_gen7";
 368    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 369       return "varying_pull_const_logical";
 370
 371    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 372       return "mov_dispatch_to_flags";
 373    case FS_OPCODE_DISCARD_JUMP:
 374       return "discard_jump";
 375
 376    case FS_OPCODE_SET_SAMPLE_ID:
 377       return "set_sample_id";
 378
 379    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 380       return "pack_half_2x16_split";
 381    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 382       return "unpack_half_2x16_split_x";
 383    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 384       return "unpack_half_2x16_split_y";
 385
 386    case FS_OPCODE_PLACEHOLDER_HALT:
 387       return "placeholder_halt";
 388
 389    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 390       return "interp_sample";
 391    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 392       return "interp_shared_offset";
 393    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 394       return "interp_per_slot_offset";
 395
 396    case VS_OPCODE_URB_WRITE:
 397       return "vs_urb_write";
 398    case VS_OPCODE_PULL_CONSTANT_LOAD:
 399       return "pull_constant_load";
 400    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 401       return "pull_constant_load_gen7";
 402
 403    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 404       return "set_simd4x2_header_gen9";
 405
 406    case VS_OPCODE_GET_BUFFER_SIZE:
 407       return "vs_get_buffer_size";
 408
 409    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 410       return "unpack_flags_simd4x2";
 411
 412    case GS_OPCODE_URB_WRITE:
 413       return "gs_urb_write";
 414    case GS_OPCODE_URB_WRITE_ALLOCATE:
 415       return "gs_urb_write_allocate";
 416    case GS_OPCODE_THREAD_END:
 417       return "gs_thread_end";
 418    case GS_OPCODE_SET_WRITE_OFFSET:
 419       return "set_write_offset";
 420    case GS_OPCODE_SET_VERTEX_COUNT:
 421       return "set_vertex_count";
 422    case GS_OPCODE_SET_DWORD_2:
 423       return "set_dword_2";
 424    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 425       return "prepare_channel_masks";
 426    case GS_OPCODE_SET_CHANNEL_MASKS:
 427       return "set_channel_masks";
 428    case GS_OPCODE_GET_INSTANCE_ID:
 429       return "get_instance_id";
 430    case GS_OPCODE_FF_SYNC:
 431       return "ff_sync";
 432    case GS_OPCODE_SET_PRIMITIVE_ID:
 433       return "set_primitive_id";
 434    case GS_OPCODE_SVB_WRITE:
 435       return "gs_svb_write";
 436    case GS_OPCODE_SVB_SET_DST_INDEX:
 437       return "gs_svb_set_dst_index";
 438    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 439       return "gs_ff_sync_set_primitives";
 440    case CS_OPCODE_CS_TERMINATE:
 441       return "cs_terminate";
 442    case SHADER_OPCODE_BARRIER:
 443       return "barrier";
 444    case SHADER_OPCODE_MULH:
 445       return "mulh";
 446    case SHADER_OPCODE_MOV_INDIRECT:
 447       return "mov_indirect";
 448
 449    case VEC4_OPCODE_URB_READ:
 450       return "urb_read";
 451    case TCS_OPCODE_GET_INSTANCE_ID:
 452       return "tcs_get_instance_id";
 453    case TCS_OPCODE_URB_WRITE:
 454       return "tcs_urb_write";
 455    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 456       return "tcs_set_input_urb_offsets";
 457    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 458       return "tcs_set_output_urb_offsets";
 459    case TCS_OPCODE_GET_PRIMITIVE_ID:
 460       return "tcs_get_primitive_id";
 461    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 462       return "tcs_create_barrier_header";
 463    case TCS_OPCODE_SRC0_010_IS_ZERO:
 464       return "tcs_src0<0,1,0>_is_zero";
 465    case TCS_OPCODE_RELEASE_INPUT:
 466       return "tcs_release_input";
 467    case TCS_OPCODE_THREAD_END:
 468       return "tcs_thread_end";
 469    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 470       return "tes_create_input_read_header";
 471    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 472       return "tes_add_indirect_urb_offset";
 473    case TES_OPCODE_GET_PRIMITIVE_ID:
 474       return "tes_get_primitive_id";
 475    }
 476
 477    unreachable("not reached");
 478 }
 479
 480 bool
 481 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 482 {
 483    union {
 484       unsigned ud;
 485       int d;
 486       float f;
 487       double df;
 488    } imm, sat_imm = { 0 };
 489
 490    const unsigned size = type_sz(type);
 491
 492    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 493     * irrelevant, so just check the size of the type and copy from/to an
 494     * appropriately sized field.
 495     */
 496    if (size < 8)
 497       imm.ud = reg->ud;
 498    else
 499       imm.df = reg->df;
 500
 501    switch (type) {
 502    case BRW_REGISTER_TYPE_UD:
 503    case BRW_REGISTER_TYPE_D:
 504    case BRW_REGISTER_TYPE_UW:
 505    case BRW_REGISTER_TYPE_W:
 506    case BRW_REGISTER_TYPE_UQ:
 507    case BRW_REGISTER_TYPE_Q:
 508       /* Nothing to do. */
 509       return false;
 510    case BRW_REGISTER_TYPE_F:
 511       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 512       break;
 513    case BRW_REGISTER_TYPE_DF:
 514       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 515       break;
 516    case BRW_REGISTER_TYPE_UB:
 517    case BRW_REGISTER_TYPE_B:
 518       unreachable("no UB/B immediates");
 519    case BRW_REGISTER_TYPE_V:
 520    case BRW_REGISTER_TYPE_UV:
 521    case BRW_REGISTER_TYPE_VF:
 522       unreachable("unimplemented: saturate vector immediate");
 523    case BRW_REGISTER_TYPE_HF:
 524       unreachable("unimplemented: saturate HF immediate");
 525    }
 526
 527    if (size < 8) {
 528       if (imm.ud != sat_imm.ud) {
 529          reg->ud = sat_imm.ud;
 530          return true;
 531       }
 532    } else {
 533       if (imm.df != sat_imm.df) {
 534          reg->df = sat_imm.df;
 535          return true;
 536       }
 537    }
 538    return false;
 539 }
 540
 541 bool
 542 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 543 {
 544    switch (type) {
 545    case BRW_REGISTER_TYPE_D:
 546    case BRW_REGISTER_TYPE_UD:
 547       reg->d = -reg->d;
 548       return true;
 549    case BRW_REGISTER_TYPE_W:
 550    case BRW_REGISTER_TYPE_UW:
 551       reg->d = -(int16_t)reg->ud;
 552       return true;
 553    case BRW_REGISTER_TYPE_F:
 554       reg->f = -reg->f;
 555       return true;
 556    case BRW_REGISTER_TYPE_VF:
 557       reg->ud ^= 0x80808080;
 558       return true;
 559    case BRW_REGISTER_TYPE_DF:
 560       reg->df = -reg->df;
 561       return true;
 562    case BRW_REGISTER_TYPE_UB:
 563    case BRW_REGISTER_TYPE_B:
 564       unreachable("no UB/B immediates");
 565    case BRW_REGISTER_TYPE_UV:
 566    case BRW_REGISTER_TYPE_V:
 567       assert(!"unimplemented: negate UV/V immediate");
 568    case BRW_REGISTER_TYPE_UQ:
 569    case BRW_REGISTER_TYPE_Q:
 570       assert(!"unimplemented: negate UQ/Q immediate");
 571    case BRW_REGISTER_TYPE_HF:
 572       assert(!"unimplemented: negate HF immediate");
 573    }
 574
 575    return false;
 576 }
 577
 578 bool
 579 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 580 {
 581    switch (type) {
 582    case BRW_REGISTER_TYPE_D:
 583       reg->d = abs(reg->d);
 584       return true;
 585    case BRW_REGISTER_TYPE_W:
 586       reg->d = abs((int16_t)reg->ud);
 587       return true;
 588    case BRW_REGISTER_TYPE_F:
 589       reg->f = fabsf(reg->f);
 590       return true;
 591    case BRW_REGISTER_TYPE_DF:
 592       reg->df = fabs(reg->df);
 593       return true;
 594    case BRW_REGISTER_TYPE_VF:
 595       reg->ud &= ~0x80808080;
 596       return true;
 597    case BRW_REGISTER_TYPE_UB:
 598    case BRW_REGISTER_TYPE_B:
 599       unreachable("no UB/B immediates");
 600    case BRW_REGISTER_TYPE_UQ:
 601    case BRW_REGISTER_TYPE_UD:
 602    case BRW_REGISTER_TYPE_UW:
 603    case BRW_REGISTER_TYPE_UV:
 604       /* Presumably the absolute value modifier on an unsigned source is a
 605        * nop, but it would be nice to confirm.
 606        */
 607       assert(!"unimplemented: abs unsigned immediate");
 608    case BRW_REGISTER_TYPE_V:
 609       assert(!"unimplemented: abs V immediate");
 610    case BRW_REGISTER_TYPE_Q:
 611       assert(!"unimplemented: abs Q immediate");
 612    case BRW_REGISTER_TYPE_HF:
 613       assert(!"unimplemented: abs HF immediate");
 614    }
 615
 616    return false;
 617 }
 618
 619 /**
 620  * Get the appropriate atomic op for an image atomic intrinsic.
 621  */
 622 unsigned
 623 get_atomic_counter_op(nir_intrinsic_op op)
 624 {
 625    switch (op) {
 626    case nir_intrinsic_atomic_counter_inc:
 627       return BRW_AOP_INC;
 628    case nir_intrinsic_atomic_counter_dec:
 629       return BRW_AOP_PREDEC;
 630    case nir_intrinsic_atomic_counter_add:
 631       return BRW_AOP_ADD;
 632    case nir_intrinsic_atomic_counter_min:
 633       return BRW_AOP_UMIN;
 634    case nir_intrinsic_atomic_counter_max:
 635       return BRW_AOP_UMAX;
 636    case nir_intrinsic_atomic_counter_and:
 637       return BRW_AOP_AND;
 638    case nir_intrinsic_atomic_counter_or:
 639       return BRW_AOP_OR;
 640    case nir_intrinsic_atomic_counter_xor:
 641       return BRW_AOP_XOR;
 642    case nir_intrinsic_atomic_counter_exchange:
 643       return BRW_AOP_MOV;
 644    case nir_intrinsic_atomic_counter_comp_swap:
 645       return BRW_AOP_CMPWR;
 646    default:
 647       unreachable("Not reachable.");
 648    }
 649 }
 650
 651 unsigned
 652 tesslevel_outer_components(GLenum tes_primitive_mode)
 653 {
 654    switch (tes_primitive_mode) {
 655    case GL_QUADS:
 656       return 4;
 657    case GL_TRIANGLES:
 658       return 3;
 659    case GL_ISOLINES:
 660       return 2;
 661    default:
 662       unreachable("Bogus tessellation domain");
 663    }
 664    return 0;
 665 }
 666
 667 unsigned
 668 tesslevel_inner_components(GLenum tes_primitive_mode)
 669 {
 670    switch (tes_primitive_mode) {
 671    case GL_QUADS:
 672       return 2;
 673    case GL_TRIANGLES:
 674       return 1;
 675    case GL_ISOLINES:
 676       return 0;
 677    default:
 678       unreachable("Bogus tessellation domain");
 679    }
 680    return 0;
 681 }
 682
 683 /**
 684  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 685  * that's stored backwards, i.e. .wzyx.
 686  */
 687 unsigned
 688 writemask_for_backwards_vector(unsigned mask)
 689 {
 690    unsigned new_mask = 0;
 691
 692    for (int i = 0; i < 4; i++)
 693       new_mask |= ((mask >> i) & 1) << (3 - i);
 694
 695    return new_mask;
 696 }
 697
 698 backend_shader::backend_shader(const struct brw_compiler *compiler,
 699                                void *log_data,
 700                                void *mem_ctx,
 701                                const nir_shader *shader,
 702                                struct brw_stage_prog_data *stage_prog_data)
 703    : compiler(compiler),
 704      log_data(log_data),
 705      devinfo(compiler->devinfo),
 706      nir(shader),
 707      stage_prog_data(stage_prog_data),
 708      mem_ctx(mem_ctx),
 709      cfg(NULL),
 710      stage(shader->stage)
 711 {
 712    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 713    stage_name = _mesa_shader_stage_to_string(stage);
 714    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 715    is_passthrough_shader =
 716       nir->info->name && strcmp(nir->info->name, "passthrough") == 0;
 717 }
 718
 719 bool
 720 backend_reg::equals(const backend_reg &r) const
 721 {
 722    return brw_regs_equal(this, &r) && offset == r.offset;
 723 }
 724
 725 bool
 726 backend_reg::is_zero() const
 727 {
 728    if (file != IMM)
 729       return false;
 730
 731    switch (type) {
 732    case BRW_REGISTER_TYPE_F:
 733       return f == 0;
 734    case BRW_REGISTER_TYPE_DF:
 735       return df == 0;
 736    case BRW_REGISTER_TYPE_D:
 737    case BRW_REGISTER_TYPE_UD:
 738       return d == 0;
 739    default:
 740       return false;
 741    }
 742 }
 743
 744 bool
 745 backend_reg::is_one() const
 746 {
 747    if (file != IMM)
 748       return false;
 749
 750    switch (type) {
 751    case BRW_REGISTER_TYPE_F:
 752       return f == 1.0f;
 753    case BRW_REGISTER_TYPE_DF:
 754       return df == 1.0;
 755    case BRW_REGISTER_TYPE_D:
 756    case BRW_REGISTER_TYPE_UD:
 757       return d == 1;
 758    default:
 759       return false;
 760    }
 761 }
 762
 763 bool
 764 backend_reg::is_negative_one() const
 765 {
 766    if (file != IMM)
 767       return false;
 768
 769    switch (type) {
 770    case BRW_REGISTER_TYPE_F:
 771       return f == -1.0;
 772    case BRW_REGISTER_TYPE_DF:
 773       return df == -1.0;
 774    case BRW_REGISTER_TYPE_D:
 775       return d == -1;
 776    default:
 777       return false;
 778    }
 779 }
 780
 781 bool
 782 backend_reg::is_null() const
 783 {
 784    return file == ARF && nr == BRW_ARF_NULL;
 785 }
 786
 787
 788 bool
 789 backend_reg::is_accumulator() const
 790 {
 791    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 792 }
 793
 794 bool
 795 backend_instruction::is_commutative() const
 796 {
 797    switch (opcode) {
 798    case BRW_OPCODE_AND:
 799    case BRW_OPCODE_OR:
 800    case BRW_OPCODE_XOR:
 801    case BRW_OPCODE_ADD:
 802    case BRW_OPCODE_MUL:
 803    case SHADER_OPCODE_MULH:
 804       return true;
 805    case BRW_OPCODE_SEL:
 806       /* MIN and MAX are commutative. */
 807       if (conditional_mod == BRW_CONDITIONAL_GE ||
 808           conditional_mod == BRW_CONDITIONAL_L) {
 809          return true;
 810       }
 811       /* fallthrough */
 812    default:
 813       return false;
 814    }
 815 }
 816
 817 bool
 818 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 819 {
 820    return ::is_3src(devinfo, opcode);
 821 }
 822
 823 bool
 824 backend_instruction::is_tex() const
 825 {
 826    return (opcode == SHADER_OPCODE_TEX ||
 827            opcode == FS_OPCODE_TXB ||
 828            opcode == SHADER_OPCODE_TXD ||
 829            opcode == SHADER_OPCODE_TXF ||
 830            opcode == SHADER_OPCODE_TXF_LZ ||
 831            opcode == SHADER_OPCODE_TXF_CMS ||
 832            opcode == SHADER_OPCODE_TXF_CMS_W ||
 833            opcode == SHADER_OPCODE_TXF_UMS ||
 834            opcode == SHADER_OPCODE_TXF_MCS ||
 835            opcode == SHADER_OPCODE_TXL ||
 836            opcode == SHADER_OPCODE_TXL_LZ ||
 837            opcode == SHADER_OPCODE_TXS ||
 838            opcode == SHADER_OPCODE_LOD ||
 839            opcode == SHADER_OPCODE_TG4 ||
 840            opcode == SHADER_OPCODE_TG4_OFFSET ||
 841            opcode == SHADER_OPCODE_SAMPLEINFO);
 842 }
 843
 844 bool
 845 backend_instruction::is_math() const
 846 {
 847    return (opcode == SHADER_OPCODE_RCP ||
 848            opcode == SHADER_OPCODE_RSQ ||
 849            opcode == SHADER_OPCODE_SQRT ||
 850            opcode == SHADER_OPCODE_EXP2 ||
 851            opcode == SHADER_OPCODE_LOG2 ||
 852            opcode == SHADER_OPCODE_SIN ||
 853            opcode == SHADER_OPCODE_COS ||
 854            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 855            opcode == SHADER_OPCODE_INT_REMAINDER ||
 856            opcode == SHADER_OPCODE_POW);
 857 }
 858
 859 bool
 860 backend_instruction::is_control_flow() const
 861 {
 862    switch (opcode) {
 863    case BRW_OPCODE_DO:
 864    case BRW_OPCODE_WHILE:
 865    case BRW_OPCODE_IF:
 866    case BRW_OPCODE_ELSE:
 867    case BRW_OPCODE_ENDIF:
 868    case BRW_OPCODE_BREAK:
 869    case BRW_OPCODE_CONTINUE:
 870       return true;
 871    default:
 872       return false;
 873    }
 874 }
 875
 876 bool
 877 backend_instruction::can_do_source_mods() const
 878 {
 879    switch (opcode) {
 880    case BRW_OPCODE_ADDC:
 881    case BRW_OPCODE_BFE:
 882    case BRW_OPCODE_BFI1:
 883    case BRW_OPCODE_BFI2:
 884    case BRW_OPCODE_BFREV:
 885    case BRW_OPCODE_CBIT:
 886    case BRW_OPCODE_FBH:
 887    case BRW_OPCODE_FBL:
 888    case BRW_OPCODE_SUBB:
 889       return false;
 890    default:
 891       return true;
 892    }
 893 }
 894
 895 bool
 896 backend_instruction::can_do_saturate() const
 897 {
 898    switch (opcode) {
 899    case BRW_OPCODE_ADD:
 900    case BRW_OPCODE_ASR:
 901    case BRW_OPCODE_AVG:
 902    case BRW_OPCODE_DP2:
 903    case BRW_OPCODE_DP3:
 904    case BRW_OPCODE_DP4:
 905    case BRW_OPCODE_DPH:
 906    case BRW_OPCODE_F16TO32:
 907    case BRW_OPCODE_F32TO16:
 908    case BRW_OPCODE_LINE:
 909    case BRW_OPCODE_LRP:
 910    case BRW_OPCODE_MAC:
 911    case BRW_OPCODE_MAD:
 912    case BRW_OPCODE_MATH:
 913    case BRW_OPCODE_MOV:
 914    case BRW_OPCODE_MUL:
 915    case SHADER_OPCODE_MULH:
 916    case BRW_OPCODE_PLN:
 917    case BRW_OPCODE_RNDD:
 918    case BRW_OPCODE_RNDE:
 919    case BRW_OPCODE_RNDU:
 920    case BRW_OPCODE_RNDZ:
 921    case BRW_OPCODE_SEL:
 922    case BRW_OPCODE_SHL:
 923    case BRW_OPCODE_SHR:
 924    case FS_OPCODE_LINTERP:
 925    case SHADER_OPCODE_COS:
 926    case SHADER_OPCODE_EXP2:
 927    case SHADER_OPCODE_LOG2:
 928    case SHADER_OPCODE_POW:
 929    case SHADER_OPCODE_RCP:
 930    case SHADER_OPCODE_RSQ:
 931    case SHADER_OPCODE_SIN:
 932    case SHADER_OPCODE_SQRT:
 933       return true;
 934    default:
 935       return false;
 936    }
 937 }
 938
 939 bool
 940 backend_instruction::can_do_cmod() const
 941 {
 942    switch (opcode) {
 943    case BRW_OPCODE_ADD:
 944    case BRW_OPCODE_ADDC:
 945    case BRW_OPCODE_AND:
 946    case BRW_OPCODE_ASR:
 947    case BRW_OPCODE_AVG:
 948    case BRW_OPCODE_CMP:
 949    case BRW_OPCODE_CMPN:
 950    case BRW_OPCODE_DP2:
 951    case BRW_OPCODE_DP3:
 952    case BRW_OPCODE_DP4:
 953    case BRW_OPCODE_DPH:
 954    case BRW_OPCODE_F16TO32:
 955    case BRW_OPCODE_F32TO16:
 956    case BRW_OPCODE_FRC:
 957    case BRW_OPCODE_LINE:
 958    case BRW_OPCODE_LRP:
 959    case BRW_OPCODE_LZD:
 960    case BRW_OPCODE_MAC:
 961    case BRW_OPCODE_MACH:
 962    case BRW_OPCODE_MAD:
 963    case BRW_OPCODE_MOV:
 964    case BRW_OPCODE_MUL:
 965    case BRW_OPCODE_NOT:
 966    case BRW_OPCODE_OR:
 967    case BRW_OPCODE_PLN:
 968    case BRW_OPCODE_RNDD:
 969    case BRW_OPCODE_RNDE:
 970    case BRW_OPCODE_RNDU:
 971    case BRW_OPCODE_RNDZ:
 972    case BRW_OPCODE_SAD2:
 973    case BRW_OPCODE_SADA2:
 974    case BRW_OPCODE_SHL:
 975    case BRW_OPCODE_SHR:
 976    case BRW_OPCODE_SUBB:
 977    case BRW_OPCODE_XOR:
 978    case FS_OPCODE_CINTERP:
 979    case FS_OPCODE_LINTERP:
 980       return true;
 981    default:
 982       return false;
 983    }
 984 }
 985
 986 bool
 987 backend_instruction::reads_accumulator_implicitly() const
 988 {
 989    switch (opcode) {
 990    case BRW_OPCODE_MAC:
 991    case BRW_OPCODE_MACH:
 992    case BRW_OPCODE_SADA2:
 993       return true;
 994    default:
 995       return false;
 996    }
 997 }
 998
 999 bool
1000 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1001 {
1002    return writes_accumulator ||
1003           (devinfo->gen < 6 &&
1004            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1005             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1006              opcode != FS_OPCODE_CINTERP)));
1007 }
1008
1009 bool
1010 backend_instruction::has_side_effects() const
1011 {
1012    switch (opcode) {
1013    case SHADER_OPCODE_UNTYPED_ATOMIC:
1014    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1015    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1016    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1017    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1018    case SHADER_OPCODE_TYPED_ATOMIC:
1019    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1020    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1021    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1022    case SHADER_OPCODE_MEMORY_FENCE:
1023    case SHADER_OPCODE_URB_WRITE_SIMD8:
1024    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1025    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1026    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1027    case FS_OPCODE_FB_WRITE:
1028    case FS_OPCODE_FB_WRITE_LOGICAL:
1029    case SHADER_OPCODE_BARRIER:
1030    case TCS_OPCODE_URB_WRITE:
1031    case TCS_OPCODE_RELEASE_INPUT:
1032       return true;
1033    default:
1034       return false;
1035    }
1036 }
1037
1038 bool
1039 backend_instruction::is_volatile() const
1040 {
1041    switch (opcode) {
1042    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1043    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1044    case SHADER_OPCODE_TYPED_SURFACE_READ:
1045    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1046    case SHADER_OPCODE_URB_READ_SIMD8:
1047    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1048    case VEC4_OPCODE_URB_READ:
1049       return true;
1050    default:
1051       return false;
1052    }
1053 }
1054
1055 #ifndef NDEBUG
1056 static bool
1057 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1058 {
1059    bool found = false;
1060    foreach_inst_in_block (backend_instruction, i, block) {
1061       if (inst == i) {
1062          found = true;
1063       }
1064    }
1065    return found;
1066 }
1067 #endif
1068
1069 static void
1070 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1071 {
1072    for (bblock_t *block_iter = start_block->next();
1073         block_iter;
1074         block_iter = block_iter->next()) {
1075       block_iter->start_ip += ip_adjustment;
1076       block_iter->end_ip += ip_adjustment;
1077    }
1078 }
1079
1080 void
1081 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1082 {
1083    assert(this != inst);
1084
1085    if (!this->is_head_sentinel())
1086       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1087
1088    block->end_ip++;
1089
1090    adjust_later_block_ips(block, 1);
1091
1092    exec_node::insert_after(inst);
1093 }
1094
1095 void
1096 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1097 {
1098    assert(this != inst);
1099
1100    if (!this->is_tail_sentinel())
1101       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1102
1103    block->end_ip++;
1104
1105    adjust_later_block_ips(block, 1);
1106
1107    exec_node::insert_before(inst);
1108 }
1109
1110 void
1111 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1112 {
1113    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1114
1115    unsigned num_inst = list->length();
1116
1117    block->end_ip += num_inst;
1118
1119    adjust_later_block_ips(block, num_inst);
1120
1121    exec_node::insert_before(list);
1122 }
1123
1124 void
1125 backend_instruction::remove(bblock_t *block)
1126 {
1127    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1128
1129    adjust_later_block_ips(block, -1);
1130
1131    if (block->start_ip == block->end_ip) {
1132       block->cfg->remove_block(block);
1133    } else {
1134       block->end_ip--;
1135    }
1136
1137    exec_node::remove();
1138 }
1139
1140 void
1141 backend_shader::dump_instructions()
1142 {
1143    dump_instructions(NULL);
1144 }
1145
1146 void
1147 backend_shader::dump_instructions(const char *name)
1148 {
1149    FILE *file = stderr;
1150    if (name && geteuid() != 0) {
1151       file = fopen(name, "w");
1152       if (!file)
1153          file = stderr;
1154    }
1155
1156    if (cfg) {
1157       int ip = 0;
1158       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1159          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1160             fprintf(file, "%4d: ", ip++);
1161          dump_instruction(inst, file);
1162       }
1163    } else {
1164       int ip = 0;
1165       foreach_in_list(backend_instruction, inst, &instructions) {
1166          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1167             fprintf(file, "%4d: ", ip++);
1168          dump_instruction(inst, file);
1169       }
1170    }
1171
1172    if (file != stderr) {
1173       fclose(file);
1174    }
1175 }
1176
1177 void
1178 backend_shader::calculate_cfg()
1179 {
1180    if (this->cfg)
1181       return;
1182    cfg = new(mem_ctx) cfg_t(&this->instructions);
1183 }
1184
1185 /**
1186  * Sets up the starting offsets for the groups of binding table entries
1187  * commong to all pipeline stages.
1188  *
1189  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1190  * unused but also make sure that addition of small offsets to them will
1191  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1192  */
1193 uint32_t
1194 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1195                                         const struct gen_device_info *devinfo,
1196                                         const struct gl_shader_program *shader_prog,
1197                                         const struct gl_program *prog,
1198                                         struct brw_stage_prog_data *stage_prog_data,
1199                                         uint32_t next_binding_table_offset)
1200 {
1201    const struct gl_linked_shader *shader = NULL;
1202    int num_textures = util_last_bit(prog->SamplersUsed);
1203
1204    if (shader_prog)
1205       shader = shader_prog->_LinkedShaders[stage];
1206
1207    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1208    next_binding_table_offset += num_textures;
1209
1210    if (shader) {
1211       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1212       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1213       next_binding_table_offset += shader->NumUniformBlocks;
1214
1215       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1216       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1217       next_binding_table_offset += shader->NumShaderStorageBlocks;
1218    } else {
1219       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1220       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1221    }
1222
1223    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1224       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1225       next_binding_table_offset++;
1226    } else {
1227       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1228    }
1229
1230    if (prog->nir->info->uses_texture_gather) {
1231       if (devinfo->gen >= 8) {
1232          stage_prog_data->binding_table.gather_texture_start =
1233             stage_prog_data->binding_table.texture_start;
1234       } else {
1235          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1236          next_binding_table_offset += num_textures;
1237       }
1238    } else {
1239       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1240    }
1241
1242    if (prog->info.num_abos) {
1243       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1244       next_binding_table_offset += prog->info.num_abos;
1245    } else {
1246       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1247    }
1248
1249    if (prog->info.num_images) {
1250       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1251       next_binding_table_offset += prog->info.num_images;
1252    } else {
1253       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1254    }
1255
1256    /* This may or may not be used depending on how the compile goes. */
1257    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1258    next_binding_table_offset++;
1259
1260    /* Plane 0 is just the regular texture section */
1261    stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
1262
1263    stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
1264    next_binding_table_offset += num_textures;
1265
1266    stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
1267    next_binding_table_offset += num_textures;
1268
1269    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1270
1271    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1272    return next_binding_table_offset;
1273 }
1274
1275 static void
1276 setup_vec4_uniform_value(const gl_constant_value **params,
1277                          const gl_constant_value *values,
1278                          unsigned n)
1279 {
1280    static const gl_constant_value zero = { 0 };
1281
1282    for (unsigned i = 0; i < n; ++i)
1283       params[i] = &values[i];
1284
1285    for (unsigned i = n; i < 4; ++i)
1286       params[i] = &zero;
1287 }
1288
1289 void
1290 brw_setup_image_uniform_values(gl_shader_stage stage,
1291                                struct brw_stage_prog_data *stage_prog_data,
1292                                unsigned param_start_index,
1293                                const gl_uniform_storage *storage)
1294 {
1295    const gl_constant_value **param =
1296       &stage_prog_data->param[param_start_index];
1297
1298    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1299       const unsigned image_idx = storage->opaque[stage].index + i;
1300       const brw_image_param *image_param =
1301          &stage_prog_data->image_param[image_idx];
1302
1303       /* Upload the brw_image_param structure.  The order is expected to match
1304        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1305        */
1306       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1307          (const gl_constant_value *)&image_param->surface_idx, 1);
1308       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1309          (const gl_constant_value *)image_param->offset, 2);
1310       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1311          (const gl_constant_value *)image_param->size, 3);
1312       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1313          (const gl_constant_value *)image_param->stride, 4);
1314       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1315          (const gl_constant_value *)image_param->tiling, 3);
1316       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1317          (const gl_constant_value *)image_param->swizzling, 2);
1318       param += BRW_IMAGE_PARAM_SIZE;
1319
1320       brw_mark_surface_used(
1321          stage_prog_data,
1322          stage_prog_data->binding_table.image_start + image_idx);
1323    }
1324 }
1325
1326 /**
1327  * Decide which set of clip planes should be used when clipping via
1328  * gl_Position or gl_ClipVertex.
1329  */
1330 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1331 {
1332    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1333       /* There is currently a GLSL vertex shader, so clip according to GLSL
1334        * rules, which means compare gl_ClipVertex (or gl_Position, if
1335        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1336        * that were stored in EyeUserPlane at the time the clip planes were
1337        * specified.
1338        */
1339       return ctx->Transform.EyeUserPlane;
1340    } else {
1341       /* Either we are using fixed function or an ARB vertex program.  In
1342        * either case the clip planes are going to be compared against
1343        * gl_Position (which is in clip coordinates) so we have to clip using
1344        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1345        * core.
1346        */
1347       return ctx->Transform._ClipUserPlane;
1348    }
1349 }
1350
1351 extern "C" const unsigned *
1352 brw_compile_tes(const struct brw_compiler *compiler,
1353                 void *log_data,
1354                 void *mem_ctx,
1355                 const struct brw_tes_prog_key *key,
1356                 struct brw_tes_prog_data *prog_data,
1357                 const nir_shader *src_shader,
1358                 struct gl_shader_program *shader_prog,
1359                 int shader_time_index,
1360                 unsigned *final_assembly_size,
1361                 char **error_str)
1362 {
1363    const struct gen_device_info *devinfo = compiler->devinfo;
1364    struct gl_linked_shader *shader =
1365       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1366    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1367
1368    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1369    nir->info->inputs_read = key->inputs_read;
1370    nir->info->patch_inputs_read = key->patch_inputs_read;
1371
1372    struct brw_vue_map input_vue_map;
1373    brw_compute_tess_vue_map(&input_vue_map, nir->info->inputs_read,
1374                             nir->info->patch_inputs_read);
1375
1376    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1377    brw_nir_lower_tes_inputs(nir, &input_vue_map);
1378    brw_nir_lower_vue_outputs(nir, is_scalar);
1379    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1380
1381    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1382                        nir->info->outputs_written,
1383                        nir->info->separate_shader);
1384
1385    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1386
1387    assert(output_size_bytes >= 1);
1388    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1389       if (error_str)
1390          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1391       return NULL;
1392    }
1393
1394    prog_data->base.clip_distance_mask =
1395       ((1 << nir->info->clip_distance_array_size) - 1);
1396    prog_data->base.cull_distance_mask =
1397       ((1 << nir->info->cull_distance_array_size) - 1) <<
1398       nir->info->clip_distance_array_size;
1399
1400    /* URB entry sizes are stored as a multiple of 64 bytes. */
1401    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1402
1403    bool need_patch_header = nir->info->system_values_read &
1404       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1405        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1406
1407    /* The TES will pull most inputs using URB read messages.
1408     *
1409     * However, we push the patch header for TessLevel factors when required,
1410     * as it's a tiny amount of extra data.
1411     */
1412    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1413
1414    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1415       fprintf(stderr, "TES Input ");
1416       brw_print_vue_map(stderr, &input_vue_map);
1417       fprintf(stderr, "TES Output ");
1418       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1419    }
1420
1421    if (is_scalar) {
1422       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1423                    &prog_data->base.base, shader->Program, nir, 8,
1424                    shader_time_index, &input_vue_map);
1425       if (!v.run_tes()) {
1426          if (error_str)
1427             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1428          return NULL;
1429       }
1430
1431       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1432       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1433
1434       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1435                      &prog_data->base.base, v.promoted_constants, false,
1436                      MESA_SHADER_TESS_EVAL);
1437       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1438          g.enable_debug(ralloc_asprintf(mem_ctx,
1439                                         "%s tessellation evaluation shader %s",
1440                                         nir->info->label ? nir->info->label
1441                                                         : "unnamed",
1442                                         nir->info->name));
1443       }
1444
1445       g.generate_code(v.cfg, 8);
1446
1447       return g.get_assembly(final_assembly_size);
1448    } else {
1449       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1450                               nir, mem_ctx, shader_time_index);
1451       if (!v.run()) {
1452          if (error_str)
1453             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1454          return NULL;
1455       }
1456
1457       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1458          v.dump_instructions();
1459
1460       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1461                                         &prog_data->base, v.cfg,
1462                                         final_assembly_size);
1463    }
1464 }