src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 struct gl_shader *
  36 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  37 {
  38    struct brw_shader *shader;
  39
  40    shader = rzalloc(NULL, struct brw_shader);
  41    if (shader) {
  42       shader->base.Type = type;
  43       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  44       shader->base.Name = name;
  45       _mesa_init_shader(ctx, &shader->base);
  46    }
  47
  48    return &shader->base;
  49 }
  50
  51 /**
  52  * Performs a compile of the shader stages even when we don't know
  53  * what non-orthogonal state will be set, in the hope that it reflects
  54  * the eventual NOS used, and thus allows us to produce link failures.
  55  */
  56 static bool
  57 brw_shader_precompile(struct gl_context *ctx,
  58                       struct gl_shader_program *sh_prog)
  59 {
  60    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  61    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  62    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  63
  64    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  65       return false;
  66
  67    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  68       return false;
  69
  70    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  71       return false;
  72
  73    return true;
  74 }
  75
  76 static inline bool
  77 is_scalar_shader_stage(struct brw_context *brw, int stage)
  78 {
  79    switch (stage) {
  80    case MESA_SHADER_FRAGMENT:
  81       return true;
  82    case MESA_SHADER_VERTEX:
  83       return brw->scalar_vs;
  84    default:
  85       return false;
  86    }
  87 }
  88
  89 static void
  90 brw_lower_packing_builtins(struct brw_context *brw,
  91                            gl_shader_stage shader_type,
  92                            exec_list *ir)
  93 {
  94    int ops = LOWER_PACK_SNORM_2x16
  95            | LOWER_UNPACK_SNORM_2x16
  96            | LOWER_PACK_UNORM_2x16
  97            | LOWER_UNPACK_UNORM_2x16;
  98
  99    if (is_scalar_shader_stage(brw, shader_type)) {
 100       ops |= LOWER_UNPACK_UNORM_4x8
 101            | LOWER_UNPACK_SNORM_4x8
 102            | LOWER_PACK_UNORM_4x8
 103            | LOWER_PACK_SNORM_4x8;
 104    }
 105
 106    if (brw->gen >= 7) {
 107       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 108        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 109        * lowering is needed. For SOA code, the Half2x16 ops must be
 110        * scalarized.
 111        */
 112       if (is_scalar_shader_stage(brw, shader_type)) {
 113          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 114              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 115       }
 116    } else {
 117       ops |= LOWER_PACK_HALF_2x16
 118           |  LOWER_UNPACK_HALF_2x16;
 119    }
 120
 121    lower_packing_builtins(ir, ops);
 122 }
 123
 124 static void
 125 process_glsl_ir(struct brw_context *brw,
 126                 struct gl_shader_program *shader_prog,
 127                 struct gl_shader *shader)
 128 {
 129    struct gl_context *ctx = &brw->ctx;
 130    const struct gl_shader_compiler_options *options =
 131       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 132
 133    /* Temporary memory context for any new IR. */
 134    void *mem_ctx = ralloc_context(NULL);
 135
 136    ralloc_adopt(mem_ctx, shader->ir);
 137
 138    /* lower_packing_builtins() inserts arithmetic instructions, so it
 139     * must precede lower_instructions().
 140     */
 141    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 142    do_mat_op_to_vec(shader->ir);
 143    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 144    lower_instructions(shader->ir,
 145                       MOD_TO_FLOOR |
 146                       DIV_TO_MUL_RCP |
 147                       SUB_TO_ADD_NEG |
 148                       EXP_TO_EXP2 |
 149                       LOG_TO_LOG2 |
 150                       bitfield_insert |
 151                       LDEXP_TO_ARITH);
 152
 153    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 154     * if-statements need to be flattened.
 155     */
 156    if (brw->gen < 6)
 157       lower_if_to_cond_assign(shader->ir, 16);
 158
 159    do_lower_texture_projection(shader->ir);
 160    brw_lower_texture_gradients(brw, shader->ir);
 161    do_vec_index_to_cond_assign(shader->ir);
 162    lower_vector_insert(shader->ir, true);
 163    if (options->NirOptions == NULL)
 164       brw_do_cubemap_normalize(shader->ir);
 165    lower_offset_arrays(shader->ir);
 166    brw_do_lower_unnormalized_offset(shader->ir);
 167    lower_noise(shader->ir);
 168    lower_quadop_vector(shader->ir, false);
 169
 170    bool lowered_variable_indexing =
 171       lower_variable_index_to_cond_assign(shader->ir,
 172                                           options->EmitNoIndirectInput,
 173                                           options->EmitNoIndirectOutput,
 174                                           options->EmitNoIndirectTemp,
 175                                           options->EmitNoIndirectUniform);
 176
 177    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 178       perf_debug("Unsupported form of variable indexing in FS; falling "
 179                  "back to very inefficient code generation\n");
 180    }
 181
 182    lower_ubo_reference(shader, shader->ir);
 183
 184    bool progress;
 185    do {
 186       progress = false;
 187
 188       if (is_scalar_shader_stage(brw, shader->Stage)) {
 189          brw_do_channel_expressions(shader->ir);
 190          brw_do_vector_splitting(shader->ir);
 191       }
 192
 193       progress = do_lower_jumps(shader->ir, true, true,
 194                                 true, /* main return */
 195                                 false, /* continue */
 196                                 false /* loops */
 197                                 ) || progress;
 198
 199       progress = do_common_optimization(shader->ir, true, true,
 200                                         options, ctx->Const.NativeIntegers) || progress;
 201    } while (progress);
 202
 203    if (options->NirOptions != NULL)
 204       lower_output_reads(shader->ir);
 205
 206    validate_ir_tree(shader->ir);
 207
 208    /* Now that we've finished altering the linked IR, reparent any live IR back
 209     * to the permanent memory context, and free the temporary one (discarding any
 210     * junk we optimized away).
 211     */
 212    reparent_ir(shader->ir, shader->ir);
 213    ralloc_free(mem_ctx);
 214
 215    if (ctx->_Shader->Flags & GLSL_DUMP) {
 216       fprintf(stderr, "\n");
 217       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 218               _mesa_shader_stage_to_string(shader->Stage),
 219               shader_prog->Name);
 220       _mesa_print_ir(stderr, shader->ir, NULL);
 221       fprintf(stderr, "\n");
 222    }
 223 }
 224
 225 GLboolean
 226 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 227 {
 228    struct brw_context *brw = brw_context(ctx);
 229    unsigned int stage;
 230
 231    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 232       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 233       const struct gl_shader_compiler_options *options =
 234          &ctx->Const.ShaderCompilerOptions[stage];
 235
 236       if (!shader)
 237          continue;
 238
 239       struct gl_program *prog =
 240          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 241                                 shader->Name);
 242       if (!prog)
 243         return false;
 244       prog->Parameters = _mesa_new_parameter_list();
 245
 246       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 247
 248       process_glsl_ir(brw, shProg, shader);
 249
 250       /* Make a pass over the IR to add state references for any built-in
 251        * uniforms that are used.  This has to be done now (during linking).
 252        * Code generation doesn't happen until the first time this shader is
 253        * used for rendering.  Waiting until then to generate the parameters is
 254        * too late.  At that point, the values for the built-in uniforms won't
 255        * get sent to the shader.
 256        */
 257       foreach_in_list(ir_instruction, node, shader->ir) {
 258          ir_variable *var = node->as_variable();
 259
 260          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 261              || (strncmp(var->name, "gl_", 3) != 0))
 262             continue;
 263
 264          const ir_state_slot *const slots = var->get_state_slots();
 265          assert(slots != NULL);
 266
 267          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 268             _mesa_add_state_reference(prog->Parameters,
 269                                       (gl_state_index *) slots[i].tokens);
 270          }
 271       }
 272
 273       do_set_program_inouts(shader->ir, prog, shader->Stage);
 274
 275       prog->SamplersUsed = shader->active_samplers;
 276       prog->ShadowSamplers = shader->shadow_samplers;
 277       _mesa_update_shader_textures_used(shProg, prog);
 278
 279       _mesa_reference_program(ctx, &shader->Program, prog);
 280
 281       brw_add_texrect_params(prog);
 282
 283       if (options->NirOptions)
 284          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 285
 286       _mesa_reference_program(ctx, &prog, NULL);
 287    }
 288
 289    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 290       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 291          const struct gl_shader *sh = shProg->Shaders[i];
 292          if (!sh)
 293             continue;
 294
 295          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 296                  _mesa_shader_stage_to_string(sh->Stage),
 297                  i, shProg->Name);
 298          fprintf(stderr, "%s", sh->Source);
 299          fprintf(stderr, "\n");
 300       }
 301    }
 302
 303    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 304       return false;
 305
 306    return true;
 307 }
 308
 309
 310 enum brw_reg_type
 311 brw_type_for_base_type(const struct glsl_type *type)
 312 {
 313    switch (type->base_type) {
 314    case GLSL_TYPE_FLOAT:
 315       return BRW_REGISTER_TYPE_F;
 316    case GLSL_TYPE_INT:
 317    case GLSL_TYPE_BOOL:
 318       return BRW_REGISTER_TYPE_D;
 319    case GLSL_TYPE_UINT:
 320       return BRW_REGISTER_TYPE_UD;
 321    case GLSL_TYPE_ARRAY:
 322       return brw_type_for_base_type(type->fields.array);
 323    case GLSL_TYPE_STRUCT:
 324    case GLSL_TYPE_SAMPLER:
 325    case GLSL_TYPE_ATOMIC_UINT:
 326       /* These should be overridden with the type of the member when
 327        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 328        * way to trip up if we don't.
 329        */
 330       return BRW_REGISTER_TYPE_UD;
 331    case GLSL_TYPE_IMAGE:
 332       return BRW_REGISTER_TYPE_UD;
 333    case GLSL_TYPE_VOID:
 334    case GLSL_TYPE_ERROR:
 335    case GLSL_TYPE_INTERFACE:
 336    case GLSL_TYPE_DOUBLE:
 337       unreachable("not reached");
 338    }
 339
 340    return BRW_REGISTER_TYPE_F;
 341 }
 342
 343 enum brw_conditional_mod
 344 brw_conditional_for_comparison(unsigned int op)
 345 {
 346    switch (op) {
 347    case ir_binop_less:
 348       return BRW_CONDITIONAL_L;
 349    case ir_binop_greater:
 350       return BRW_CONDITIONAL_G;
 351    case ir_binop_lequal:
 352       return BRW_CONDITIONAL_LE;
 353    case ir_binop_gequal:
 354       return BRW_CONDITIONAL_GE;
 355    case ir_binop_equal:
 356    case ir_binop_all_equal: /* same as equal for scalars */
 357       return BRW_CONDITIONAL_Z;
 358    case ir_binop_nequal:
 359    case ir_binop_any_nequal: /* same as nequal for scalars */
 360       return BRW_CONDITIONAL_NZ;
 361    default:
 362       unreachable("not reached: bad operation for comparison");
 363    }
 364 }
 365
 366 uint32_t
 367 brw_math_function(enum opcode op)
 368 {
 369    switch (op) {
 370    case SHADER_OPCODE_RCP:
 371       return BRW_MATH_FUNCTION_INV;
 372    case SHADER_OPCODE_RSQ:
 373       return BRW_MATH_FUNCTION_RSQ;
 374    case SHADER_OPCODE_SQRT:
 375       return BRW_MATH_FUNCTION_SQRT;
 376    case SHADER_OPCODE_EXP2:
 377       return BRW_MATH_FUNCTION_EXP;
 378    case SHADER_OPCODE_LOG2:
 379       return BRW_MATH_FUNCTION_LOG;
 380    case SHADER_OPCODE_POW:
 381       return BRW_MATH_FUNCTION_POW;
 382    case SHADER_OPCODE_SIN:
 383       return BRW_MATH_FUNCTION_SIN;
 384    case SHADER_OPCODE_COS:
 385       return BRW_MATH_FUNCTION_COS;
 386    case SHADER_OPCODE_INT_QUOTIENT:
 387       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 388    case SHADER_OPCODE_INT_REMAINDER:
 389       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 390    default:
 391       unreachable("not reached: unknown math function");
 392    }
 393 }
 394
 395 uint32_t
 396 brw_texture_offset(int *offsets, unsigned num_components)
 397 {
 398    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 399
 400    /* Combine all three offsets into a single unsigned dword:
 401     *
 402     *    bits 11:8 - U Offset (X component)
 403     *    bits  7:4 - V Offset (Y component)
 404     *    bits  3:0 - R Offset (Z component)
 405     */
 406    unsigned offset_bits = 0;
 407    for (unsigned i = 0; i < num_components; i++) {
 408       const unsigned shift = 4 * (2 - i);
 409       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 410    }
 411    return offset_bits;
 412 }
 413
 414 const char *
 415 brw_instruction_name(enum opcode op)
 416 {
 417    switch (op) {
 418    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 419       assert(opcode_descs[op].name);
 420       return opcode_descs[op].name;
 421    case FS_OPCODE_FB_WRITE:
 422       return "fb_write";
 423    case FS_OPCODE_BLORP_FB_WRITE:
 424       return "blorp_fb_write";
 425    case FS_OPCODE_REP_FB_WRITE:
 426       return "rep_fb_write";
 427
 428    case SHADER_OPCODE_RCP:
 429       return "rcp";
 430    case SHADER_OPCODE_RSQ:
 431       return "rsq";
 432    case SHADER_OPCODE_SQRT:
 433       return "sqrt";
 434    case SHADER_OPCODE_EXP2:
 435       return "exp2";
 436    case SHADER_OPCODE_LOG2:
 437       return "log2";
 438    case SHADER_OPCODE_POW:
 439       return "pow";
 440    case SHADER_OPCODE_INT_QUOTIENT:
 441       return "int_quot";
 442    case SHADER_OPCODE_INT_REMAINDER:
 443       return "int_rem";
 444    case SHADER_OPCODE_SIN:
 445       return "sin";
 446    case SHADER_OPCODE_COS:
 447       return "cos";
 448
 449    case SHADER_OPCODE_TEX:
 450       return "tex";
 451    case SHADER_OPCODE_TXD:
 452       return "txd";
 453    case SHADER_OPCODE_TXF:
 454       return "txf";
 455    case SHADER_OPCODE_TXL:
 456       return "txl";
 457    case SHADER_OPCODE_TXS:
 458       return "txs";
 459    case FS_OPCODE_TXB:
 460       return "txb";
 461    case SHADER_OPCODE_TXF_CMS:
 462       return "txf_cms";
 463    case SHADER_OPCODE_TXF_UMS:
 464       return "txf_ums";
 465    case SHADER_OPCODE_TXF_MCS:
 466       return "txf_mcs";
 467    case SHADER_OPCODE_LOD:
 468       return "lod";
 469    case SHADER_OPCODE_TG4:
 470       return "tg4";
 471    case SHADER_OPCODE_TG4_OFFSET:
 472       return "tg4_offset";
 473    case SHADER_OPCODE_SHADER_TIME_ADD:
 474       return "shader_time_add";
 475
 476    case SHADER_OPCODE_UNTYPED_ATOMIC:
 477       return "untyped_atomic";
 478    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 479       return "untyped_surface_read";
 480
 481    case SHADER_OPCODE_LOAD_PAYLOAD:
 482       return "load_payload";
 483
 484    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 485       return "gen4_scratch_read";
 486    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 487       return "gen4_scratch_write";
 488    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 489       return "gen7_scratch_read";
 490    case SHADER_OPCODE_URB_WRITE_SIMD8:
 491       return "gen8_urb_write_simd8";
 492
 493    case VEC4_OPCODE_MOV_BYTES:
 494       return "mov_bytes";
 495    case VEC4_OPCODE_PACK_BYTES:
 496       return "pack_bytes";
 497    case VEC4_OPCODE_UNPACK_UNIFORM:
 498       return "unpack_uniform";
 499
 500    case FS_OPCODE_DDX_COARSE:
 501       return "ddx_coarse";
 502    case FS_OPCODE_DDX_FINE:
 503       return "ddx_fine";
 504    case FS_OPCODE_DDY_COARSE:
 505       return "ddy_coarse";
 506    case FS_OPCODE_DDY_FINE:
 507       return "ddy_fine";
 508
 509    case FS_OPCODE_CINTERP:
 510       return "cinterp";
 511    case FS_OPCODE_LINTERP:
 512       return "linterp";
 513
 514    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 515       return "uniform_pull_const";
 516    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 517       return "uniform_pull_const_gen7";
 518    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 519       return "varying_pull_const";
 520    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 521       return "varying_pull_const_gen7";
 522
 523    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 524       return "mov_dispatch_to_flags";
 525    case FS_OPCODE_DISCARD_JUMP:
 526       return "discard_jump";
 527
 528    case FS_OPCODE_SET_OMASK:
 529       return "set_omask";
 530    case FS_OPCODE_SET_SAMPLE_ID:
 531       return "set_sample_id";
 532    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 533       return "set_simd4x2_offset";
 534
 535    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 536       return "pack_half_2x16_split";
 537    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 538       return "unpack_half_2x16_split_x";
 539    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 540       return "unpack_half_2x16_split_y";
 541
 542    case FS_OPCODE_PLACEHOLDER_HALT:
 543       return "placeholder_halt";
 544
 545    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 546       return "interp_centroid";
 547    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 548       return "interp_sample";
 549    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 550       return "interp_shared_offset";
 551    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 552       return "interp_per_slot_offset";
 553
 554    case VS_OPCODE_URB_WRITE:
 555       return "vs_urb_write";
 556    case VS_OPCODE_PULL_CONSTANT_LOAD:
 557       return "pull_constant_load";
 558    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 559       return "pull_constant_load_gen7";
 560
 561    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 562       return "set_simd4x2_header_gen9";
 563
 564    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 565       return "unpack_flags_simd4x2";
 566
 567    case GS_OPCODE_URB_WRITE:
 568       return "gs_urb_write";
 569    case GS_OPCODE_URB_WRITE_ALLOCATE:
 570       return "gs_urb_write_allocate";
 571    case GS_OPCODE_THREAD_END:
 572       return "gs_thread_end";
 573    case GS_OPCODE_SET_WRITE_OFFSET:
 574       return "set_write_offset";
 575    case GS_OPCODE_SET_VERTEX_COUNT:
 576       return "set_vertex_count";
 577    case GS_OPCODE_SET_DWORD_2:
 578       return "set_dword_2";
 579    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 580       return "prepare_channel_masks";
 581    case GS_OPCODE_SET_CHANNEL_MASKS:
 582       return "set_channel_masks";
 583    case GS_OPCODE_GET_INSTANCE_ID:
 584       return "get_instance_id";
 585    case GS_OPCODE_FF_SYNC:
 586       return "ff_sync";
 587    case GS_OPCODE_SET_PRIMITIVE_ID:
 588       return "set_primitive_id";
 589    case GS_OPCODE_SVB_WRITE:
 590       return "gs_svb_write";
 591    case GS_OPCODE_SVB_SET_DST_INDEX:
 592       return "gs_svb_set_dst_index";
 593    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 594       return "gs_ff_sync_set_primitives";
 595    }
 596
 597    unreachable("not reached");
 598 }
 599
 600 bool
 601 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 602 {
 603    union {
 604       unsigned ud;
 605       int d;
 606       float f;
 607    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 608
 609    switch (type) {
 610    case BRW_REGISTER_TYPE_UD:
 611    case BRW_REGISTER_TYPE_D:
 612    case BRW_REGISTER_TYPE_UQ:
 613    case BRW_REGISTER_TYPE_Q:
 614       /* Nothing to do. */
 615       return false;
 616    case BRW_REGISTER_TYPE_UW:
 617       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 618       break;
 619    case BRW_REGISTER_TYPE_W:
 620       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 621       break;
 622    case BRW_REGISTER_TYPE_F:
 623       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 624       break;
 625    case BRW_REGISTER_TYPE_UB:
 626    case BRW_REGISTER_TYPE_B:
 627       unreachable("no UB/B immediates");
 628    case BRW_REGISTER_TYPE_V:
 629    case BRW_REGISTER_TYPE_UV:
 630    case BRW_REGISTER_TYPE_VF:
 631       unreachable("unimplemented: saturate vector immediate");
 632    case BRW_REGISTER_TYPE_DF:
 633    case BRW_REGISTER_TYPE_HF:
 634       unreachable("unimplemented: saturate DF/HF immediate");
 635    }
 636
 637    if (imm.ud != sat_imm.ud) {
 638       reg->dw1.ud = sat_imm.ud;
 639       return true;
 640    }
 641    return false;
 642 }
 643
 644 bool
 645 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 646 {
 647    switch (type) {
 648    case BRW_REGISTER_TYPE_D:
 649    case BRW_REGISTER_TYPE_UD:
 650       reg->dw1.d = -reg->dw1.d;
 651       return true;
 652    case BRW_REGISTER_TYPE_W:
 653    case BRW_REGISTER_TYPE_UW:
 654       reg->dw1.d = -(int16_t)reg->dw1.ud;
 655       return true;
 656    case BRW_REGISTER_TYPE_F:
 657       reg->dw1.f = -reg->dw1.f;
 658       return true;
 659    case BRW_REGISTER_TYPE_VF:
 660       reg->dw1.ud ^= 0x80808080;
 661       return true;
 662    case BRW_REGISTER_TYPE_UB:
 663    case BRW_REGISTER_TYPE_B:
 664       unreachable("no UB/B immediates");
 665    case BRW_REGISTER_TYPE_UV:
 666    case BRW_REGISTER_TYPE_V:
 667       assert(!"unimplemented: negate UV/V immediate");
 668    case BRW_REGISTER_TYPE_UQ:
 669    case BRW_REGISTER_TYPE_Q:
 670       assert(!"unimplemented: negate UQ/Q immediate");
 671    case BRW_REGISTER_TYPE_DF:
 672    case BRW_REGISTER_TYPE_HF:
 673       assert(!"unimplemented: negate DF/HF immediate");
 674    }
 675
 676    return false;
 677 }
 678
 679 bool
 680 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 681 {
 682    switch (type) {
 683    case BRW_REGISTER_TYPE_D:
 684       reg->dw1.d = abs(reg->dw1.d);
 685       return true;
 686    case BRW_REGISTER_TYPE_W:
 687       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 688       return true;
 689    case BRW_REGISTER_TYPE_F:
 690       reg->dw1.f = fabsf(reg->dw1.f);
 691       return true;
 692    case BRW_REGISTER_TYPE_VF:
 693       reg->dw1.ud &= ~0x80808080;
 694       return true;
 695    case BRW_REGISTER_TYPE_UB:
 696    case BRW_REGISTER_TYPE_B:
 697       unreachable("no UB/B immediates");
 698    case BRW_REGISTER_TYPE_UQ:
 699    case BRW_REGISTER_TYPE_UD:
 700    case BRW_REGISTER_TYPE_UW:
 701    case BRW_REGISTER_TYPE_UV:
 702       /* Presumably the absolute value modifier on an unsigned source is a
 703        * nop, but it would be nice to confirm.
 704        */
 705       assert(!"unimplemented: abs unsigned immediate");
 706    case BRW_REGISTER_TYPE_V:
 707       assert(!"unimplemented: abs V immediate");
 708    case BRW_REGISTER_TYPE_Q:
 709       assert(!"unimplemented: abs Q immediate");
 710    case BRW_REGISTER_TYPE_DF:
 711    case BRW_REGISTER_TYPE_HF:
 712       assert(!"unimplemented: abs DF/HF immediate");
 713    }
 714
 715    return false;
 716 }
 717
 718 backend_visitor::backend_visitor(struct brw_context *brw,
 719                                  struct gl_shader_program *shader_prog,
 720                                  struct gl_program *prog,
 721                                  struct brw_stage_prog_data *stage_prog_data,
 722                                  gl_shader_stage stage)
 723    : brw(brw),
 724      ctx(&brw->ctx),
 725      shader(shader_prog ?
 726         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 727      shader_prog(shader_prog),
 728      prog(prog),
 729      stage_prog_data(stage_prog_data),
 730      cfg(NULL),
 731      stage(stage)
 732 {
 733    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 734    stage_name = _mesa_shader_stage_to_string(stage);
 735    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 736 }
 737
 738 bool
 739 backend_reg::is_zero() const
 740 {
 741    if (file != IMM)
 742       return false;
 743
 744    return fixed_hw_reg.dw1.d == 0;
 745 }
 746
 747 bool
 748 backend_reg::is_one() const
 749 {
 750    if (file != IMM)
 751       return false;
 752
 753    return type == BRW_REGISTER_TYPE_F
 754           ? fixed_hw_reg.dw1.f == 1.0
 755           : fixed_hw_reg.dw1.d == 1;
 756 }
 757
 758 bool
 759 backend_reg::is_negative_one() const
 760 {
 761    if (file != IMM)
 762       return false;
 763
 764    switch (type) {
 765    case BRW_REGISTER_TYPE_F:
 766       return fixed_hw_reg.dw1.f == -1.0;
 767    case BRW_REGISTER_TYPE_D:
 768       return fixed_hw_reg.dw1.d == -1;
 769    default:
 770       return false;
 771    }
 772 }
 773
 774 bool
 775 backend_reg::is_null() const
 776 {
 777    return file == HW_REG &&
 778           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 779           fixed_hw_reg.nr == BRW_ARF_NULL;
 780 }
 781
 782
 783 bool
 784 backend_reg::is_accumulator() const
 785 {
 786    return file == HW_REG &&
 787           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 788           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 789 }
 790
 791 bool
 792 backend_reg::in_range(const backend_reg &r, unsigned n) const
 793 {
 794    return (file == r.file &&
 795            reg == r.reg &&
 796            reg_offset >= r.reg_offset &&
 797            reg_offset < r.reg_offset + n);
 798 }
 799
 800 bool
 801 backend_instruction::is_commutative() const
 802 {
 803    switch (opcode) {
 804    case BRW_OPCODE_AND:
 805    case BRW_OPCODE_OR:
 806    case BRW_OPCODE_XOR:
 807    case BRW_OPCODE_ADD:
 808    case BRW_OPCODE_MUL:
 809       return true;
 810    case BRW_OPCODE_SEL:
 811       /* MIN and MAX are commutative. */
 812       if (conditional_mod == BRW_CONDITIONAL_GE ||
 813           conditional_mod == BRW_CONDITIONAL_L) {
 814          return true;
 815       }
 816       /* fallthrough */
 817    default:
 818       return false;
 819    }
 820 }
 821
 822 bool
 823 backend_instruction::is_3src() const
 824 {
 825    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 826 }
 827
 828 bool
 829 backend_instruction::is_tex() const
 830 {
 831    return (opcode == SHADER_OPCODE_TEX ||
 832            opcode == FS_OPCODE_TXB ||
 833            opcode == SHADER_OPCODE_TXD ||
 834            opcode == SHADER_OPCODE_TXF ||
 835            opcode == SHADER_OPCODE_TXF_CMS ||
 836            opcode == SHADER_OPCODE_TXF_UMS ||
 837            opcode == SHADER_OPCODE_TXF_MCS ||
 838            opcode == SHADER_OPCODE_TXL ||
 839            opcode == SHADER_OPCODE_TXS ||
 840            opcode == SHADER_OPCODE_LOD ||
 841            opcode == SHADER_OPCODE_TG4 ||
 842            opcode == SHADER_OPCODE_TG4_OFFSET);
 843 }
 844
 845 bool
 846 backend_instruction::is_math() const
 847 {
 848    return (opcode == SHADER_OPCODE_RCP ||
 849            opcode == SHADER_OPCODE_RSQ ||
 850            opcode == SHADER_OPCODE_SQRT ||
 851            opcode == SHADER_OPCODE_EXP2 ||
 852            opcode == SHADER_OPCODE_LOG2 ||
 853            opcode == SHADER_OPCODE_SIN ||
 854            opcode == SHADER_OPCODE_COS ||
 855            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 856            opcode == SHADER_OPCODE_INT_REMAINDER ||
 857            opcode == SHADER_OPCODE_POW);
 858 }
 859
 860 bool
 861 backend_instruction::is_control_flow() const
 862 {
 863    switch (opcode) {
 864    case BRW_OPCODE_DO:
 865    case BRW_OPCODE_WHILE:
 866    case BRW_OPCODE_IF:
 867    case BRW_OPCODE_ELSE:
 868    case BRW_OPCODE_ENDIF:
 869    case BRW_OPCODE_BREAK:
 870    case BRW_OPCODE_CONTINUE:
 871       return true;
 872    default:
 873       return false;
 874    }
 875 }
 876
 877 bool
 878 backend_instruction::can_do_source_mods() const
 879 {
 880    switch (opcode) {
 881    case BRW_OPCODE_ADDC:
 882    case BRW_OPCODE_BFE:
 883    case BRW_OPCODE_BFI1:
 884    case BRW_OPCODE_BFI2:
 885    case BRW_OPCODE_BFREV:
 886    case BRW_OPCODE_CBIT:
 887    case BRW_OPCODE_FBH:
 888    case BRW_OPCODE_FBL:
 889    case BRW_OPCODE_SUBB:
 890       return false;
 891    default:
 892       return true;
 893    }
 894 }
 895
 896 bool
 897 backend_instruction::can_do_saturate() const
 898 {
 899    switch (opcode) {
 900    case BRW_OPCODE_ADD:
 901    case BRW_OPCODE_ASR:
 902    case BRW_OPCODE_AVG:
 903    case BRW_OPCODE_DP2:
 904    case BRW_OPCODE_DP3:
 905    case BRW_OPCODE_DP4:
 906    case BRW_OPCODE_DPH:
 907    case BRW_OPCODE_F16TO32:
 908    case BRW_OPCODE_F32TO16:
 909    case BRW_OPCODE_LINE:
 910    case BRW_OPCODE_LRP:
 911    case BRW_OPCODE_MAC:
 912    case BRW_OPCODE_MACH:
 913    case BRW_OPCODE_MAD:
 914    case BRW_OPCODE_MATH:
 915    case BRW_OPCODE_MOV:
 916    case BRW_OPCODE_MUL:
 917    case BRW_OPCODE_PLN:
 918    case BRW_OPCODE_RNDD:
 919    case BRW_OPCODE_RNDE:
 920    case BRW_OPCODE_RNDU:
 921    case BRW_OPCODE_RNDZ:
 922    case BRW_OPCODE_SEL:
 923    case BRW_OPCODE_SHL:
 924    case BRW_OPCODE_SHR:
 925    case FS_OPCODE_LINTERP:
 926    case SHADER_OPCODE_COS:
 927    case SHADER_OPCODE_EXP2:
 928    case SHADER_OPCODE_LOG2:
 929    case SHADER_OPCODE_POW:
 930    case SHADER_OPCODE_RCP:
 931    case SHADER_OPCODE_RSQ:
 932    case SHADER_OPCODE_SIN:
 933    case SHADER_OPCODE_SQRT:
 934       return true;
 935    default:
 936       return false;
 937    }
 938 }
 939
 940 bool
 941 backend_instruction::can_do_cmod() const
 942 {
 943    switch (opcode) {
 944    case BRW_OPCODE_ADD:
 945    case BRW_OPCODE_ADDC:
 946    case BRW_OPCODE_AND:
 947    case BRW_OPCODE_ASR:
 948    case BRW_OPCODE_AVG:
 949    case BRW_OPCODE_CMP:
 950    case BRW_OPCODE_CMPN:
 951    case BRW_OPCODE_DP2:
 952    case BRW_OPCODE_DP3:
 953    case BRW_OPCODE_DP4:
 954    case BRW_OPCODE_DPH:
 955    case BRW_OPCODE_F16TO32:
 956    case BRW_OPCODE_F32TO16:
 957    case BRW_OPCODE_FRC:
 958    case BRW_OPCODE_LINE:
 959    case BRW_OPCODE_LRP:
 960    case BRW_OPCODE_LZD:
 961    case BRW_OPCODE_MAC:
 962    case BRW_OPCODE_MACH:
 963    case BRW_OPCODE_MAD:
 964    case BRW_OPCODE_MOV:
 965    case BRW_OPCODE_MUL:
 966    case BRW_OPCODE_NOT:
 967    case BRW_OPCODE_OR:
 968    case BRW_OPCODE_PLN:
 969    case BRW_OPCODE_RNDD:
 970    case BRW_OPCODE_RNDE:
 971    case BRW_OPCODE_RNDU:
 972    case BRW_OPCODE_RNDZ:
 973    case BRW_OPCODE_SAD2:
 974    case BRW_OPCODE_SADA2:
 975    case BRW_OPCODE_SHL:
 976    case BRW_OPCODE_SHR:
 977    case BRW_OPCODE_SUBB:
 978    case BRW_OPCODE_XOR:
 979    case FS_OPCODE_CINTERP:
 980    case FS_OPCODE_LINTERP:
 981       return true;
 982    default:
 983       return false;
 984    }
 985 }
 986
 987 bool
 988 backend_instruction::reads_accumulator_implicitly() const
 989 {
 990    switch (opcode) {
 991    case BRW_OPCODE_MAC:
 992    case BRW_OPCODE_MACH:
 993    case BRW_OPCODE_SADA2:
 994       return true;
 995    default:
 996       return false;
 997    }
 998 }
 999
1000 bool
1001 backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
1002 {
1003    return writes_accumulator ||
1004           (brw->gen < 6 &&
1005            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1006             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1007              opcode != FS_OPCODE_CINTERP)));
1008 }
1009
1010 bool
1011 backend_instruction::has_side_effects() const
1012 {
1013    switch (opcode) {
1014    case SHADER_OPCODE_UNTYPED_ATOMIC:
1015    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1016    case SHADER_OPCODE_URB_WRITE_SIMD8:
1017    case FS_OPCODE_FB_WRITE:
1018       return true;
1019    default:
1020       return false;
1021    }
1022 }
1023
1024 #ifndef NDEBUG
1025 static bool
1026 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1027 {
1028    bool found = false;
1029    foreach_inst_in_block (backend_instruction, i, block) {
1030       if (inst == i) {
1031          found = true;
1032       }
1033    }
1034    return found;
1035 }
1036 #endif
1037
1038 static void
1039 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1040 {
1041    for (bblock_t *block_iter = start_block->next();
1042         !block_iter->link.is_tail_sentinel();
1043         block_iter = block_iter->next()) {
1044       block_iter->start_ip += ip_adjustment;
1045       block_iter->end_ip += ip_adjustment;
1046    }
1047 }
1048
1049 void
1050 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1051 {
1052    if (!this->is_head_sentinel())
1053       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1054
1055    block->end_ip++;
1056
1057    adjust_later_block_ips(block, 1);
1058
1059    exec_node::insert_after(inst);
1060 }
1061
1062 void
1063 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1064 {
1065    if (!this->is_tail_sentinel())
1066       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1067
1068    block->end_ip++;
1069
1070    adjust_later_block_ips(block, 1);
1071
1072    exec_node::insert_before(inst);
1073 }
1074
1075 void
1076 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1077 {
1078    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1079
1080    unsigned num_inst = list->length();
1081
1082    block->end_ip += num_inst;
1083
1084    adjust_later_block_ips(block, num_inst);
1085
1086    exec_node::insert_before(list);
1087 }
1088
1089 void
1090 backend_instruction::remove(bblock_t *block)
1091 {
1092    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1093
1094    adjust_later_block_ips(block, -1);
1095
1096    if (block->start_ip == block->end_ip) {
1097       block->cfg->remove_block(block);
1098    } else {
1099       block->end_ip--;
1100    }
1101
1102    exec_node::remove();
1103 }
1104
1105 void
1106 backend_visitor::dump_instructions()
1107 {
1108    dump_instructions(NULL);
1109 }
1110
1111 void
1112 backend_visitor::dump_instructions(const char *name)
1113 {
1114    FILE *file = stderr;
1115    if (name && geteuid() != 0) {
1116       file = fopen(name, "w");
1117       if (!file)
1118          file = stderr;
1119    }
1120
1121    if (cfg) {
1122       int ip = 0;
1123       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1124          fprintf(file, "%4d: ", ip++);
1125          dump_instruction(inst, file);
1126       }
1127    } else {
1128       int ip = 0;
1129       foreach_in_list(backend_instruction, inst, &instructions) {
1130          fprintf(file, "%4d: ", ip++);
1131          dump_instruction(inst, file);
1132       }
1133    }
1134
1135    if (file != stderr) {
1136       fclose(file);
1137    }
1138 }
1139
1140 void
1141 backend_visitor::calculate_cfg()
1142 {
1143    if (this->cfg)
1144       return;
1145    cfg = new(mem_ctx) cfg_t(&this->instructions);
1146 }
1147
1148 void
1149 backend_visitor::invalidate_cfg()
1150 {
1151    ralloc_free(this->cfg);
1152    this->cfg = NULL;
1153 }
1154
1155 /**
1156  * Sets up the starting offsets for the groups of binding table entries
1157  * commong to all pipeline stages.
1158  *
1159  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1160  * unused but also make sure that addition of small offsets to them will
1161  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1162  */
1163 void
1164 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1165 {
1166    int num_textures = _mesa_fls(prog->SamplersUsed);
1167
1168    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1169    next_binding_table_offset += num_textures;
1170
1171    if (shader) {
1172       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1173       next_binding_table_offset += shader->base.NumUniformBlocks;
1174    } else {
1175       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1176    }
1177
1178    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1179       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1180       next_binding_table_offset++;
1181    } else {
1182       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1183    }
1184
1185    if (prog->UsesGather) {
1186       if (brw->gen >= 8) {
1187          stage_prog_data->binding_table.gather_texture_start =
1188             stage_prog_data->binding_table.texture_start;
1189       } else {
1190          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1191          next_binding_table_offset += num_textures;
1192       }
1193    } else {
1194       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1195    }
1196
1197    if (shader_prog && shader_prog->NumAtomicBuffers) {
1198       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1199       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1200    } else {
1201       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1202    }
1203
1204    if (shader && shader->base.NumImages) {
1205       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1206       next_binding_table_offset += shader->base.NumImages;
1207    } else {
1208       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1209    }
1210
1211    /* This may or may not be used depending on how the compile goes. */
1212    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1213    next_binding_table_offset++;
1214
1215    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1216
1217    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1218 }