src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34 #include "util/debug.h"
  35
  36 static void
  37 shader_debug_log_mesa(void *data, const char *fmt, ...)
  38 {
  39    struct brw_context *brw = (struct brw_context *)data;
  40    va_list args;
  41
  42    va_start(args, fmt);
  43    GLuint msg_id = 0;
  44    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  45                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  46                    MESA_DEBUG_TYPE_OTHER,
  47                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  48    va_end(args);
  49 }
  50
  51 static void
  52 shader_perf_log_mesa(void *data, const char *fmt, ...)
  53 {
  54    struct brw_context *brw = (struct brw_context *)data;
  55
  56    va_list args;
  57    va_start(args, fmt);
  58
  59    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  60       va_list args_copy;
  61       va_copy(args_copy, args);
  62       vfprintf(stderr, fmt, args_copy);
  63       va_end(args_copy);
  64    }
  65
  66    if (brw->perf_debug) {
  67       GLuint msg_id = 0;
  68       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  69                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  70                       MESA_DEBUG_TYPE_PERFORMANCE,
  71                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  72    }
  73    va_end(args);
  74 }
  75
  76 struct brw_compiler *
  77 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  78 {
  79    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  80
  81    compiler->devinfo = devinfo;
  82    compiler->shader_debug_log = shader_debug_log_mesa;
  83    compiler->shader_perf_log = shader_perf_log_mesa;
  84
  85    brw_fs_alloc_reg_sets(compiler);
  86    brw_vec4_alloc_reg_set(compiler);
  87
  88    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  89       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  90    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  91       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  92    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  93    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  94
  95    nir_shader_compiler_options *nir_options =
  96       rzalloc(compiler, nir_shader_compiler_options);
  97    nir_options->native_integers = true;
  98    /* In order to help allow for better CSE at the NIR level we tell NIR
  99     * to split all ffma instructions during opt_algebraic and we then
 100     * re-combine them as a later step.
 101     */
 102    nir_options->lower_ffma = true;
 103    nir_options->lower_sub = true;
 104    /* In the vec4 backend, our dpN instruction replicates its result to all
 105     * the components of a vec4.  We would like NIR to give us replicated fdot
 106     * instructions because it can optimize better for us.
 107     *
 108     * For the FS backend, it should be lowered away by the scalarizing pass so
 109     * we should never see fdot anyway.
 110     */
 111    nir_options->fdot_replicates = true;
 112
 113    /* We want the GLSL compiler to emit code that uses condition codes */
 114    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 115       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 116       compiler->glsl_compiler_options[i].MaxIfDepth =
 117          devinfo->gen < 6 ? 16 : UINT_MAX;
 118
 119       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 120       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 121       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 122       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 123       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 124       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 125
 126       bool is_scalar = compiler->scalar_stage[i];
 127
 128       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 129       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 130       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 131
 132       /* !ARB_gpu_shader5 */
 133       if (devinfo->gen < 7)
 134          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 135
 136       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 137
 138       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 139    }
 140
 141    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 142       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 143
 144    return compiler;
 145 }
 146
 147 struct gl_shader *
 148 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 149 {
 150    struct brw_shader *shader;
 151
 152    shader = rzalloc(NULL, struct brw_shader);
 153    if (shader) {
 154       shader->base.Type = type;
 155       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 156       shader->base.Name = name;
 157       _mesa_init_shader(ctx, &shader->base);
 158    }
 159
 160    return &shader->base;
 161 }
 162
 163 void
 164 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 165                       unsigned surf_index)
 166 {
 167    assert(surf_index < BRW_MAX_SURFACES);
 168
 169    prog_data->binding_table.size_bytes =
 170       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 171 }
 172
 173 enum brw_reg_type
 174 brw_type_for_base_type(const struct glsl_type *type)
 175 {
 176    switch (type->base_type) {
 177    case GLSL_TYPE_FLOAT:
 178       return BRW_REGISTER_TYPE_F;
 179    case GLSL_TYPE_INT:
 180    case GLSL_TYPE_BOOL:
 181    case GLSL_TYPE_SUBROUTINE:
 182       return BRW_REGISTER_TYPE_D;
 183    case GLSL_TYPE_UINT:
 184       return BRW_REGISTER_TYPE_UD;
 185    case GLSL_TYPE_ARRAY:
 186       return brw_type_for_base_type(type->fields.array);
 187    case GLSL_TYPE_STRUCT:
 188    case GLSL_TYPE_SAMPLER:
 189    case GLSL_TYPE_ATOMIC_UINT:
 190       /* These should be overridden with the type of the member when
 191        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 192        * way to trip up if we don't.
 193        */
 194       return BRW_REGISTER_TYPE_UD;
 195    case GLSL_TYPE_IMAGE:
 196       return BRW_REGISTER_TYPE_UD;
 197    case GLSL_TYPE_VOID:
 198    case GLSL_TYPE_ERROR:
 199    case GLSL_TYPE_INTERFACE:
 200    case GLSL_TYPE_DOUBLE:
 201       unreachable("not reached");
 202    }
 203
 204    return BRW_REGISTER_TYPE_F;
 205 }
 206
 207 enum brw_conditional_mod
 208 brw_conditional_for_comparison(unsigned int op)
 209 {
 210    switch (op) {
 211    case ir_binop_less:
 212       return BRW_CONDITIONAL_L;
 213    case ir_binop_greater:
 214       return BRW_CONDITIONAL_G;
 215    case ir_binop_lequal:
 216       return BRW_CONDITIONAL_LE;
 217    case ir_binop_gequal:
 218       return BRW_CONDITIONAL_GE;
 219    case ir_binop_equal:
 220    case ir_binop_all_equal: /* same as equal for scalars */
 221       return BRW_CONDITIONAL_Z;
 222    case ir_binop_nequal:
 223    case ir_binop_any_nequal: /* same as nequal for scalars */
 224       return BRW_CONDITIONAL_NZ;
 225    default:
 226       unreachable("not reached: bad operation for comparison");
 227    }
 228 }
 229
 230 uint32_t
 231 brw_math_function(enum opcode op)
 232 {
 233    switch (op) {
 234    case SHADER_OPCODE_RCP:
 235       return BRW_MATH_FUNCTION_INV;
 236    case SHADER_OPCODE_RSQ:
 237       return BRW_MATH_FUNCTION_RSQ;
 238    case SHADER_OPCODE_SQRT:
 239       return BRW_MATH_FUNCTION_SQRT;
 240    case SHADER_OPCODE_EXP2:
 241       return BRW_MATH_FUNCTION_EXP;
 242    case SHADER_OPCODE_LOG2:
 243       return BRW_MATH_FUNCTION_LOG;
 244    case SHADER_OPCODE_POW:
 245       return BRW_MATH_FUNCTION_POW;
 246    case SHADER_OPCODE_SIN:
 247       return BRW_MATH_FUNCTION_SIN;
 248    case SHADER_OPCODE_COS:
 249       return BRW_MATH_FUNCTION_COS;
 250    case SHADER_OPCODE_INT_QUOTIENT:
 251       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 252    case SHADER_OPCODE_INT_REMAINDER:
 253       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 254    default:
 255       unreachable("not reached: unknown math function");
 256    }
 257 }
 258
 259 uint32_t
 260 brw_texture_offset(int *offsets, unsigned num_components)
 261 {
 262    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 263
 264    /* Combine all three offsets into a single unsigned dword:
 265     *
 266     *    bits 11:8 - U Offset (X component)
 267     *    bits  7:4 - V Offset (Y component)
 268     *    bits  3:0 - R Offset (Z component)
 269     */
 270    unsigned offset_bits = 0;
 271    for (unsigned i = 0; i < num_components; i++) {
 272       const unsigned shift = 4 * (2 - i);
 273       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 274    }
 275    return offset_bits;
 276 }
 277
 278 const char *
 279 brw_instruction_name(enum opcode op)
 280 {
 281    switch (op) {
 282    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 283       assert(opcode_descs[op].name);
 284       return opcode_descs[op].name;
 285    case FS_OPCODE_FB_WRITE:
 286       return "fb_write";
 287    case FS_OPCODE_FB_WRITE_LOGICAL:
 288       return "fb_write_logical";
 289    case FS_OPCODE_PACK_STENCIL_REF:
 290       return "pack_stencil_ref";
 291    case FS_OPCODE_BLORP_FB_WRITE:
 292       return "blorp_fb_write";
 293    case FS_OPCODE_REP_FB_WRITE:
 294       return "rep_fb_write";
 295
 296    case SHADER_OPCODE_RCP:
 297       return "rcp";
 298    case SHADER_OPCODE_RSQ:
 299       return "rsq";
 300    case SHADER_OPCODE_SQRT:
 301       return "sqrt";
 302    case SHADER_OPCODE_EXP2:
 303       return "exp2";
 304    case SHADER_OPCODE_LOG2:
 305       return "log2";
 306    case SHADER_OPCODE_POW:
 307       return "pow";
 308    case SHADER_OPCODE_INT_QUOTIENT:
 309       return "int_quot";
 310    case SHADER_OPCODE_INT_REMAINDER:
 311       return "int_rem";
 312    case SHADER_OPCODE_SIN:
 313       return "sin";
 314    case SHADER_OPCODE_COS:
 315       return "cos";
 316
 317    case SHADER_OPCODE_TEX:
 318       return "tex";
 319    case SHADER_OPCODE_TEX_LOGICAL:
 320       return "tex_logical";
 321    case SHADER_OPCODE_TXD:
 322       return "txd";
 323    case SHADER_OPCODE_TXD_LOGICAL:
 324       return "txd_logical";
 325    case SHADER_OPCODE_TXF:
 326       return "txf";
 327    case SHADER_OPCODE_TXF_LOGICAL:
 328       return "txf_logical";
 329    case SHADER_OPCODE_TXL:
 330       return "txl";
 331    case SHADER_OPCODE_TXL_LOGICAL:
 332       return "txl_logical";
 333    case SHADER_OPCODE_TXS:
 334       return "txs";
 335    case SHADER_OPCODE_TXS_LOGICAL:
 336       return "txs_logical";
 337    case FS_OPCODE_TXB:
 338       return "txb";
 339    case FS_OPCODE_TXB_LOGICAL:
 340       return "txb_logical";
 341    case SHADER_OPCODE_TXF_CMS:
 342       return "txf_cms";
 343    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 344       return "txf_cms_logical";
 345    case SHADER_OPCODE_TXF_CMS_W:
 346       return "txf_cms_w";
 347    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 348       return "txf_cms_w_logical";
 349    case SHADER_OPCODE_TXF_UMS:
 350       return "txf_ums";
 351    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 352       return "txf_ums_logical";
 353    case SHADER_OPCODE_TXF_MCS:
 354       return "txf_mcs";
 355    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 356       return "txf_mcs_logical";
 357    case SHADER_OPCODE_LOD:
 358       return "lod";
 359    case SHADER_OPCODE_LOD_LOGICAL:
 360       return "lod_logical";
 361    case SHADER_OPCODE_TG4:
 362       return "tg4";
 363    case SHADER_OPCODE_TG4_LOGICAL:
 364       return "tg4_logical";
 365    case SHADER_OPCODE_TG4_OFFSET:
 366       return "tg4_offset";
 367    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 368       return "tg4_offset_logical";
 369    case SHADER_OPCODE_SAMPLEINFO:
 370       return "sampleinfo";
 371
 372    case SHADER_OPCODE_SHADER_TIME_ADD:
 373       return "shader_time_add";
 374
 375    case SHADER_OPCODE_UNTYPED_ATOMIC:
 376       return "untyped_atomic";
 377    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 378       return "untyped_atomic_logical";
 379    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 380       return "untyped_surface_read";
 381    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 382       return "untyped_surface_read_logical";
 383    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 384       return "untyped_surface_write";
 385    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 386       return "untyped_surface_write_logical";
 387    case SHADER_OPCODE_TYPED_ATOMIC:
 388       return "typed_atomic";
 389    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 390       return "typed_atomic_logical";
 391    case SHADER_OPCODE_TYPED_SURFACE_READ:
 392       return "typed_surface_read";
 393    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 394       return "typed_surface_read_logical";
 395    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 396       return "typed_surface_write";
 397    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 398       return "typed_surface_write_logical";
 399    case SHADER_OPCODE_MEMORY_FENCE:
 400       return "memory_fence";
 401
 402    case SHADER_OPCODE_LOAD_PAYLOAD:
 403       return "load_payload";
 404
 405    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 406       return "gen4_scratch_read";
 407    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 408       return "gen4_scratch_write";
 409    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 410       return "gen7_scratch_read";
 411    case SHADER_OPCODE_URB_WRITE_SIMD8:
 412       return "gen8_urb_write_simd8";
 413    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 414       return "gen8_urb_write_simd8_per_slot";
 415    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 416       return "gen8_urb_write_simd8_masked";
 417    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 418       return "gen8_urb_write_simd8_masked_per_slot";
 419    case SHADER_OPCODE_URB_READ_SIMD8:
 420       return "urb_read_simd8";
 421    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 422       return "urb_read_simd8_per_slot";
 423
 424    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 425       return "find_live_channel";
 426    case SHADER_OPCODE_BROADCAST:
 427       return "broadcast";
 428
 429    case VEC4_OPCODE_MOV_BYTES:
 430       return "mov_bytes";
 431    case VEC4_OPCODE_PACK_BYTES:
 432       return "pack_bytes";
 433    case VEC4_OPCODE_UNPACK_UNIFORM:
 434       return "unpack_uniform";
 435
 436    case FS_OPCODE_DDX_COARSE:
 437       return "ddx_coarse";
 438    case FS_OPCODE_DDX_FINE:
 439       return "ddx_fine";
 440    case FS_OPCODE_DDY_COARSE:
 441       return "ddy_coarse";
 442    case FS_OPCODE_DDY_FINE:
 443       return "ddy_fine";
 444
 445    case FS_OPCODE_CINTERP:
 446       return "cinterp";
 447    case FS_OPCODE_LINTERP:
 448       return "linterp";
 449
 450    case FS_OPCODE_PIXEL_X:
 451       return "pixel_x";
 452    case FS_OPCODE_PIXEL_Y:
 453       return "pixel_y";
 454
 455    case FS_OPCODE_GET_BUFFER_SIZE:
 456       return "fs_get_buffer_size";
 457
 458    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 459       return "uniform_pull_const";
 460    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 461       return "uniform_pull_const_gen7";
 462    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 463       return "varying_pull_const";
 464    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 465       return "varying_pull_const_gen7";
 466
 467    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 468       return "mov_dispatch_to_flags";
 469    case FS_OPCODE_DISCARD_JUMP:
 470       return "discard_jump";
 471
 472    case FS_OPCODE_SET_SAMPLE_ID:
 473       return "set_sample_id";
 474    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 475       return "set_simd4x2_offset";
 476
 477    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 478       return "pack_half_2x16_split";
 479    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 480       return "unpack_half_2x16_split_x";
 481    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 482       return "unpack_half_2x16_split_y";
 483
 484    case FS_OPCODE_PLACEHOLDER_HALT:
 485       return "placeholder_halt";
 486
 487    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 488       return "interp_centroid";
 489    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 490       return "interp_sample";
 491    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 492       return "interp_shared_offset";
 493    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 494       return "interp_per_slot_offset";
 495
 496    case VS_OPCODE_URB_WRITE:
 497       return "vs_urb_write";
 498    case VS_OPCODE_PULL_CONSTANT_LOAD:
 499       return "pull_constant_load";
 500    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 501       return "pull_constant_load_gen7";
 502
 503    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 504       return "set_simd4x2_header_gen9";
 505
 506    case VS_OPCODE_GET_BUFFER_SIZE:
 507       return "vs_get_buffer_size";
 508
 509    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 510       return "unpack_flags_simd4x2";
 511
 512    case GS_OPCODE_URB_WRITE:
 513       return "gs_urb_write";
 514    case GS_OPCODE_URB_WRITE_ALLOCATE:
 515       return "gs_urb_write_allocate";
 516    case GS_OPCODE_THREAD_END:
 517       return "gs_thread_end";
 518    case GS_OPCODE_SET_WRITE_OFFSET:
 519       return "set_write_offset";
 520    case GS_OPCODE_SET_VERTEX_COUNT:
 521       return "set_vertex_count";
 522    case GS_OPCODE_SET_DWORD_2:
 523       return "set_dword_2";
 524    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 525       return "prepare_channel_masks";
 526    case GS_OPCODE_SET_CHANNEL_MASKS:
 527       return "set_channel_masks";
 528    case GS_OPCODE_GET_INSTANCE_ID:
 529       return "get_instance_id";
 530    case GS_OPCODE_FF_SYNC:
 531       return "ff_sync";
 532    case GS_OPCODE_SET_PRIMITIVE_ID:
 533       return "set_primitive_id";
 534    case GS_OPCODE_SVB_WRITE:
 535       return "gs_svb_write";
 536    case GS_OPCODE_SVB_SET_DST_INDEX:
 537       return "gs_svb_set_dst_index";
 538    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 539       return "gs_ff_sync_set_primitives";
 540    case CS_OPCODE_CS_TERMINATE:
 541       return "cs_terminate";
 542    case SHADER_OPCODE_BARRIER:
 543       return "barrier";
 544    case SHADER_OPCODE_MULH:
 545       return "mulh";
 546    case SHADER_OPCODE_MOV_INDIRECT:
 547       return "mov_indirect";
 548    }
 549
 550    unreachable("not reached");
 551 }
 552
 553 bool
 554 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 555 {
 556    union {
 557       unsigned ud;
 558       int d;
 559       float f;
 560    } imm = { reg->ud }, sat_imm = { 0 };
 561
 562    switch (type) {
 563    case BRW_REGISTER_TYPE_UD:
 564    case BRW_REGISTER_TYPE_D:
 565    case BRW_REGISTER_TYPE_UW:
 566    case BRW_REGISTER_TYPE_W:
 567    case BRW_REGISTER_TYPE_UQ:
 568    case BRW_REGISTER_TYPE_Q:
 569       /* Nothing to do. */
 570       return false;
 571    case BRW_REGISTER_TYPE_F:
 572       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 573       break;
 574    case BRW_REGISTER_TYPE_UB:
 575    case BRW_REGISTER_TYPE_B:
 576       unreachable("no UB/B immediates");
 577    case BRW_REGISTER_TYPE_V:
 578    case BRW_REGISTER_TYPE_UV:
 579    case BRW_REGISTER_TYPE_VF:
 580       unreachable("unimplemented: saturate vector immediate");
 581    case BRW_REGISTER_TYPE_DF:
 582    case BRW_REGISTER_TYPE_HF:
 583       unreachable("unimplemented: saturate DF/HF immediate");
 584    }
 585
 586    if (imm.ud != sat_imm.ud) {
 587       reg->ud = sat_imm.ud;
 588       return true;
 589    }
 590    return false;
 591 }
 592
 593 bool
 594 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 595 {
 596    switch (type) {
 597    case BRW_REGISTER_TYPE_D:
 598    case BRW_REGISTER_TYPE_UD:
 599       reg->d = -reg->d;
 600       return true;
 601    case BRW_REGISTER_TYPE_W:
 602    case BRW_REGISTER_TYPE_UW:
 603       reg->d = -(int16_t)reg->ud;
 604       return true;
 605    case BRW_REGISTER_TYPE_F:
 606       reg->f = -reg->f;
 607       return true;
 608    case BRW_REGISTER_TYPE_VF:
 609       reg->ud ^= 0x80808080;
 610       return true;
 611    case BRW_REGISTER_TYPE_UB:
 612    case BRW_REGISTER_TYPE_B:
 613       unreachable("no UB/B immediates");
 614    case BRW_REGISTER_TYPE_UV:
 615    case BRW_REGISTER_TYPE_V:
 616       assert(!"unimplemented: negate UV/V immediate");
 617    case BRW_REGISTER_TYPE_UQ:
 618    case BRW_REGISTER_TYPE_Q:
 619       assert(!"unimplemented: negate UQ/Q immediate");
 620    case BRW_REGISTER_TYPE_DF:
 621    case BRW_REGISTER_TYPE_HF:
 622       assert(!"unimplemented: negate DF/HF immediate");
 623    }
 624
 625    return false;
 626 }
 627
 628 bool
 629 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 630 {
 631    switch (type) {
 632    case BRW_REGISTER_TYPE_D:
 633       reg->d = abs(reg->d);
 634       return true;
 635    case BRW_REGISTER_TYPE_W:
 636       reg->d = abs((int16_t)reg->ud);
 637       return true;
 638    case BRW_REGISTER_TYPE_F:
 639       reg->f = fabsf(reg->f);
 640       return true;
 641    case BRW_REGISTER_TYPE_VF:
 642       reg->ud &= ~0x80808080;
 643       return true;
 644    case BRW_REGISTER_TYPE_UB:
 645    case BRW_REGISTER_TYPE_B:
 646       unreachable("no UB/B immediates");
 647    case BRW_REGISTER_TYPE_UQ:
 648    case BRW_REGISTER_TYPE_UD:
 649    case BRW_REGISTER_TYPE_UW:
 650    case BRW_REGISTER_TYPE_UV:
 651       /* Presumably the absolute value modifier on an unsigned source is a
 652        * nop, but it would be nice to confirm.
 653        */
 654       assert(!"unimplemented: abs unsigned immediate");
 655    case BRW_REGISTER_TYPE_V:
 656       assert(!"unimplemented: abs V immediate");
 657    case BRW_REGISTER_TYPE_Q:
 658       assert(!"unimplemented: abs Q immediate");
 659    case BRW_REGISTER_TYPE_DF:
 660    case BRW_REGISTER_TYPE_HF:
 661       assert(!"unimplemented: abs DF/HF immediate");
 662    }
 663
 664    return false;
 665 }
 666
 667 backend_shader::backend_shader(const struct brw_compiler *compiler,
 668                                void *log_data,
 669                                void *mem_ctx,
 670                                const nir_shader *shader,
 671                                struct brw_stage_prog_data *stage_prog_data)
 672    : compiler(compiler),
 673      log_data(log_data),
 674      devinfo(compiler->devinfo),
 675      nir(shader),
 676      stage_prog_data(stage_prog_data),
 677      mem_ctx(mem_ctx),
 678      cfg(NULL),
 679      stage(shader->stage)
 680 {
 681    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 682    stage_name = _mesa_shader_stage_to_string(stage);
 683    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 684 }
 685
 686 bool
 687 backend_reg::is_zero() const
 688 {
 689    if (file != IMM)
 690       return false;
 691
 692    return d == 0;
 693 }
 694
 695 bool
 696 backend_reg::is_one() const
 697 {
 698    if (file != IMM)
 699       return false;
 700
 701    return type == BRW_REGISTER_TYPE_F
 702           ? f == 1.0
 703           : d == 1;
 704 }
 705
 706 bool
 707 backend_reg::is_negative_one() const
 708 {
 709    if (file != IMM)
 710       return false;
 711
 712    switch (type) {
 713    case BRW_REGISTER_TYPE_F:
 714       return f == -1.0;
 715    case BRW_REGISTER_TYPE_D:
 716       return d == -1;
 717    default:
 718       return false;
 719    }
 720 }
 721
 722 bool
 723 backend_reg::is_null() const
 724 {
 725    return file == ARF && nr == BRW_ARF_NULL;
 726 }
 727
 728
 729 bool
 730 backend_reg::is_accumulator() const
 731 {
 732    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 733 }
 734
 735 bool
 736 backend_reg::in_range(const backend_reg &r, unsigned n) const
 737 {
 738    return (file == r.file &&
 739            nr == r.nr &&
 740            reg_offset >= r.reg_offset &&
 741            reg_offset < r.reg_offset + n);
 742 }
 743
 744 bool
 745 backend_instruction::is_commutative() const
 746 {
 747    switch (opcode) {
 748    case BRW_OPCODE_AND:
 749    case BRW_OPCODE_OR:
 750    case BRW_OPCODE_XOR:
 751    case BRW_OPCODE_ADD:
 752    case BRW_OPCODE_MUL:
 753    case SHADER_OPCODE_MULH:
 754       return true;
 755    case BRW_OPCODE_SEL:
 756       /* MIN and MAX are commutative. */
 757       if (conditional_mod == BRW_CONDITIONAL_GE ||
 758           conditional_mod == BRW_CONDITIONAL_L) {
 759          return true;
 760       }
 761       /* fallthrough */
 762    default:
 763       return false;
 764    }
 765 }
 766
 767 bool
 768 backend_instruction::is_3src() const
 769 {
 770    return ::is_3src(opcode);
 771 }
 772
 773 bool
 774 backend_instruction::is_tex() const
 775 {
 776    return (opcode == SHADER_OPCODE_TEX ||
 777            opcode == FS_OPCODE_TXB ||
 778            opcode == SHADER_OPCODE_TXD ||
 779            opcode == SHADER_OPCODE_TXF ||
 780            opcode == SHADER_OPCODE_TXF_CMS ||
 781            opcode == SHADER_OPCODE_TXF_CMS_W ||
 782            opcode == SHADER_OPCODE_TXF_UMS ||
 783            opcode == SHADER_OPCODE_TXF_MCS ||
 784            opcode == SHADER_OPCODE_TXL ||
 785            opcode == SHADER_OPCODE_TXS ||
 786            opcode == SHADER_OPCODE_LOD ||
 787            opcode == SHADER_OPCODE_TG4 ||
 788            opcode == SHADER_OPCODE_TG4_OFFSET);
 789 }
 790
 791 bool
 792 backend_instruction::is_math() const
 793 {
 794    return (opcode == SHADER_OPCODE_RCP ||
 795            opcode == SHADER_OPCODE_RSQ ||
 796            opcode == SHADER_OPCODE_SQRT ||
 797            opcode == SHADER_OPCODE_EXP2 ||
 798            opcode == SHADER_OPCODE_LOG2 ||
 799            opcode == SHADER_OPCODE_SIN ||
 800            opcode == SHADER_OPCODE_COS ||
 801            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 802            opcode == SHADER_OPCODE_INT_REMAINDER ||
 803            opcode == SHADER_OPCODE_POW);
 804 }
 805
 806 bool
 807 backend_instruction::is_control_flow() const
 808 {
 809    switch (opcode) {
 810    case BRW_OPCODE_DO:
 811    case BRW_OPCODE_WHILE:
 812    case BRW_OPCODE_IF:
 813    case BRW_OPCODE_ELSE:
 814    case BRW_OPCODE_ENDIF:
 815    case BRW_OPCODE_BREAK:
 816    case BRW_OPCODE_CONTINUE:
 817       return true;
 818    default:
 819       return false;
 820    }
 821 }
 822
 823 bool
 824 backend_instruction::can_do_source_mods() const
 825 {
 826    switch (opcode) {
 827    case BRW_OPCODE_ADDC:
 828    case BRW_OPCODE_BFE:
 829    case BRW_OPCODE_BFI1:
 830    case BRW_OPCODE_BFI2:
 831    case BRW_OPCODE_BFREV:
 832    case BRW_OPCODE_CBIT:
 833    case BRW_OPCODE_FBH:
 834    case BRW_OPCODE_FBL:
 835    case BRW_OPCODE_SUBB:
 836       return false;
 837    default:
 838       return true;
 839    }
 840 }
 841
 842 bool
 843 backend_instruction::can_do_saturate() const
 844 {
 845    switch (opcode) {
 846    case BRW_OPCODE_ADD:
 847    case BRW_OPCODE_ASR:
 848    case BRW_OPCODE_AVG:
 849    case BRW_OPCODE_DP2:
 850    case BRW_OPCODE_DP3:
 851    case BRW_OPCODE_DP4:
 852    case BRW_OPCODE_DPH:
 853    case BRW_OPCODE_F16TO32:
 854    case BRW_OPCODE_F32TO16:
 855    case BRW_OPCODE_LINE:
 856    case BRW_OPCODE_LRP:
 857    case BRW_OPCODE_MAC:
 858    case BRW_OPCODE_MAD:
 859    case BRW_OPCODE_MATH:
 860    case BRW_OPCODE_MOV:
 861    case BRW_OPCODE_MUL:
 862    case SHADER_OPCODE_MULH:
 863    case BRW_OPCODE_PLN:
 864    case BRW_OPCODE_RNDD:
 865    case BRW_OPCODE_RNDE:
 866    case BRW_OPCODE_RNDU:
 867    case BRW_OPCODE_RNDZ:
 868    case BRW_OPCODE_SEL:
 869    case BRW_OPCODE_SHL:
 870    case BRW_OPCODE_SHR:
 871    case FS_OPCODE_LINTERP:
 872    case SHADER_OPCODE_COS:
 873    case SHADER_OPCODE_EXP2:
 874    case SHADER_OPCODE_LOG2:
 875    case SHADER_OPCODE_POW:
 876    case SHADER_OPCODE_RCP:
 877    case SHADER_OPCODE_RSQ:
 878    case SHADER_OPCODE_SIN:
 879    case SHADER_OPCODE_SQRT:
 880       return true;
 881    default:
 882       return false;
 883    }
 884 }
 885
 886 bool
 887 backend_instruction::can_do_cmod() const
 888 {
 889    switch (opcode) {
 890    case BRW_OPCODE_ADD:
 891    case BRW_OPCODE_ADDC:
 892    case BRW_OPCODE_AND:
 893    case BRW_OPCODE_ASR:
 894    case BRW_OPCODE_AVG:
 895    case BRW_OPCODE_CMP:
 896    case BRW_OPCODE_CMPN:
 897    case BRW_OPCODE_DP2:
 898    case BRW_OPCODE_DP3:
 899    case BRW_OPCODE_DP4:
 900    case BRW_OPCODE_DPH:
 901    case BRW_OPCODE_F16TO32:
 902    case BRW_OPCODE_F32TO16:
 903    case BRW_OPCODE_FRC:
 904    case BRW_OPCODE_LINE:
 905    case BRW_OPCODE_LRP:
 906    case BRW_OPCODE_LZD:
 907    case BRW_OPCODE_MAC:
 908    case BRW_OPCODE_MACH:
 909    case BRW_OPCODE_MAD:
 910    case BRW_OPCODE_MOV:
 911    case BRW_OPCODE_MUL:
 912    case BRW_OPCODE_NOT:
 913    case BRW_OPCODE_OR:
 914    case BRW_OPCODE_PLN:
 915    case BRW_OPCODE_RNDD:
 916    case BRW_OPCODE_RNDE:
 917    case BRW_OPCODE_RNDU:
 918    case BRW_OPCODE_RNDZ:
 919    case BRW_OPCODE_SAD2:
 920    case BRW_OPCODE_SADA2:
 921    case BRW_OPCODE_SHL:
 922    case BRW_OPCODE_SHR:
 923    case BRW_OPCODE_SUBB:
 924    case BRW_OPCODE_XOR:
 925    case FS_OPCODE_CINTERP:
 926    case FS_OPCODE_LINTERP:
 927       return true;
 928    default:
 929       return false;
 930    }
 931 }
 932
 933 bool
 934 backend_instruction::reads_accumulator_implicitly() const
 935 {
 936    switch (opcode) {
 937    case BRW_OPCODE_MAC:
 938    case BRW_OPCODE_MACH:
 939    case BRW_OPCODE_SADA2:
 940       return true;
 941    default:
 942       return false;
 943    }
 944 }
 945
 946 bool
 947 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 948 {
 949    return writes_accumulator ||
 950           (devinfo->gen < 6 &&
 951            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 952             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 953              opcode != FS_OPCODE_CINTERP)));
 954 }
 955
 956 bool
 957 backend_instruction::has_side_effects() const
 958 {
 959    switch (opcode) {
 960    case SHADER_OPCODE_UNTYPED_ATOMIC:
 961    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 962    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 963    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 964    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 965    case SHADER_OPCODE_TYPED_ATOMIC:
 966    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 967    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 968    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 969    case SHADER_OPCODE_MEMORY_FENCE:
 970    case SHADER_OPCODE_URB_WRITE_SIMD8:
 971    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 972    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 973    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 974    case FS_OPCODE_FB_WRITE:
 975    case SHADER_OPCODE_BARRIER:
 976       return true;
 977    default:
 978       return false;
 979    }
 980 }
 981
 982 bool
 983 backend_instruction::is_volatile() const
 984 {
 985    switch (opcode) {
 986    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 987    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 988    case SHADER_OPCODE_TYPED_SURFACE_READ:
 989    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 990       return true;
 991    default:
 992       return false;
 993    }
 994 }
 995
 996 #ifndef NDEBUG
 997 static bool
 998 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 999 {
1000    bool found = false;
1001    foreach_inst_in_block (backend_instruction, i, block) {
1002       if (inst == i) {
1003          found = true;
1004       }
1005    }
1006    return found;
1007 }
1008 #endif
1009
1010 static void
1011 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1012 {
1013    for (bblock_t *block_iter = start_block->next();
1014         !block_iter->link.is_tail_sentinel();
1015         block_iter = block_iter->next()) {
1016       block_iter->start_ip += ip_adjustment;
1017       block_iter->end_ip += ip_adjustment;
1018    }
1019 }
1020
1021 void
1022 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1023 {
1024    if (!this->is_head_sentinel())
1025       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1026
1027    block->end_ip++;
1028
1029    adjust_later_block_ips(block, 1);
1030
1031    exec_node::insert_after(inst);
1032 }
1033
1034 void
1035 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1036 {
1037    if (!this->is_tail_sentinel())
1038       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1039
1040    block->end_ip++;
1041
1042    adjust_later_block_ips(block, 1);
1043
1044    exec_node::insert_before(inst);
1045 }
1046
1047 void
1048 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1049 {
1050    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1051
1052    unsigned num_inst = list->length();
1053
1054    block->end_ip += num_inst;
1055
1056    adjust_later_block_ips(block, num_inst);
1057
1058    exec_node::insert_before(list);
1059 }
1060
1061 void
1062 backend_instruction::remove(bblock_t *block)
1063 {
1064    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1065
1066    adjust_later_block_ips(block, -1);
1067
1068    if (block->start_ip == block->end_ip) {
1069       block->cfg->remove_block(block);
1070    } else {
1071       block->end_ip--;
1072    }
1073
1074    exec_node::remove();
1075 }
1076
1077 void
1078 backend_shader::dump_instructions()
1079 {
1080    dump_instructions(NULL);
1081 }
1082
1083 void
1084 backend_shader::dump_instructions(const char *name)
1085 {
1086    FILE *file = stderr;
1087    if (name && geteuid() != 0) {
1088       file = fopen(name, "w");
1089       if (!file)
1090          file = stderr;
1091    }
1092
1093    if (cfg) {
1094       int ip = 0;
1095       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1096          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1097             fprintf(file, "%4d: ", ip++);
1098          dump_instruction(inst, file);
1099       }
1100    } else {
1101       int ip = 0;
1102       foreach_in_list(backend_instruction, inst, &instructions) {
1103          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1104             fprintf(file, "%4d: ", ip++);
1105          dump_instruction(inst, file);
1106       }
1107    }
1108
1109    if (file != stderr) {
1110       fclose(file);
1111    }
1112 }
1113
1114 void
1115 backend_shader::calculate_cfg()
1116 {
1117    if (this->cfg)
1118       return;
1119    cfg = new(mem_ctx) cfg_t(&this->instructions);
1120 }
1121
1122 void
1123 backend_shader::invalidate_cfg()
1124 {
1125    ralloc_free(this->cfg);
1126    this->cfg = NULL;
1127 }
1128
1129 /**
1130  * Sets up the starting offsets for the groups of binding table entries
1131  * commong to all pipeline stages.
1132  *
1133  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1134  * unused but also make sure that addition of small offsets to them will
1135  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1136  */
1137 void
1138 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1139                                         const struct brw_device_info *devinfo,
1140                                         const struct gl_shader_program *shader_prog,
1141                                         const struct gl_program *prog,
1142                                         struct brw_stage_prog_data *stage_prog_data,
1143                                         uint32_t next_binding_table_offset)
1144 {
1145    const struct gl_shader *shader = NULL;
1146    int num_textures = _mesa_fls(prog->SamplersUsed);
1147
1148    if (shader_prog)
1149       shader = shader_prog->_LinkedShaders[stage];
1150
1151    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1152    next_binding_table_offset += num_textures;
1153
1154    if (shader) {
1155       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1156       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1157       next_binding_table_offset += shader->NumUniformBlocks;
1158
1159       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1160       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1161       next_binding_table_offset += shader->NumShaderStorageBlocks;
1162    } else {
1163       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1164       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1165    }
1166
1167    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1168       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1169       next_binding_table_offset++;
1170    } else {
1171       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1172    }
1173
1174    if (prog->UsesGather) {
1175       if (devinfo->gen >= 8) {
1176          stage_prog_data->binding_table.gather_texture_start =
1177             stage_prog_data->binding_table.texture_start;
1178       } else {
1179          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1180          next_binding_table_offset += num_textures;
1181       }
1182    } else {
1183       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1184    }
1185
1186    if (shader && shader->NumAtomicBuffers) {
1187       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1188       next_binding_table_offset += shader->NumAtomicBuffers;
1189    } else {
1190       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1191    }
1192
1193    if (shader && shader->NumImages) {
1194       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1195       next_binding_table_offset += shader->NumImages;
1196    } else {
1197       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1198    }
1199
1200    /* This may or may not be used depending on how the compile goes. */
1201    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1202    next_binding_table_offset++;
1203
1204    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1205
1206    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1207 }
1208
1209 static void
1210 setup_vec4_uniform_value(const gl_constant_value **params,
1211                          const gl_constant_value *values,
1212                          unsigned n)
1213 {
1214    static const gl_constant_value zero = { 0 };
1215
1216    for (unsigned i = 0; i < n; ++i)
1217       params[i] = &values[i];
1218
1219    for (unsigned i = n; i < 4; ++i)
1220       params[i] = &zero;
1221 }
1222
1223 void
1224 brw_setup_image_uniform_values(gl_shader_stage stage,
1225                                struct brw_stage_prog_data *stage_prog_data,
1226                                unsigned param_start_index,
1227                                const gl_uniform_storage *storage)
1228 {
1229    const gl_constant_value **param =
1230       &stage_prog_data->param[param_start_index];
1231
1232    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1233       const unsigned image_idx = storage->opaque[stage].index + i;
1234       const brw_image_param *image_param =
1235          &stage_prog_data->image_param[image_idx];
1236
1237       /* Upload the brw_image_param structure.  The order is expected to match
1238        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1239        */
1240       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1241          (const gl_constant_value *)&image_param->surface_idx, 1);
1242       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1243          (const gl_constant_value *)image_param->offset, 2);
1244       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1245          (const gl_constant_value *)image_param->size, 3);
1246       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1247          (const gl_constant_value *)image_param->stride, 4);
1248       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1249          (const gl_constant_value *)image_param->tiling, 3);
1250       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1251          (const gl_constant_value *)image_param->swizzling, 2);
1252       param += BRW_IMAGE_PARAM_SIZE;
1253
1254       brw_mark_surface_used(
1255          stage_prog_data,
1256          stage_prog_data->binding_table.image_start + image_idx);
1257    }
1258 }
1259
1260 /**
1261  * Decide which set of clip planes should be used when clipping via
1262  * gl_Position or gl_ClipVertex.
1263  */
1264 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1265 {
1266    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1267       /* There is currently a GLSL vertex shader, so clip according to GLSL
1268        * rules, which means compare gl_ClipVertex (or gl_Position, if
1269        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1270        * that were stored in EyeUserPlane at the time the clip planes were
1271        * specified.
1272        */
1273       return ctx->Transform.EyeUserPlane;
1274    } else {
1275       /* Either we are using fixed function or an ARB vertex program.  In
1276        * either case the clip planes are going to be compared against
1277        * gl_Position (which is in clip coordinates) so we have to clip using
1278        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1279        * core.
1280        */
1281       return ctx->Transform._ClipUserPlane;
1282    }
1283 }
1284