src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "brw_context.h"
  27 }
  28 #include "brw_vs.h"
  29 #include "brw_gs.h"
  30 #include "brw_fs.h"
  31 #include "brw_cfg.h"
  32 #include "glsl/ir_optimization.h"
  33 #include "glsl/glsl_parser_extras.h"
  34 #include "main/shaderapi.h"
  35
  36 struct gl_shader *
  37 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  38 {
  39    struct brw_shader *shader;
  40
  41    shader = rzalloc(NULL, struct brw_shader);
  42    if (shader) {
  43       shader->base.Type = type;
  44       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  45       shader->base.Name = name;
  46       _mesa_init_shader(ctx, &shader->base);
  47    }
  48
  49    return &shader->base;
  50 }
  51
  52 /**
  53  * Performs a compile of the shader stages even when we don't know
  54  * what non-orthogonal state will be set, in the hope that it reflects
  55  * the eventual NOS used, and thus allows us to produce link failures.
  56  */
  57 static bool
  58 brw_shader_precompile(struct gl_context *ctx,
  59                       struct gl_shader_program *sh_prog)
  60 {
  61    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  62    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  63    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  64
  65    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  66       return false;
  67
  68    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  69       return false;
  70
  71    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  72       return false;
  73
  74    return true;
  75 }
  76
  77 static inline bool
  78 is_scalar_shader_stage(struct brw_context *brw, int stage)
  79 {
  80    switch (stage) {
  81    case MESA_SHADER_FRAGMENT:
  82       return true;
  83    case MESA_SHADER_VERTEX:
  84       return brw->scalar_vs;
  85    default:
  86       return false;
  87    }
  88 }
  89
  90 static void
  91 brw_lower_packing_builtins(struct brw_context *brw,
  92                            gl_shader_stage shader_type,
  93                            exec_list *ir)
  94 {
  95    int ops = LOWER_PACK_SNORM_2x16
  96            | LOWER_UNPACK_SNORM_2x16
  97            | LOWER_PACK_UNORM_2x16
  98            | LOWER_UNPACK_UNORM_2x16;
  99
 100    if (is_scalar_shader_stage(brw, shader_type)) {
 101       ops |= LOWER_UNPACK_UNORM_4x8
 102            | LOWER_UNPACK_SNORM_4x8
 103            | LOWER_PACK_UNORM_4x8
 104            | LOWER_PACK_SNORM_4x8;
 105    }
 106
 107    if (brw->gen >= 7) {
 108       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 109        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 110        * lowering is needed. For SOA code, the Half2x16 ops must be
 111        * scalarized.
 112        */
 113       if (is_scalar_shader_stage(brw, shader_type)) {
 114          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 115              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 116       }
 117    } else {
 118       ops |= LOWER_PACK_HALF_2x16
 119           |  LOWER_UNPACK_HALF_2x16;
 120    }
 121
 122    lower_packing_builtins(ir, ops);
 123 }
 124
 125 GLboolean
 126 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 127 {
 128    struct brw_context *brw = brw_context(ctx);
 129    unsigned int stage;
 130
 131    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 132       const struct gl_shader_compiler_options *options =
 133          &ctx->Const.ShaderCompilerOptions[stage];
 134       struct brw_shader *shader =
 135          (struct brw_shader *)shProg->_LinkedShaders[stage];
 136
 137       if (!shader)
 138          continue;
 139
 140       struct gl_program *prog =
 141          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 142                                 shader->base.Name);
 143       if (!prog)
 144         return false;
 145       prog->Parameters = _mesa_new_parameter_list();
 146
 147       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 148
 149       bool progress;
 150
 151       /* lower_packing_builtins() inserts arithmetic instructions, so it
 152        * must precede lower_instructions().
 153        */
 154       brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->base.ir);
 155       do_mat_op_to_vec(shader->base.ir);
 156       const int bitfield_insert = brw->gen >= 7
 157                                   ? BITFIELD_INSERT_TO_BFM_BFI
 158                                   : 0;
 159       lower_instructions(shader->base.ir,
 160                          MOD_TO_FLOOR |
 161                          DIV_TO_MUL_RCP |
 162                          SUB_TO_ADD_NEG |
 163                          EXP_TO_EXP2 |
 164                          LOG_TO_LOG2 |
 165                          bitfield_insert |
 166                          LDEXP_TO_ARITH);
 167
 168       /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 169        * if-statements need to be flattened.
 170        */
 171       if (brw->gen < 6)
 172          lower_if_to_cond_assign(shader->base.ir, 16);
 173
 174       do_lower_texture_projection(shader->base.ir);
 175       brw_lower_texture_gradients(brw, shader->base.ir);
 176       do_vec_index_to_cond_assign(shader->base.ir);
 177       lower_vector_insert(shader->base.ir, true);
 178       brw_do_cubemap_normalize(shader->base.ir);
 179       lower_offset_arrays(shader->base.ir);
 180       brw_do_lower_unnormalized_offset(shader->base.ir);
 181       lower_noise(shader->base.ir);
 182       lower_quadop_vector(shader->base.ir, false);
 183
 184       bool lowered_variable_indexing =
 185          lower_variable_index_to_cond_assign(shader->base.ir,
 186                                              options->EmitNoIndirectInput,
 187                                              options->EmitNoIndirectOutput,
 188                                              options->EmitNoIndirectTemp,
 189                                              options->EmitNoIndirectUniform);
 190
 191       if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 192          perf_debug("Unsupported form of variable indexing in FS; falling "
 193                     "back to very inefficient code generation\n");
 194       }
 195
 196       lower_ubo_reference(&shader->base, shader->base.ir);
 197
 198       do {
 199          progress = false;
 200
 201          if (is_scalar_shader_stage(brw, stage)) {
 202             brw_do_channel_expressions(shader->base.ir);
 203             brw_do_vector_splitting(shader->base.ir);
 204          }
 205
 206          progress = do_lower_jumps(shader->base.ir, true, true,
 207                                    true, /* main return */
 208                                    false, /* continue */
 209                                    false /* loops */
 210                                    ) || progress;
 211
 212          progress = do_common_optimization(shader->base.ir, true, true,
 213                                            options, ctx->Const.NativeIntegers)
 214            || progress;
 215       } while (progress);
 216
 217       /* Make a pass over the IR to add state references for any built-in
 218        * uniforms that are used.  This has to be done now (during linking).
 219        * Code generation doesn't happen until the first time this shader is
 220        * used for rendering.  Waiting until then to generate the parameters is
 221        * too late.  At that point, the values for the built-in uniforms won't
 222        * get sent to the shader.
 223        */
 224       foreach_in_list(ir_instruction, node, shader->base.ir) {
 225          ir_variable *var = node->as_variable();
 226
 227          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 228              || (strncmp(var->name, "gl_", 3) != 0))
 229             continue;
 230
 231          const ir_state_slot *const slots = var->get_state_slots();
 232          assert(slots != NULL);
 233
 234          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 235             _mesa_add_state_reference(prog->Parameters,
 236                                       (gl_state_index *) slots[i].tokens);
 237          }
 238       }
 239
 240       validate_ir_tree(shader->base.ir);
 241
 242       do_set_program_inouts(shader->base.ir, prog, shader->base.Stage);
 243
 244       prog->SamplersUsed = shader->base.active_samplers;
 245       prog->ShadowSamplers = shader->base.shadow_samplers;
 246       _mesa_update_shader_textures_used(shProg, prog);
 247
 248       _mesa_reference_program(ctx, &shader->base.Program, prog);
 249
 250       brw_add_texrect_params(prog);
 251
 252       _mesa_reference_program(ctx, &prog, NULL);
 253
 254       if (ctx->_Shader->Flags & GLSL_DUMP) {
 255          fprintf(stderr, "\n");
 256          fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 257                  _mesa_shader_stage_to_string(shader->base.Stage),
 258                  shProg->Name);
 259          _mesa_print_ir(stderr, shader->base.ir, NULL);
 260          fprintf(stderr, "\n");
 261       }
 262    }
 263
 264    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 265       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 266          const struct gl_shader *sh = shProg->Shaders[i];
 267          if (!sh)
 268             continue;
 269
 270          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 271                  _mesa_shader_stage_to_string(sh->Stage),
 272                  i, shProg->Name);
 273          fprintf(stderr, "%s", sh->Source);
 274          fprintf(stderr, "\n");
 275       }
 276    }
 277
 278    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 279       return false;
 280
 281    return true;
 282 }
 283
 284
 285 enum brw_reg_type
 286 brw_type_for_base_type(const struct glsl_type *type)
 287 {
 288    switch (type->base_type) {
 289    case GLSL_TYPE_FLOAT:
 290       return BRW_REGISTER_TYPE_F;
 291    case GLSL_TYPE_INT:
 292    case GLSL_TYPE_BOOL:
 293       return BRW_REGISTER_TYPE_D;
 294    case GLSL_TYPE_UINT:
 295       return BRW_REGISTER_TYPE_UD;
 296    case GLSL_TYPE_ARRAY:
 297       return brw_type_for_base_type(type->fields.array);
 298    case GLSL_TYPE_STRUCT:
 299    case GLSL_TYPE_SAMPLER:
 300    case GLSL_TYPE_ATOMIC_UINT:
 301       /* These should be overridden with the type of the member when
 302        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 303        * way to trip up if we don't.
 304        */
 305       return BRW_REGISTER_TYPE_UD;
 306    case GLSL_TYPE_IMAGE:
 307       return BRW_REGISTER_TYPE_UD;
 308    case GLSL_TYPE_VOID:
 309    case GLSL_TYPE_ERROR:
 310    case GLSL_TYPE_INTERFACE:
 311    case GLSL_TYPE_DOUBLE:
 312       unreachable("not reached");
 313    }
 314
 315    return BRW_REGISTER_TYPE_F;
 316 }
 317
 318 enum brw_conditional_mod
 319 brw_conditional_for_comparison(unsigned int op)
 320 {
 321    switch (op) {
 322    case ir_binop_less:
 323       return BRW_CONDITIONAL_L;
 324    case ir_binop_greater:
 325       return BRW_CONDITIONAL_G;
 326    case ir_binop_lequal:
 327       return BRW_CONDITIONAL_LE;
 328    case ir_binop_gequal:
 329       return BRW_CONDITIONAL_GE;
 330    case ir_binop_equal:
 331    case ir_binop_all_equal: /* same as equal for scalars */
 332       return BRW_CONDITIONAL_Z;
 333    case ir_binop_nequal:
 334    case ir_binop_any_nequal: /* same as nequal for scalars */
 335       return BRW_CONDITIONAL_NZ;
 336    default:
 337       unreachable("not reached: bad operation for comparison");
 338    }
 339 }
 340
 341 uint32_t
 342 brw_math_function(enum opcode op)
 343 {
 344    switch (op) {
 345    case SHADER_OPCODE_RCP:
 346       return BRW_MATH_FUNCTION_INV;
 347    case SHADER_OPCODE_RSQ:
 348       return BRW_MATH_FUNCTION_RSQ;
 349    case SHADER_OPCODE_SQRT:
 350       return BRW_MATH_FUNCTION_SQRT;
 351    case SHADER_OPCODE_EXP2:
 352       return BRW_MATH_FUNCTION_EXP;
 353    case SHADER_OPCODE_LOG2:
 354       return BRW_MATH_FUNCTION_LOG;
 355    case SHADER_OPCODE_POW:
 356       return BRW_MATH_FUNCTION_POW;
 357    case SHADER_OPCODE_SIN:
 358       return BRW_MATH_FUNCTION_SIN;
 359    case SHADER_OPCODE_COS:
 360       return BRW_MATH_FUNCTION_COS;
 361    case SHADER_OPCODE_INT_QUOTIENT:
 362       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 363    case SHADER_OPCODE_INT_REMAINDER:
 364       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 365    default:
 366       unreachable("not reached: unknown math function");
 367    }
 368 }
 369
 370 uint32_t
 371 brw_texture_offset(struct gl_context *ctx, int *offsets,
 372                    unsigned num_components)
 373 {
 374    /* If the driver does not support GL_ARB_gpu_shader5, the offset
 375     * must be constant.
 376     */
 377    assert(offsets != NULL || ctx->Extensions.ARB_gpu_shader5);
 378
 379    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 380
 381    /* Combine all three offsets into a single unsigned dword:
 382     *
 383     *    bits 11:8 - U Offset (X component)
 384     *    bits  7:4 - V Offset (Y component)
 385     *    bits  3:0 - R Offset (Z component)
 386     */
 387    unsigned offset_bits = 0;
 388    for (unsigned i = 0; i < num_components; i++) {
 389       const unsigned shift = 4 * (2 - i);
 390       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 391    }
 392    return offset_bits;
 393 }
 394
 395 const char *
 396 brw_instruction_name(enum opcode op)
 397 {
 398    switch (op) {
 399    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 400       assert(opcode_descs[op].name);
 401       return opcode_descs[op].name;
 402    case FS_OPCODE_FB_WRITE:
 403       return "fb_write";
 404    case FS_OPCODE_BLORP_FB_WRITE:
 405       return "blorp_fb_write";
 406    case FS_OPCODE_REP_FB_WRITE:
 407       return "rep_fb_write";
 408
 409    case SHADER_OPCODE_RCP:
 410       return "rcp";
 411    case SHADER_OPCODE_RSQ:
 412       return "rsq";
 413    case SHADER_OPCODE_SQRT:
 414       return "sqrt";
 415    case SHADER_OPCODE_EXP2:
 416       return "exp2";
 417    case SHADER_OPCODE_LOG2:
 418       return "log2";
 419    case SHADER_OPCODE_POW:
 420       return "pow";
 421    case SHADER_OPCODE_INT_QUOTIENT:
 422       return "int_quot";
 423    case SHADER_OPCODE_INT_REMAINDER:
 424       return "int_rem";
 425    case SHADER_OPCODE_SIN:
 426       return "sin";
 427    case SHADER_OPCODE_COS:
 428       return "cos";
 429
 430    case SHADER_OPCODE_TEX:
 431       return "tex";
 432    case SHADER_OPCODE_TXD:
 433       return "txd";
 434    case SHADER_OPCODE_TXF:
 435       return "txf";
 436    case SHADER_OPCODE_TXL:
 437       return "txl";
 438    case SHADER_OPCODE_TXS:
 439       return "txs";
 440    case FS_OPCODE_TXB:
 441       return "txb";
 442    case SHADER_OPCODE_TXF_CMS:
 443       return "txf_cms";
 444    case SHADER_OPCODE_TXF_UMS:
 445       return "txf_ums";
 446    case SHADER_OPCODE_TXF_MCS:
 447       return "txf_mcs";
 448    case SHADER_OPCODE_LOD:
 449       return "lod";
 450    case SHADER_OPCODE_TG4:
 451       return "tg4";
 452    case SHADER_OPCODE_TG4_OFFSET:
 453       return "tg4_offset";
 454    case SHADER_OPCODE_SHADER_TIME_ADD:
 455       return "shader_time_add";
 456
 457    case SHADER_OPCODE_UNTYPED_ATOMIC:
 458       return "untyped_atomic";
 459    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 460       return "untyped_surface_read";
 461
 462    case SHADER_OPCODE_LOAD_PAYLOAD:
 463       return "load_payload";
 464
 465    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 466       return "gen4_scratch_read";
 467    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 468       return "gen4_scratch_write";
 469    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 470       return "gen7_scratch_read";
 471    case SHADER_OPCODE_URB_WRITE_SIMD8:
 472       return "gen8_urb_write_simd8";
 473
 474    case VEC4_OPCODE_MOV_BYTES:
 475       return "mov_bytes";
 476    case VEC4_OPCODE_PACK_BYTES:
 477       return "pack_bytes";
 478    case VEC4_OPCODE_UNPACK_UNIFORM:
 479       return "unpack_uniform";
 480
 481    case FS_OPCODE_DDX_COARSE:
 482       return "ddx_coarse";
 483    case FS_OPCODE_DDX_FINE:
 484       return "ddx_fine";
 485    case FS_OPCODE_DDY_COARSE:
 486       return "ddy_coarse";
 487    case FS_OPCODE_DDY_FINE:
 488       return "ddy_fine";
 489
 490    case FS_OPCODE_PIXEL_X:
 491       return "pixel_x";
 492    case FS_OPCODE_PIXEL_Y:
 493       return "pixel_y";
 494
 495    case FS_OPCODE_CINTERP:
 496       return "cinterp";
 497    case FS_OPCODE_LINTERP:
 498       return "linterp";
 499
 500    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 501       return "uniform_pull_const";
 502    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 503       return "uniform_pull_const_gen7";
 504    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 505       return "varying_pull_const";
 506    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 507       return "varying_pull_const_gen7";
 508
 509    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 510       return "mov_dispatch_to_flags";
 511    case FS_OPCODE_DISCARD_JUMP:
 512       return "discard_jump";
 513
 514    case FS_OPCODE_SET_OMASK:
 515       return "set_omask";
 516    case FS_OPCODE_SET_SAMPLE_ID:
 517       return "set_sample_id";
 518    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 519       return "set_simd4x2_offset";
 520
 521    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 522       return "pack_half_2x16_split";
 523    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 524       return "unpack_half_2x16_split_x";
 525    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 526       return "unpack_half_2x16_split_y";
 527
 528    case FS_OPCODE_PLACEHOLDER_HALT:
 529       return "placeholder_halt";
 530
 531    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 532       return "interp_centroid";
 533    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 534       return "interp_sample";
 535    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 536       return "interp_shared_offset";
 537    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 538       return "interp_per_slot_offset";
 539
 540    case VS_OPCODE_URB_WRITE:
 541       return "vs_urb_write";
 542    case VS_OPCODE_PULL_CONSTANT_LOAD:
 543       return "pull_constant_load";
 544    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 545       return "pull_constant_load_gen7";
 546    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 547       return "unpack_flags_simd4x2";
 548
 549    case GS_OPCODE_URB_WRITE:
 550       return "gs_urb_write";
 551    case GS_OPCODE_URB_WRITE_ALLOCATE:
 552       return "gs_urb_write_allocate";
 553    case GS_OPCODE_THREAD_END:
 554       return "gs_thread_end";
 555    case GS_OPCODE_SET_WRITE_OFFSET:
 556       return "set_write_offset";
 557    case GS_OPCODE_SET_VERTEX_COUNT:
 558       return "set_vertex_count";
 559    case GS_OPCODE_SET_DWORD_2:
 560       return "set_dword_2";
 561    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 562       return "prepare_channel_masks";
 563    case GS_OPCODE_SET_CHANNEL_MASKS:
 564       return "set_channel_masks";
 565    case GS_OPCODE_GET_INSTANCE_ID:
 566       return "get_instance_id";
 567    case GS_OPCODE_FF_SYNC:
 568       return "ff_sync";
 569    case GS_OPCODE_SET_PRIMITIVE_ID:
 570       return "set_primitive_id";
 571    case GS_OPCODE_SVB_WRITE:
 572       return "gs_svb_write";
 573    case GS_OPCODE_SVB_SET_DST_INDEX:
 574       return "gs_svb_set_dst_index";
 575    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 576       return "gs_ff_sync_set_primitives";
 577    }
 578
 579    unreachable("not reached");
 580 }
 581
 582 bool
 583 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 584 {
 585    union {
 586       unsigned ud;
 587       int d;
 588       float f;
 589    } imm = { reg->dw1.ud }, sat_imm;
 590
 591    switch (type) {
 592    case BRW_REGISTER_TYPE_UD:
 593    case BRW_REGISTER_TYPE_D:
 594    case BRW_REGISTER_TYPE_UQ:
 595    case BRW_REGISTER_TYPE_Q:
 596       /* Nothing to do. */
 597       return false;
 598    case BRW_REGISTER_TYPE_UW:
 599       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 600       break;
 601    case BRW_REGISTER_TYPE_W:
 602       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 603       break;
 604    case BRW_REGISTER_TYPE_F:
 605       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 606       break;
 607    case BRW_REGISTER_TYPE_UB:
 608    case BRW_REGISTER_TYPE_B:
 609       unreachable("no UB/B immediates");
 610    case BRW_REGISTER_TYPE_V:
 611    case BRW_REGISTER_TYPE_UV:
 612    case BRW_REGISTER_TYPE_VF:
 613       unreachable("unimplemented: saturate vector immediate");
 614    case BRW_REGISTER_TYPE_DF:
 615    case BRW_REGISTER_TYPE_HF:
 616       unreachable("unimplemented: saturate DF/HF immediate");
 617    }
 618
 619    if (imm.ud != sat_imm.ud) {
 620       reg->dw1.ud = sat_imm.ud;
 621       return true;
 622    }
 623    return false;
 624 }
 625
 626 bool
 627 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 628 {
 629    switch (type) {
 630    case BRW_REGISTER_TYPE_D:
 631    case BRW_REGISTER_TYPE_UD:
 632       reg->dw1.d = -reg->dw1.d;
 633       return true;
 634    case BRW_REGISTER_TYPE_W:
 635    case BRW_REGISTER_TYPE_UW:
 636       reg->dw1.d = -(int16_t)reg->dw1.ud;
 637       return true;
 638    case BRW_REGISTER_TYPE_F:
 639       reg->dw1.f = -reg->dw1.f;
 640       return true;
 641    case BRW_REGISTER_TYPE_VF:
 642       reg->dw1.ud ^= 0x80808080;
 643       return true;
 644    case BRW_REGISTER_TYPE_UB:
 645    case BRW_REGISTER_TYPE_B:
 646       unreachable("no UB/B immediates");
 647    case BRW_REGISTER_TYPE_UV:
 648    case BRW_REGISTER_TYPE_V:
 649       assert(!"unimplemented: negate UV/V immediate");
 650    case BRW_REGISTER_TYPE_UQ:
 651    case BRW_REGISTER_TYPE_Q:
 652       assert(!"unimplemented: negate UQ/Q immediate");
 653    case BRW_REGISTER_TYPE_DF:
 654    case BRW_REGISTER_TYPE_HF:
 655       assert(!"unimplemented: negate DF/HF immediate");
 656    }
 657
 658    return false;
 659 }
 660
 661 bool
 662 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 663 {
 664    switch (type) {
 665    case BRW_REGISTER_TYPE_D:
 666       reg->dw1.d = abs(reg->dw1.d);
 667       return true;
 668    case BRW_REGISTER_TYPE_W:
 669       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 670       return true;
 671    case BRW_REGISTER_TYPE_F:
 672       reg->dw1.f = fabsf(reg->dw1.f);
 673       return true;
 674    case BRW_REGISTER_TYPE_VF:
 675       reg->dw1.ud &= ~0x80808080;
 676       return true;
 677    case BRW_REGISTER_TYPE_UB:
 678    case BRW_REGISTER_TYPE_B:
 679       unreachable("no UB/B immediates");
 680    case BRW_REGISTER_TYPE_UQ:
 681    case BRW_REGISTER_TYPE_UD:
 682    case BRW_REGISTER_TYPE_UW:
 683    case BRW_REGISTER_TYPE_UV:
 684       /* Presumably the absolute value modifier on an unsigned source is a
 685        * nop, but it would be nice to confirm.
 686        */
 687       assert(!"unimplemented: abs unsigned immediate");
 688    case BRW_REGISTER_TYPE_V:
 689       assert(!"unimplemented: abs V immediate");
 690    case BRW_REGISTER_TYPE_Q:
 691       assert(!"unimplemented: abs Q immediate");
 692    case BRW_REGISTER_TYPE_DF:
 693    case BRW_REGISTER_TYPE_HF:
 694       assert(!"unimplemented: abs DF/HF immediate");
 695    }
 696
 697    return false;
 698 }
 699
 700 backend_visitor::backend_visitor(struct brw_context *brw,
 701                                  struct gl_shader_program *shader_prog,
 702                                  struct gl_program *prog,
 703                                  struct brw_stage_prog_data *stage_prog_data,
 704                                  gl_shader_stage stage)
 705    : brw(brw),
 706      ctx(&brw->ctx),
 707      shader(shader_prog ?
 708         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 709      shader_prog(shader_prog),
 710      prog(prog),
 711      stage_prog_data(stage_prog_data),
 712      cfg(NULL),
 713      stage(stage)
 714 {
 715    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 716    stage_name = _mesa_shader_stage_to_string(stage);
 717    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 718 }
 719
 720 bool
 721 backend_reg::is_zero() const
 722 {
 723    if (file != IMM)
 724       return false;
 725
 726    return fixed_hw_reg.dw1.d == 0;
 727 }
 728
 729 bool
 730 backend_reg::is_one() const
 731 {
 732    if (file != IMM)
 733       return false;
 734
 735    return type == BRW_REGISTER_TYPE_F
 736           ? fixed_hw_reg.dw1.f == 1.0
 737           : fixed_hw_reg.dw1.d == 1;
 738 }
 739
 740 bool
 741 backend_reg::is_negative_one() const
 742 {
 743    if (file != IMM)
 744       return false;
 745
 746    switch (type) {
 747    case BRW_REGISTER_TYPE_F:
 748       return fixed_hw_reg.dw1.f == -1.0;
 749    case BRW_REGISTER_TYPE_D:
 750       return fixed_hw_reg.dw1.d == -1;
 751    default:
 752       return false;
 753    }
 754 }
 755
 756 bool
 757 backend_reg::is_null() const
 758 {
 759    return file == HW_REG &&
 760           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 761           fixed_hw_reg.nr == BRW_ARF_NULL;
 762 }
 763
 764
 765 bool
 766 backend_reg::is_accumulator() const
 767 {
 768    return file == HW_REG &&
 769           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 770           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 771 }
 772
 773 bool
 774 backend_instruction::is_3src() const
 775 {
 776    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 777 }
 778
 779 bool
 780 backend_instruction::is_tex() const
 781 {
 782    return (opcode == SHADER_OPCODE_TEX ||
 783            opcode == FS_OPCODE_TXB ||
 784            opcode == SHADER_OPCODE_TXD ||
 785            opcode == SHADER_OPCODE_TXF ||
 786            opcode == SHADER_OPCODE_TXF_CMS ||
 787            opcode == SHADER_OPCODE_TXF_UMS ||
 788            opcode == SHADER_OPCODE_TXF_MCS ||
 789            opcode == SHADER_OPCODE_TXL ||
 790            opcode == SHADER_OPCODE_TXS ||
 791            opcode == SHADER_OPCODE_LOD ||
 792            opcode == SHADER_OPCODE_TG4 ||
 793            opcode == SHADER_OPCODE_TG4_OFFSET);
 794 }
 795
 796 bool
 797 backend_instruction::is_math() const
 798 {
 799    return (opcode == SHADER_OPCODE_RCP ||
 800            opcode == SHADER_OPCODE_RSQ ||
 801            opcode == SHADER_OPCODE_SQRT ||
 802            opcode == SHADER_OPCODE_EXP2 ||
 803            opcode == SHADER_OPCODE_LOG2 ||
 804            opcode == SHADER_OPCODE_SIN ||
 805            opcode == SHADER_OPCODE_COS ||
 806            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 807            opcode == SHADER_OPCODE_INT_REMAINDER ||
 808            opcode == SHADER_OPCODE_POW);
 809 }
 810
 811 bool
 812 backend_instruction::is_control_flow() const
 813 {
 814    switch (opcode) {
 815    case BRW_OPCODE_DO:
 816    case BRW_OPCODE_WHILE:
 817    case BRW_OPCODE_IF:
 818    case BRW_OPCODE_ELSE:
 819    case BRW_OPCODE_ENDIF:
 820    case BRW_OPCODE_BREAK:
 821    case BRW_OPCODE_CONTINUE:
 822       return true;
 823    default:
 824       return false;
 825    }
 826 }
 827
 828 bool
 829 backend_instruction::can_do_source_mods() const
 830 {
 831    switch (opcode) {
 832    case BRW_OPCODE_ADDC:
 833    case BRW_OPCODE_BFE:
 834    case BRW_OPCODE_BFI1:
 835    case BRW_OPCODE_BFI2:
 836    case BRW_OPCODE_BFREV:
 837    case BRW_OPCODE_CBIT:
 838    case BRW_OPCODE_FBH:
 839    case BRW_OPCODE_FBL:
 840    case BRW_OPCODE_SUBB:
 841       return false;
 842    default:
 843       return true;
 844    }
 845 }
 846
 847 bool
 848 backend_instruction::can_do_saturate() const
 849 {
 850    switch (opcode) {
 851    case BRW_OPCODE_ADD:
 852    case BRW_OPCODE_ASR:
 853    case BRW_OPCODE_AVG:
 854    case BRW_OPCODE_DP2:
 855    case BRW_OPCODE_DP3:
 856    case BRW_OPCODE_DP4:
 857    case BRW_OPCODE_DPH:
 858    case BRW_OPCODE_F16TO32:
 859    case BRW_OPCODE_F32TO16:
 860    case BRW_OPCODE_LINE:
 861    case BRW_OPCODE_LRP:
 862    case BRW_OPCODE_MAC:
 863    case BRW_OPCODE_MACH:
 864    case BRW_OPCODE_MAD:
 865    case BRW_OPCODE_MATH:
 866    case BRW_OPCODE_MOV:
 867    case BRW_OPCODE_MUL:
 868    case BRW_OPCODE_PLN:
 869    case BRW_OPCODE_RNDD:
 870    case BRW_OPCODE_RNDE:
 871    case BRW_OPCODE_RNDU:
 872    case BRW_OPCODE_RNDZ:
 873    case BRW_OPCODE_SEL:
 874    case BRW_OPCODE_SHL:
 875    case BRW_OPCODE_SHR:
 876    case FS_OPCODE_LINTERP:
 877    case SHADER_OPCODE_COS:
 878    case SHADER_OPCODE_EXP2:
 879    case SHADER_OPCODE_LOG2:
 880    case SHADER_OPCODE_POW:
 881    case SHADER_OPCODE_RCP:
 882    case SHADER_OPCODE_RSQ:
 883    case SHADER_OPCODE_SIN:
 884    case SHADER_OPCODE_SQRT:
 885       return true;
 886    default:
 887       return false;
 888    }
 889 }
 890
 891 bool
 892 backend_instruction::can_do_cmod() const
 893 {
 894    switch (opcode) {
 895    case BRW_OPCODE_ADD:
 896    case BRW_OPCODE_ADDC:
 897    case BRW_OPCODE_AND:
 898    case BRW_OPCODE_ASR:
 899    case BRW_OPCODE_AVG:
 900    case BRW_OPCODE_CMP:
 901    case BRW_OPCODE_CMPN:
 902    case BRW_OPCODE_DP2:
 903    case BRW_OPCODE_DP3:
 904    case BRW_OPCODE_DP4:
 905    case BRW_OPCODE_DPH:
 906    case BRW_OPCODE_F16TO32:
 907    case BRW_OPCODE_F32TO16:
 908    case BRW_OPCODE_FRC:
 909    case BRW_OPCODE_LINE:
 910    case BRW_OPCODE_LRP:
 911    case BRW_OPCODE_LZD:
 912    case BRW_OPCODE_MAC:
 913    case BRW_OPCODE_MACH:
 914    case BRW_OPCODE_MAD:
 915    case BRW_OPCODE_MOV:
 916    case BRW_OPCODE_MUL:
 917    case BRW_OPCODE_NOT:
 918    case BRW_OPCODE_OR:
 919    case BRW_OPCODE_PLN:
 920    case BRW_OPCODE_RNDD:
 921    case BRW_OPCODE_RNDE:
 922    case BRW_OPCODE_RNDU:
 923    case BRW_OPCODE_RNDZ:
 924    case BRW_OPCODE_SAD2:
 925    case BRW_OPCODE_SADA2:
 926    case BRW_OPCODE_SHL:
 927    case BRW_OPCODE_SHR:
 928    case BRW_OPCODE_SUBB:
 929    case BRW_OPCODE_XOR:
 930    case FS_OPCODE_CINTERP:
 931    case FS_OPCODE_LINTERP:
 932       return true;
 933    default:
 934       return false;
 935    }
 936 }
 937
 938 bool
 939 backend_instruction::reads_accumulator_implicitly() const
 940 {
 941    switch (opcode) {
 942    case BRW_OPCODE_MAC:
 943    case BRW_OPCODE_MACH:
 944    case BRW_OPCODE_SADA2:
 945       return true;
 946    default:
 947       return false;
 948    }
 949 }
 950
 951 bool
 952 backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
 953 {
 954    return writes_accumulator ||
 955           (brw->gen < 6 &&
 956            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 957             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 958              opcode != FS_OPCODE_CINTERP)));
 959 }
 960
 961 bool
 962 backend_instruction::has_side_effects() const
 963 {
 964    switch (opcode) {
 965    case SHADER_OPCODE_UNTYPED_ATOMIC:
 966    case SHADER_OPCODE_URB_WRITE_SIMD8:
 967    case FS_OPCODE_FB_WRITE:
 968       return true;
 969    default:
 970       return false;
 971    }
 972 }
 973
 974 #ifndef NDEBUG
 975 static bool
 976 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 977 {
 978    bool found = false;
 979    foreach_inst_in_block (backend_instruction, i, block) {
 980       if (inst == i) {
 981          found = true;
 982       }
 983    }
 984    return found;
 985 }
 986 #endif
 987
 988 static void
 989 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 990 {
 991    for (bblock_t *block_iter = start_block->next();
 992         !block_iter->link.is_tail_sentinel();
 993         block_iter = block_iter->next()) {
 994       block_iter->start_ip += ip_adjustment;
 995       block_iter->end_ip += ip_adjustment;
 996    }
 997 }
 998
 999 void
1000 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1001 {
1002    if (!this->is_head_sentinel())
1003       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1004
1005    block->end_ip++;
1006
1007    adjust_later_block_ips(block, 1);
1008
1009    exec_node::insert_after(inst);
1010 }
1011
1012 void
1013 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1014 {
1015    if (!this->is_tail_sentinel())
1016       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1017
1018    block->end_ip++;
1019
1020    adjust_later_block_ips(block, 1);
1021
1022    exec_node::insert_before(inst);
1023 }
1024
1025 void
1026 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1027 {
1028    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1029
1030    unsigned num_inst = list->length();
1031
1032    block->end_ip += num_inst;
1033
1034    adjust_later_block_ips(block, num_inst);
1035
1036    exec_node::insert_before(list);
1037 }
1038
1039 void
1040 backend_instruction::remove(bblock_t *block)
1041 {
1042    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1043
1044    adjust_later_block_ips(block, -1);
1045
1046    if (block->start_ip == block->end_ip) {
1047       block->cfg->remove_block(block);
1048    } else {
1049       block->end_ip--;
1050    }
1051
1052    exec_node::remove();
1053 }
1054
1055 void
1056 backend_visitor::dump_instructions()
1057 {
1058    dump_instructions(NULL);
1059 }
1060
1061 void
1062 backend_visitor::dump_instructions(const char *name)
1063 {
1064    FILE *file = stderr;
1065    if (name && geteuid() != 0) {
1066       file = fopen(name, "w");
1067       if (!file)
1068          file = stderr;
1069    }
1070
1071    if (cfg) {
1072       int ip = 0;
1073       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1074          fprintf(file, "%4d: ", ip++);
1075          dump_instruction(inst, file);
1076       }
1077    } else {
1078       int ip = 0;
1079       foreach_in_list(backend_instruction, inst, &instructions) {
1080          fprintf(file, "%4d: ", ip++);
1081          dump_instruction(inst, file);
1082       }
1083    }
1084
1085    if (file != stderr) {
1086       fclose(file);
1087    }
1088 }
1089
1090 void
1091 backend_visitor::calculate_cfg()
1092 {
1093    if (this->cfg)
1094       return;
1095    cfg = new(mem_ctx) cfg_t(&this->instructions);
1096 }
1097
1098 void
1099 backend_visitor::invalidate_cfg()
1100 {
1101    ralloc_free(this->cfg);
1102    this->cfg = NULL;
1103 }
1104
1105 /**
1106  * Sets up the starting offsets for the groups of binding table entries
1107  * commong to all pipeline stages.
1108  *
1109  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1110  * unused but also make sure that addition of small offsets to them will
1111  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1112  */
1113 void
1114 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1115 {
1116    int num_textures = _mesa_fls(prog->SamplersUsed);
1117
1118    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1119    next_binding_table_offset += num_textures;
1120
1121    if (shader) {
1122       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1123       next_binding_table_offset += shader->base.NumUniformBlocks;
1124    } else {
1125       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1126    }
1127
1128    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1129       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1130       next_binding_table_offset++;
1131    } else {
1132       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1133    }
1134
1135    if (prog->UsesGather) {
1136       if (brw->gen >= 8) {
1137          stage_prog_data->binding_table.gather_texture_start =
1138             stage_prog_data->binding_table.texture_start;
1139       } else {
1140          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1141          next_binding_table_offset += num_textures;
1142       }
1143    } else {
1144       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1145    }
1146
1147    if (shader_prog && shader_prog->NumAtomicBuffers) {
1148       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1149       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1150    } else {
1151       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1152    }
1153
1154    if (shader && shader->base.NumImages) {
1155       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1156       next_binding_table_offset += shader->base.NumImages;
1157    } else {
1158       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1159    }
1160
1161    /* This may or may not be used depending on how the compile goes. */
1162    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1163    next_binding_table_offset++;
1164
1165    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1166
1167    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1168 }