src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "glsl/glsl_parser_extras.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32 #include "util/debug.h"
  33
  34 static void
  35 shader_debug_log_mesa(void *data, const char *fmt, ...)
  36 {
  37    struct brw_context *brw = (struct brw_context *)data;
  38    va_list args;
  39
  40    va_start(args, fmt);
  41    GLuint msg_id = 0;
  42    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  43                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  44                    MESA_DEBUG_TYPE_OTHER,
  45                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  46    va_end(args);
  47 }
  48
  49 static void
  50 shader_perf_log_mesa(void *data, const char *fmt, ...)
  51 {
  52    struct brw_context *brw = (struct brw_context *)data;
  53
  54    va_list args;
  55    va_start(args, fmt);
  56
  57    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  58       va_list args_copy;
  59       va_copy(args_copy, args);
  60       vfprintf(stderr, fmt, args_copy);
  61       va_end(args_copy);
  62    }
  63
  64    if (brw->perf_debug) {
  65       GLuint msg_id = 0;
  66       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  67                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  68                       MESA_DEBUG_TYPE_PERFORMANCE,
  69                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  70    }
  71    va_end(args);
  72 }
  73
  74 struct brw_compiler *
  75 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  76 {
  77    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  78
  79    compiler->devinfo = devinfo;
  80    compiler->shader_debug_log = shader_debug_log_mesa;
  81    compiler->shader_perf_log = shader_perf_log_mesa;
  82
  83    brw_fs_alloc_reg_sets(compiler);
  84    brw_vec4_alloc_reg_set(compiler);
  85
  86    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  87       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  88    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = false;
  89    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] = true;
  90    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  91       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  92    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  93    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  94
  95    nir_shader_compiler_options *nir_options =
  96       rzalloc(compiler, nir_shader_compiler_options);
  97    nir_options->native_integers = true;
  98    /* In order to help allow for better CSE at the NIR level we tell NIR
  99     * to split all ffma instructions during opt_algebraic and we then
 100     * re-combine them as a later step.
 101     */
 102    nir_options->lower_ffma = true;
 103    nir_options->lower_sub = true;
 104    nir_options->lower_fdiv = true;
 105
 106    /* In the vec4 backend, our dpN instruction replicates its result to all
 107     * the components of a vec4.  We would like NIR to give us replicated fdot
 108     * instructions because it can optimize better for us.
 109     *
 110     * For the FS backend, it should be lowered away by the scalarizing pass so
 111     * we should never see fdot anyway.
 112     */
 113    nir_options->fdot_replicates = true;
 114
 115    /* We want the GLSL compiler to emit code that uses condition codes */
 116    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 117       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 118       compiler->glsl_compiler_options[i].MaxIfDepth =
 119          devinfo->gen < 6 ? 16 : UINT_MAX;
 120
 121       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 122       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 123       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 124       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 125       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 126       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 127
 128       bool is_scalar = compiler->scalar_stage[i];
 129
 130       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 131       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 132       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 133
 134       /* !ARB_gpu_shader5 */
 135       if (devinfo->gen < 7)
 136          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 137
 138       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 139
 140       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 141    }
 142
 143    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 144    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 145
 146    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 147       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 148
 149    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 150       .LowerShaderSharedVariables = true;
 151
 152    return compiler;
 153 }
 154
 155 extern "C" struct gl_shader *
 156 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 157 {
 158    struct brw_shader *shader;
 159
 160    shader = rzalloc(NULL, struct brw_shader);
 161    if (shader) {
 162       shader->base.Type = type;
 163       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 164       shader->base.Name = name;
 165       _mesa_init_shader(ctx, &shader->base);
 166    }
 167
 168    return &shader->base;
 169 }
 170
 171 extern "C" void
 172 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 173                       unsigned surf_index)
 174 {
 175    assert(surf_index < BRW_MAX_SURFACES);
 176
 177    prog_data->binding_table.size_bytes =
 178       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 179 }
 180
 181 enum brw_reg_type
 182 brw_type_for_base_type(const struct glsl_type *type)
 183 {
 184    switch (type->base_type) {
 185    case GLSL_TYPE_FLOAT:
 186       return BRW_REGISTER_TYPE_F;
 187    case GLSL_TYPE_INT:
 188    case GLSL_TYPE_BOOL:
 189    case GLSL_TYPE_SUBROUTINE:
 190       return BRW_REGISTER_TYPE_D;
 191    case GLSL_TYPE_UINT:
 192       return BRW_REGISTER_TYPE_UD;
 193    case GLSL_TYPE_ARRAY:
 194       return brw_type_for_base_type(type->fields.array);
 195    case GLSL_TYPE_STRUCT:
 196    case GLSL_TYPE_SAMPLER:
 197    case GLSL_TYPE_ATOMIC_UINT:
 198       /* These should be overridden with the type of the member when
 199        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 200        * way to trip up if we don't.
 201        */
 202       return BRW_REGISTER_TYPE_UD;
 203    case GLSL_TYPE_IMAGE:
 204       return BRW_REGISTER_TYPE_UD;
 205    case GLSL_TYPE_VOID:
 206    case GLSL_TYPE_ERROR:
 207    case GLSL_TYPE_INTERFACE:
 208    case GLSL_TYPE_DOUBLE:
 209    case GLSL_TYPE_FUNCTION:
 210       unreachable("not reached");
 211    }
 212
 213    return BRW_REGISTER_TYPE_F;
 214 }
 215
 216 enum brw_conditional_mod
 217 brw_conditional_for_comparison(unsigned int op)
 218 {
 219    switch (op) {
 220    case ir_binop_less:
 221       return BRW_CONDITIONAL_L;
 222    case ir_binop_greater:
 223       return BRW_CONDITIONAL_G;
 224    case ir_binop_lequal:
 225       return BRW_CONDITIONAL_LE;
 226    case ir_binop_gequal:
 227       return BRW_CONDITIONAL_GE;
 228    case ir_binop_equal:
 229    case ir_binop_all_equal: /* same as equal for scalars */
 230       return BRW_CONDITIONAL_Z;
 231    case ir_binop_nequal:
 232    case ir_binop_any_nequal: /* same as nequal for scalars */
 233       return BRW_CONDITIONAL_NZ;
 234    default:
 235       unreachable("not reached: bad operation for comparison");
 236    }
 237 }
 238
 239 uint32_t
 240 brw_math_function(enum opcode op)
 241 {
 242    switch (op) {
 243    case SHADER_OPCODE_RCP:
 244       return BRW_MATH_FUNCTION_INV;
 245    case SHADER_OPCODE_RSQ:
 246       return BRW_MATH_FUNCTION_RSQ;
 247    case SHADER_OPCODE_SQRT:
 248       return BRW_MATH_FUNCTION_SQRT;
 249    case SHADER_OPCODE_EXP2:
 250       return BRW_MATH_FUNCTION_EXP;
 251    case SHADER_OPCODE_LOG2:
 252       return BRW_MATH_FUNCTION_LOG;
 253    case SHADER_OPCODE_POW:
 254       return BRW_MATH_FUNCTION_POW;
 255    case SHADER_OPCODE_SIN:
 256       return BRW_MATH_FUNCTION_SIN;
 257    case SHADER_OPCODE_COS:
 258       return BRW_MATH_FUNCTION_COS;
 259    case SHADER_OPCODE_INT_QUOTIENT:
 260       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 261    case SHADER_OPCODE_INT_REMAINDER:
 262       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 263    default:
 264       unreachable("not reached: unknown math function");
 265    }
 266 }
 267
 268 uint32_t
 269 brw_texture_offset(int *offsets, unsigned num_components)
 270 {
 271    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 272
 273    /* Combine all three offsets into a single unsigned dword:
 274     *
 275     *    bits 11:8 - U Offset (X component)
 276     *    bits  7:4 - V Offset (Y component)
 277     *    bits  3:0 - R Offset (Z component)
 278     */
 279    unsigned offset_bits = 0;
 280    for (unsigned i = 0; i < num_components; i++) {
 281       const unsigned shift = 4 * (2 - i);
 282       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 283    }
 284    return offset_bits;
 285 }
 286
 287 const char *
 288 brw_instruction_name(enum opcode op)
 289 {
 290    switch (op) {
 291    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 292       assert(opcode_descs[op].name);
 293       return opcode_descs[op].name;
 294    case FS_OPCODE_FB_WRITE:
 295       return "fb_write";
 296    case FS_OPCODE_FB_WRITE_LOGICAL:
 297       return "fb_write_logical";
 298    case FS_OPCODE_PACK_STENCIL_REF:
 299       return "pack_stencil_ref";
 300    case FS_OPCODE_BLORP_FB_WRITE:
 301       return "blorp_fb_write";
 302    case FS_OPCODE_REP_FB_WRITE:
 303       return "rep_fb_write";
 304
 305    case SHADER_OPCODE_RCP:
 306       return "rcp";
 307    case SHADER_OPCODE_RSQ:
 308       return "rsq";
 309    case SHADER_OPCODE_SQRT:
 310       return "sqrt";
 311    case SHADER_OPCODE_EXP2:
 312       return "exp2";
 313    case SHADER_OPCODE_LOG2:
 314       return "log2";
 315    case SHADER_OPCODE_POW:
 316       return "pow";
 317    case SHADER_OPCODE_INT_QUOTIENT:
 318       return "int_quot";
 319    case SHADER_OPCODE_INT_REMAINDER:
 320       return "int_rem";
 321    case SHADER_OPCODE_SIN:
 322       return "sin";
 323    case SHADER_OPCODE_COS:
 324       return "cos";
 325
 326    case SHADER_OPCODE_TEX:
 327       return "tex";
 328    case SHADER_OPCODE_TEX_LOGICAL:
 329       return "tex_logical";
 330    case SHADER_OPCODE_TXD:
 331       return "txd";
 332    case SHADER_OPCODE_TXD_LOGICAL:
 333       return "txd_logical";
 334    case SHADER_OPCODE_TXF:
 335       return "txf";
 336    case SHADER_OPCODE_TXF_LOGICAL:
 337       return "txf_logical";
 338    case SHADER_OPCODE_TXL:
 339       return "txl";
 340    case SHADER_OPCODE_TXL_LOGICAL:
 341       return "txl_logical";
 342    case SHADER_OPCODE_TXS:
 343       return "txs";
 344    case SHADER_OPCODE_TXS_LOGICAL:
 345       return "txs_logical";
 346    case FS_OPCODE_TXB:
 347       return "txb";
 348    case FS_OPCODE_TXB_LOGICAL:
 349       return "txb_logical";
 350    case SHADER_OPCODE_TXF_CMS:
 351       return "txf_cms";
 352    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 353       return "txf_cms_logical";
 354    case SHADER_OPCODE_TXF_CMS_W:
 355       return "txf_cms_w";
 356    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 357       return "txf_cms_w_logical";
 358    case SHADER_OPCODE_TXF_UMS:
 359       return "txf_ums";
 360    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 361       return "txf_ums_logical";
 362    case SHADER_OPCODE_TXF_MCS:
 363       return "txf_mcs";
 364    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 365       return "txf_mcs_logical";
 366    case SHADER_OPCODE_LOD:
 367       return "lod";
 368    case SHADER_OPCODE_LOD_LOGICAL:
 369       return "lod_logical";
 370    case SHADER_OPCODE_TG4:
 371       return "tg4";
 372    case SHADER_OPCODE_TG4_LOGICAL:
 373       return "tg4_logical";
 374    case SHADER_OPCODE_TG4_OFFSET:
 375       return "tg4_offset";
 376    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 377       return "tg4_offset_logical";
 378    case SHADER_OPCODE_SAMPLEINFO:
 379       return "sampleinfo";
 380
 381    case SHADER_OPCODE_SHADER_TIME_ADD:
 382       return "shader_time_add";
 383
 384    case SHADER_OPCODE_UNTYPED_ATOMIC:
 385       return "untyped_atomic";
 386    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 387       return "untyped_atomic_logical";
 388    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 389       return "untyped_surface_read";
 390    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 391       return "untyped_surface_read_logical";
 392    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 393       return "untyped_surface_write";
 394    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 395       return "untyped_surface_write_logical";
 396    case SHADER_OPCODE_TYPED_ATOMIC:
 397       return "typed_atomic";
 398    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 399       return "typed_atomic_logical";
 400    case SHADER_OPCODE_TYPED_SURFACE_READ:
 401       return "typed_surface_read";
 402    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 403       return "typed_surface_read_logical";
 404    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 405       return "typed_surface_write";
 406    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 407       return "typed_surface_write_logical";
 408    case SHADER_OPCODE_MEMORY_FENCE:
 409       return "memory_fence";
 410
 411    case SHADER_OPCODE_LOAD_PAYLOAD:
 412       return "load_payload";
 413
 414    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 415       return "gen4_scratch_read";
 416    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 417       return "gen4_scratch_write";
 418    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 419       return "gen7_scratch_read";
 420    case SHADER_OPCODE_URB_WRITE_SIMD8:
 421       return "gen8_urb_write_simd8";
 422    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 423       return "gen8_urb_write_simd8_per_slot";
 424    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 425       return "gen8_urb_write_simd8_masked";
 426    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 427       return "gen8_urb_write_simd8_masked_per_slot";
 428    case SHADER_OPCODE_URB_READ_SIMD8:
 429       return "urb_read_simd8";
 430    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 431       return "urb_read_simd8_per_slot";
 432
 433    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 434       return "find_live_channel";
 435    case SHADER_OPCODE_BROADCAST:
 436       return "broadcast";
 437
 438    case VEC4_OPCODE_MOV_BYTES:
 439       return "mov_bytes";
 440    case VEC4_OPCODE_PACK_BYTES:
 441       return "pack_bytes";
 442    case VEC4_OPCODE_UNPACK_UNIFORM:
 443       return "unpack_uniform";
 444
 445    case FS_OPCODE_DDX_COARSE:
 446       return "ddx_coarse";
 447    case FS_OPCODE_DDX_FINE:
 448       return "ddx_fine";
 449    case FS_OPCODE_DDY_COARSE:
 450       return "ddy_coarse";
 451    case FS_OPCODE_DDY_FINE:
 452       return "ddy_fine";
 453
 454    case FS_OPCODE_CINTERP:
 455       return "cinterp";
 456    case FS_OPCODE_LINTERP:
 457       return "linterp";
 458
 459    case FS_OPCODE_PIXEL_X:
 460       return "pixel_x";
 461    case FS_OPCODE_PIXEL_Y:
 462       return "pixel_y";
 463
 464    case FS_OPCODE_GET_BUFFER_SIZE:
 465       return "fs_get_buffer_size";
 466
 467    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 468       return "uniform_pull_const";
 469    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 470       return "uniform_pull_const_gen7";
 471    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 472       return "varying_pull_const";
 473    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 474       return "varying_pull_const_gen7";
 475
 476    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 477       return "mov_dispatch_to_flags";
 478    case FS_OPCODE_DISCARD_JUMP:
 479       return "discard_jump";
 480
 481    case FS_OPCODE_SET_SAMPLE_ID:
 482       return "set_sample_id";
 483    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 484       return "set_simd4x2_offset";
 485
 486    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 487       return "pack_half_2x16_split";
 488    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 489       return "unpack_half_2x16_split_x";
 490    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 491       return "unpack_half_2x16_split_y";
 492
 493    case FS_OPCODE_PLACEHOLDER_HALT:
 494       return "placeholder_halt";
 495
 496    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 497       return "interp_centroid";
 498    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 499       return "interp_sample";
 500    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 501       return "interp_shared_offset";
 502    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 503       return "interp_per_slot_offset";
 504
 505    case VS_OPCODE_URB_WRITE:
 506       return "vs_urb_write";
 507    case VS_OPCODE_PULL_CONSTANT_LOAD:
 508       return "pull_constant_load";
 509    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 510       return "pull_constant_load_gen7";
 511
 512    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 513       return "set_simd4x2_header_gen9";
 514
 515    case VS_OPCODE_GET_BUFFER_SIZE:
 516       return "vs_get_buffer_size";
 517
 518    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 519       return "unpack_flags_simd4x2";
 520
 521    case GS_OPCODE_URB_WRITE:
 522       return "gs_urb_write";
 523    case GS_OPCODE_URB_WRITE_ALLOCATE:
 524       return "gs_urb_write_allocate";
 525    case GS_OPCODE_THREAD_END:
 526       return "gs_thread_end";
 527    case GS_OPCODE_SET_WRITE_OFFSET:
 528       return "set_write_offset";
 529    case GS_OPCODE_SET_VERTEX_COUNT:
 530       return "set_vertex_count";
 531    case GS_OPCODE_SET_DWORD_2:
 532       return "set_dword_2";
 533    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 534       return "prepare_channel_masks";
 535    case GS_OPCODE_SET_CHANNEL_MASKS:
 536       return "set_channel_masks";
 537    case GS_OPCODE_GET_INSTANCE_ID:
 538       return "get_instance_id";
 539    case GS_OPCODE_FF_SYNC:
 540       return "ff_sync";
 541    case GS_OPCODE_SET_PRIMITIVE_ID:
 542       return "set_primitive_id";
 543    case GS_OPCODE_SVB_WRITE:
 544       return "gs_svb_write";
 545    case GS_OPCODE_SVB_SET_DST_INDEX:
 546       return "gs_svb_set_dst_index";
 547    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 548       return "gs_ff_sync_set_primitives";
 549    case CS_OPCODE_CS_TERMINATE:
 550       return "cs_terminate";
 551    case SHADER_OPCODE_BARRIER:
 552       return "barrier";
 553    case SHADER_OPCODE_MULH:
 554       return "mulh";
 555    case SHADER_OPCODE_MOV_INDIRECT:
 556       return "mov_indirect";
 557
 558    case VEC4_OPCODE_URB_READ:
 559       return "urb_read";
 560    case TCS_OPCODE_GET_INSTANCE_ID:
 561       return "tcs_get_instance_id";
 562    case TCS_OPCODE_URB_WRITE:
 563       return "tcs_urb_write";
 564    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 565       return "tcs_set_input_urb_offsets";
 566    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 567       return "tcs_set_output_urb_offsets";
 568    case TCS_OPCODE_GET_PRIMITIVE_ID:
 569       return "tcs_get_primitive_id";
 570    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 571       return "tcs_create_barrier_header";
 572    }
 573
 574    unreachable("not reached");
 575 }
 576
 577 bool
 578 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 579 {
 580    union {
 581       unsigned ud;
 582       int d;
 583       float f;
 584    } imm = { reg->ud }, sat_imm = { 0 };
 585
 586    switch (type) {
 587    case BRW_REGISTER_TYPE_UD:
 588    case BRW_REGISTER_TYPE_D:
 589    case BRW_REGISTER_TYPE_UW:
 590    case BRW_REGISTER_TYPE_W:
 591    case BRW_REGISTER_TYPE_UQ:
 592    case BRW_REGISTER_TYPE_Q:
 593       /* Nothing to do. */
 594       return false;
 595    case BRW_REGISTER_TYPE_F:
 596       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 597       break;
 598    case BRW_REGISTER_TYPE_UB:
 599    case BRW_REGISTER_TYPE_B:
 600       unreachable("no UB/B immediates");
 601    case BRW_REGISTER_TYPE_V:
 602    case BRW_REGISTER_TYPE_UV:
 603    case BRW_REGISTER_TYPE_VF:
 604       unreachable("unimplemented: saturate vector immediate");
 605    case BRW_REGISTER_TYPE_DF:
 606    case BRW_REGISTER_TYPE_HF:
 607       unreachable("unimplemented: saturate DF/HF immediate");
 608    }
 609
 610    if (imm.ud != sat_imm.ud) {
 611       reg->ud = sat_imm.ud;
 612       return true;
 613    }
 614    return false;
 615 }
 616
 617 bool
 618 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 619 {
 620    switch (type) {
 621    case BRW_REGISTER_TYPE_D:
 622    case BRW_REGISTER_TYPE_UD:
 623       reg->d = -reg->d;
 624       return true;
 625    case BRW_REGISTER_TYPE_W:
 626    case BRW_REGISTER_TYPE_UW:
 627       reg->d = -(int16_t)reg->ud;
 628       return true;
 629    case BRW_REGISTER_TYPE_F:
 630       reg->f = -reg->f;
 631       return true;
 632    case BRW_REGISTER_TYPE_VF:
 633       reg->ud ^= 0x80808080;
 634       return true;
 635    case BRW_REGISTER_TYPE_UB:
 636    case BRW_REGISTER_TYPE_B:
 637       unreachable("no UB/B immediates");
 638    case BRW_REGISTER_TYPE_UV:
 639    case BRW_REGISTER_TYPE_V:
 640       assert(!"unimplemented: negate UV/V immediate");
 641    case BRW_REGISTER_TYPE_UQ:
 642    case BRW_REGISTER_TYPE_Q:
 643       assert(!"unimplemented: negate UQ/Q immediate");
 644    case BRW_REGISTER_TYPE_DF:
 645    case BRW_REGISTER_TYPE_HF:
 646       assert(!"unimplemented: negate DF/HF immediate");
 647    }
 648
 649    return false;
 650 }
 651
 652 bool
 653 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 654 {
 655    switch (type) {
 656    case BRW_REGISTER_TYPE_D:
 657       reg->d = abs(reg->d);
 658       return true;
 659    case BRW_REGISTER_TYPE_W:
 660       reg->d = abs((int16_t)reg->ud);
 661       return true;
 662    case BRW_REGISTER_TYPE_F:
 663       reg->f = fabsf(reg->f);
 664       return true;
 665    case BRW_REGISTER_TYPE_VF:
 666       reg->ud &= ~0x80808080;
 667       return true;
 668    case BRW_REGISTER_TYPE_UB:
 669    case BRW_REGISTER_TYPE_B:
 670       unreachable("no UB/B immediates");
 671    case BRW_REGISTER_TYPE_UQ:
 672    case BRW_REGISTER_TYPE_UD:
 673    case BRW_REGISTER_TYPE_UW:
 674    case BRW_REGISTER_TYPE_UV:
 675       /* Presumably the absolute value modifier on an unsigned source is a
 676        * nop, but it would be nice to confirm.
 677        */
 678       assert(!"unimplemented: abs unsigned immediate");
 679    case BRW_REGISTER_TYPE_V:
 680       assert(!"unimplemented: abs V immediate");
 681    case BRW_REGISTER_TYPE_Q:
 682       assert(!"unimplemented: abs Q immediate");
 683    case BRW_REGISTER_TYPE_DF:
 684    case BRW_REGISTER_TYPE_HF:
 685       assert(!"unimplemented: abs DF/HF immediate");
 686    }
 687
 688    return false;
 689 }
 690
 691 backend_shader::backend_shader(const struct brw_compiler *compiler,
 692                                void *log_data,
 693                                void *mem_ctx,
 694                                const nir_shader *shader,
 695                                struct brw_stage_prog_data *stage_prog_data)
 696    : compiler(compiler),
 697      log_data(log_data),
 698      devinfo(compiler->devinfo),
 699      nir(shader),
 700      stage_prog_data(stage_prog_data),
 701      mem_ctx(mem_ctx),
 702      cfg(NULL),
 703      stage(shader->stage)
 704 {
 705    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 706    stage_name = _mesa_shader_stage_to_string(stage);
 707    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 708 }
 709
 710 bool
 711 backend_reg::equals(const backend_reg &r) const
 712 {
 713    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 714           reg_offset == r.reg_offset;
 715 }
 716
 717 bool
 718 backend_reg::is_zero() const
 719 {
 720    if (file != IMM)
 721       return false;
 722
 723    return d == 0;
 724 }
 725
 726 bool
 727 backend_reg::is_one() const
 728 {
 729    if (file != IMM)
 730       return false;
 731
 732    return type == BRW_REGISTER_TYPE_F
 733           ? f == 1.0
 734           : d == 1;
 735 }
 736
 737 bool
 738 backend_reg::is_negative_one() const
 739 {
 740    if (file != IMM)
 741       return false;
 742
 743    switch (type) {
 744    case BRW_REGISTER_TYPE_F:
 745       return f == -1.0;
 746    case BRW_REGISTER_TYPE_D:
 747       return d == -1;
 748    default:
 749       return false;
 750    }
 751 }
 752
 753 bool
 754 backend_reg::is_null() const
 755 {
 756    return file == ARF && nr == BRW_ARF_NULL;
 757 }
 758
 759
 760 bool
 761 backend_reg::is_accumulator() const
 762 {
 763    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 764 }
 765
 766 bool
 767 backend_reg::in_range(const backend_reg &r, unsigned n) const
 768 {
 769    return (file == r.file &&
 770            nr == r.nr &&
 771            reg_offset >= r.reg_offset &&
 772            reg_offset < r.reg_offset + n);
 773 }
 774
 775 bool
 776 backend_instruction::is_commutative() const
 777 {
 778    switch (opcode) {
 779    case BRW_OPCODE_AND:
 780    case BRW_OPCODE_OR:
 781    case BRW_OPCODE_XOR:
 782    case BRW_OPCODE_ADD:
 783    case BRW_OPCODE_MUL:
 784    case SHADER_OPCODE_MULH:
 785       return true;
 786    case BRW_OPCODE_SEL:
 787       /* MIN and MAX are commutative. */
 788       if (conditional_mod == BRW_CONDITIONAL_GE ||
 789           conditional_mod == BRW_CONDITIONAL_L) {
 790          return true;
 791       }
 792       /* fallthrough */
 793    default:
 794       return false;
 795    }
 796 }
 797
 798 bool
 799 backend_instruction::is_3src() const
 800 {
 801    return ::is_3src(opcode);
 802 }
 803
 804 bool
 805 backend_instruction::is_tex() const
 806 {
 807    return (opcode == SHADER_OPCODE_TEX ||
 808            opcode == FS_OPCODE_TXB ||
 809            opcode == SHADER_OPCODE_TXD ||
 810            opcode == SHADER_OPCODE_TXF ||
 811            opcode == SHADER_OPCODE_TXF_CMS ||
 812            opcode == SHADER_OPCODE_TXF_CMS_W ||
 813            opcode == SHADER_OPCODE_TXF_UMS ||
 814            opcode == SHADER_OPCODE_TXF_MCS ||
 815            opcode == SHADER_OPCODE_TXL ||
 816            opcode == SHADER_OPCODE_TXS ||
 817            opcode == SHADER_OPCODE_LOD ||
 818            opcode == SHADER_OPCODE_TG4 ||
 819            opcode == SHADER_OPCODE_TG4_OFFSET);
 820 }
 821
 822 bool
 823 backend_instruction::is_math() const
 824 {
 825    return (opcode == SHADER_OPCODE_RCP ||
 826            opcode == SHADER_OPCODE_RSQ ||
 827            opcode == SHADER_OPCODE_SQRT ||
 828            opcode == SHADER_OPCODE_EXP2 ||
 829            opcode == SHADER_OPCODE_LOG2 ||
 830            opcode == SHADER_OPCODE_SIN ||
 831            opcode == SHADER_OPCODE_COS ||
 832            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 833            opcode == SHADER_OPCODE_INT_REMAINDER ||
 834            opcode == SHADER_OPCODE_POW);
 835 }
 836
 837 bool
 838 backend_instruction::is_control_flow() const
 839 {
 840    switch (opcode) {
 841    case BRW_OPCODE_DO:
 842    case BRW_OPCODE_WHILE:
 843    case BRW_OPCODE_IF:
 844    case BRW_OPCODE_ELSE:
 845    case BRW_OPCODE_ENDIF:
 846    case BRW_OPCODE_BREAK:
 847    case BRW_OPCODE_CONTINUE:
 848       return true;
 849    default:
 850       return false;
 851    }
 852 }
 853
 854 bool
 855 backend_instruction::can_do_source_mods() const
 856 {
 857    switch (opcode) {
 858    case BRW_OPCODE_ADDC:
 859    case BRW_OPCODE_BFE:
 860    case BRW_OPCODE_BFI1:
 861    case BRW_OPCODE_BFI2:
 862    case BRW_OPCODE_BFREV:
 863    case BRW_OPCODE_CBIT:
 864    case BRW_OPCODE_FBH:
 865    case BRW_OPCODE_FBL:
 866    case BRW_OPCODE_SUBB:
 867       return false;
 868    default:
 869       return true;
 870    }
 871 }
 872
 873 bool
 874 backend_instruction::can_do_saturate() const
 875 {
 876    switch (opcode) {
 877    case BRW_OPCODE_ADD:
 878    case BRW_OPCODE_ASR:
 879    case BRW_OPCODE_AVG:
 880    case BRW_OPCODE_DP2:
 881    case BRW_OPCODE_DP3:
 882    case BRW_OPCODE_DP4:
 883    case BRW_OPCODE_DPH:
 884    case BRW_OPCODE_F16TO32:
 885    case BRW_OPCODE_F32TO16:
 886    case BRW_OPCODE_LINE:
 887    case BRW_OPCODE_LRP:
 888    case BRW_OPCODE_MAC:
 889    case BRW_OPCODE_MAD:
 890    case BRW_OPCODE_MATH:
 891    case BRW_OPCODE_MOV:
 892    case BRW_OPCODE_MUL:
 893    case SHADER_OPCODE_MULH:
 894    case BRW_OPCODE_PLN:
 895    case BRW_OPCODE_RNDD:
 896    case BRW_OPCODE_RNDE:
 897    case BRW_OPCODE_RNDU:
 898    case BRW_OPCODE_RNDZ:
 899    case BRW_OPCODE_SEL:
 900    case BRW_OPCODE_SHL:
 901    case BRW_OPCODE_SHR:
 902    case FS_OPCODE_LINTERP:
 903    case SHADER_OPCODE_COS:
 904    case SHADER_OPCODE_EXP2:
 905    case SHADER_OPCODE_LOG2:
 906    case SHADER_OPCODE_POW:
 907    case SHADER_OPCODE_RCP:
 908    case SHADER_OPCODE_RSQ:
 909    case SHADER_OPCODE_SIN:
 910    case SHADER_OPCODE_SQRT:
 911       return true;
 912    default:
 913       return false;
 914    }
 915 }
 916
 917 bool
 918 backend_instruction::can_do_cmod() const
 919 {
 920    switch (opcode) {
 921    case BRW_OPCODE_ADD:
 922    case BRW_OPCODE_ADDC:
 923    case BRW_OPCODE_AND:
 924    case BRW_OPCODE_ASR:
 925    case BRW_OPCODE_AVG:
 926    case BRW_OPCODE_CMP:
 927    case BRW_OPCODE_CMPN:
 928    case BRW_OPCODE_DP2:
 929    case BRW_OPCODE_DP3:
 930    case BRW_OPCODE_DP4:
 931    case BRW_OPCODE_DPH:
 932    case BRW_OPCODE_F16TO32:
 933    case BRW_OPCODE_F32TO16:
 934    case BRW_OPCODE_FRC:
 935    case BRW_OPCODE_LINE:
 936    case BRW_OPCODE_LRP:
 937    case BRW_OPCODE_LZD:
 938    case BRW_OPCODE_MAC:
 939    case BRW_OPCODE_MACH:
 940    case BRW_OPCODE_MAD:
 941    case BRW_OPCODE_MOV:
 942    case BRW_OPCODE_MUL:
 943    case BRW_OPCODE_NOT:
 944    case BRW_OPCODE_OR:
 945    case BRW_OPCODE_PLN:
 946    case BRW_OPCODE_RNDD:
 947    case BRW_OPCODE_RNDE:
 948    case BRW_OPCODE_RNDU:
 949    case BRW_OPCODE_RNDZ:
 950    case BRW_OPCODE_SAD2:
 951    case BRW_OPCODE_SADA2:
 952    case BRW_OPCODE_SHL:
 953    case BRW_OPCODE_SHR:
 954    case BRW_OPCODE_SUBB:
 955    case BRW_OPCODE_XOR:
 956    case FS_OPCODE_CINTERP:
 957    case FS_OPCODE_LINTERP:
 958       return true;
 959    default:
 960       return false;
 961    }
 962 }
 963
 964 bool
 965 backend_instruction::reads_accumulator_implicitly() const
 966 {
 967    switch (opcode) {
 968    case BRW_OPCODE_MAC:
 969    case BRW_OPCODE_MACH:
 970    case BRW_OPCODE_SADA2:
 971       return true;
 972    default:
 973       return false;
 974    }
 975 }
 976
 977 bool
 978 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 979 {
 980    return writes_accumulator ||
 981           (devinfo->gen < 6 &&
 982            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 983             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 984              opcode != FS_OPCODE_CINTERP)));
 985 }
 986
 987 bool
 988 backend_instruction::has_side_effects() const
 989 {
 990    switch (opcode) {
 991    case SHADER_OPCODE_UNTYPED_ATOMIC:
 992    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 993    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 994    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 995    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 996    case SHADER_OPCODE_TYPED_ATOMIC:
 997    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 998    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 999    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1000    case SHADER_OPCODE_MEMORY_FENCE:
1001    case SHADER_OPCODE_URB_WRITE_SIMD8:
1002    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1003    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1004    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1005    case FS_OPCODE_FB_WRITE:
1006    case SHADER_OPCODE_BARRIER:
1007       return true;
1008    default:
1009       return false;
1010    }
1011 }
1012
1013 bool
1014 backend_instruction::is_volatile() const
1015 {
1016    switch (opcode) {
1017    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1018    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1019    case SHADER_OPCODE_TYPED_SURFACE_READ:
1020    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1021       return true;
1022    default:
1023       return false;
1024    }
1025 }
1026
1027 #ifndef NDEBUG
1028 static bool
1029 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1030 {
1031    bool found = false;
1032    foreach_inst_in_block (backend_instruction, i, block) {
1033       if (inst == i) {
1034          found = true;
1035       }
1036    }
1037    return found;
1038 }
1039 #endif
1040
1041 static void
1042 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1043 {
1044    for (bblock_t *block_iter = start_block->next();
1045         !block_iter->link.is_tail_sentinel();
1046         block_iter = block_iter->next()) {
1047       block_iter->start_ip += ip_adjustment;
1048       block_iter->end_ip += ip_adjustment;
1049    }
1050 }
1051
1052 void
1053 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1054 {
1055    if (!this->is_head_sentinel())
1056       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1057
1058    block->end_ip++;
1059
1060    adjust_later_block_ips(block, 1);
1061
1062    exec_node::insert_after(inst);
1063 }
1064
1065 void
1066 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1067 {
1068    if (!this->is_tail_sentinel())
1069       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1070
1071    block->end_ip++;
1072
1073    adjust_later_block_ips(block, 1);
1074
1075    exec_node::insert_before(inst);
1076 }
1077
1078 void
1079 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1080 {
1081    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1082
1083    unsigned num_inst = list->length();
1084
1085    block->end_ip += num_inst;
1086
1087    adjust_later_block_ips(block, num_inst);
1088
1089    exec_node::insert_before(list);
1090 }
1091
1092 void
1093 backend_instruction::remove(bblock_t *block)
1094 {
1095    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1096
1097    adjust_later_block_ips(block, -1);
1098
1099    if (block->start_ip == block->end_ip) {
1100       block->cfg->remove_block(block);
1101    } else {
1102       block->end_ip--;
1103    }
1104
1105    exec_node::remove();
1106 }
1107
1108 void
1109 backend_shader::dump_instructions()
1110 {
1111    dump_instructions(NULL);
1112 }
1113
1114 void
1115 backend_shader::dump_instructions(const char *name)
1116 {
1117    FILE *file = stderr;
1118    if (name && geteuid() != 0) {
1119       file = fopen(name, "w");
1120       if (!file)
1121          file = stderr;
1122    }
1123
1124    if (cfg) {
1125       int ip = 0;
1126       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1127          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1128             fprintf(file, "%4d: ", ip++);
1129          dump_instruction(inst, file);
1130       }
1131    } else {
1132       int ip = 0;
1133       foreach_in_list(backend_instruction, inst, &instructions) {
1134          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1135             fprintf(file, "%4d: ", ip++);
1136          dump_instruction(inst, file);
1137       }
1138    }
1139
1140    if (file != stderr) {
1141       fclose(file);
1142    }
1143 }
1144
1145 void
1146 backend_shader::calculate_cfg()
1147 {
1148    if (this->cfg)
1149       return;
1150    cfg = new(mem_ctx) cfg_t(&this->instructions);
1151 }
1152
1153 void
1154 backend_shader::invalidate_cfg()
1155 {
1156    ralloc_free(this->cfg);
1157    this->cfg = NULL;
1158 }
1159
1160 /**
1161  * Sets up the starting offsets for the groups of binding table entries
1162  * commong to all pipeline stages.
1163  *
1164  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1165  * unused but also make sure that addition of small offsets to them will
1166  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1167  */
1168 void
1169 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1170                                         const struct brw_device_info *devinfo,
1171                                         const struct gl_shader_program *shader_prog,
1172                                         const struct gl_program *prog,
1173                                         struct brw_stage_prog_data *stage_prog_data,
1174                                         uint32_t next_binding_table_offset)
1175 {
1176    const struct gl_shader *shader = NULL;
1177    int num_textures = _mesa_fls(prog->SamplersUsed);
1178
1179    if (shader_prog)
1180       shader = shader_prog->_LinkedShaders[stage];
1181
1182    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1183    next_binding_table_offset += num_textures;
1184
1185    if (shader) {
1186       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1187       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1188       next_binding_table_offset += shader->NumUniformBlocks;
1189
1190       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1191       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1192       next_binding_table_offset += shader->NumShaderStorageBlocks;
1193    } else {
1194       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1195       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1196    }
1197
1198    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1199       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1200       next_binding_table_offset++;
1201    } else {
1202       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1203    }
1204
1205    if (prog->UsesGather) {
1206       if (devinfo->gen >= 8) {
1207          stage_prog_data->binding_table.gather_texture_start =
1208             stage_prog_data->binding_table.texture_start;
1209       } else {
1210          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1211          next_binding_table_offset += num_textures;
1212       }
1213    } else {
1214       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1215    }
1216
1217    if (shader && shader->NumAtomicBuffers) {
1218       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1219       next_binding_table_offset += shader->NumAtomicBuffers;
1220    } else {
1221       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1222    }
1223
1224    if (shader && shader->NumImages) {
1225       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1226       next_binding_table_offset += shader->NumImages;
1227    } else {
1228       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1229    }
1230
1231    /* This may or may not be used depending on how the compile goes. */
1232    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1233    next_binding_table_offset++;
1234
1235    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1236
1237    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1238 }
1239
1240 static void
1241 setup_vec4_uniform_value(const gl_constant_value **params,
1242                          const gl_constant_value *values,
1243                          unsigned n)
1244 {
1245    static const gl_constant_value zero = { 0 };
1246
1247    for (unsigned i = 0; i < n; ++i)
1248       params[i] = &values[i];
1249
1250    for (unsigned i = n; i < 4; ++i)
1251       params[i] = &zero;
1252 }
1253
1254 void
1255 brw_setup_image_uniform_values(gl_shader_stage stage,
1256                                struct brw_stage_prog_data *stage_prog_data,
1257                                unsigned param_start_index,
1258                                const gl_uniform_storage *storage)
1259 {
1260    const gl_constant_value **param =
1261       &stage_prog_data->param[param_start_index];
1262
1263    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1264       const unsigned image_idx = storage->opaque[stage].index + i;
1265       const brw_image_param *image_param =
1266          &stage_prog_data->image_param[image_idx];
1267
1268       /* Upload the brw_image_param structure.  The order is expected to match
1269        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1270        */
1271       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1272          (const gl_constant_value *)&image_param->surface_idx, 1);
1273       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1274          (const gl_constant_value *)image_param->offset, 2);
1275       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1276          (const gl_constant_value *)image_param->size, 3);
1277       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1278          (const gl_constant_value *)image_param->stride, 4);
1279       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1280          (const gl_constant_value *)image_param->tiling, 3);
1281       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1282          (const gl_constant_value *)image_param->swizzling, 2);
1283       param += BRW_IMAGE_PARAM_SIZE;
1284
1285       brw_mark_surface_used(
1286          stage_prog_data,
1287          stage_prog_data->binding_table.image_start + image_idx);
1288    }
1289 }
1290
1291 /**
1292  * Decide which set of clip planes should be used when clipping via
1293  * gl_Position or gl_ClipVertex.
1294  */
1295 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1296 {
1297    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1298       /* There is currently a GLSL vertex shader, so clip according to GLSL
1299        * rules, which means compare gl_ClipVertex (or gl_Position, if
1300        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1301        * that were stored in EyeUserPlane at the time the clip planes were
1302        * specified.
1303        */
1304       return ctx->Transform.EyeUserPlane;
1305    } else {
1306       /* Either we are using fixed function or an ARB vertex program.  In
1307        * either case the clip planes are going to be compared against
1308        * gl_Position (which is in clip coordinates) so we have to clip using
1309        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1310        * core.
1311        */
1312       return ctx->Transform._ClipUserPlane;
1313    }
1314 }
1315
1316 extern "C" const unsigned *
1317 brw_compile_tes(const struct brw_compiler *compiler,
1318                 void *log_data,
1319                 void *mem_ctx,
1320                 const struct brw_tes_prog_key *key,
1321                 struct brw_tes_prog_data *prog_data,
1322                 const nir_shader *src_shader,
1323                 struct gl_shader_program *shader_prog,
1324                 int shader_time_index,
1325                 unsigned *final_assembly_size,
1326                 char **error_str)
1327 {
1328    const struct brw_device_info *devinfo = compiler->devinfo;
1329    struct gl_shader *shader =
1330       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1331    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1332
1333    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1334    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1335    nir->info.inputs_read = key->inputs_read;
1336    nir->info.patch_inputs_read = key->patch_inputs_read;
1337    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
1338    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1339
1340    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1341                        nir->info.outputs_written,
1342                        nir->info.separate_shader);
1343
1344    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1345
1346    assert(output_size_bytes >= 1);
1347    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1348       if (error_str)
1349          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1350       return NULL;
1351    }
1352
1353    /* URB entry sizes are stored as a multiple of 64 bytes. */
1354    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1355
1356    struct brw_vue_map input_vue_map;
1357    brw_compute_tess_vue_map(&input_vue_map,
1358                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1359                             nir->info.patch_inputs_read);
1360
1361    bool need_patch_header = nir->info.system_values_read &
1362       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1363        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1364
1365    /* The TES will pull most inputs using URB read messages.
1366     *
1367     * However, we push the patch header for TessLevel factors when required,
1368     * as it's a tiny amount of extra data.
1369     */
1370    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1371
1372    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1373       fprintf(stderr, "TES Input ");
1374       brw_print_vue_map(stderr, &input_vue_map);
1375       fprintf(stderr, "TES Output ");
1376       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1377    }
1378
1379    if (is_scalar) {
1380       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1381                    &prog_data->base.base, shader->Program, nir, 8,
1382                    shader_time_index, &input_vue_map);
1383       if (!v.run_tes()) {
1384          if (error_str)
1385             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1386          return NULL;
1387       }
1388
1389       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1390
1391       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1392                      &prog_data->base.base, v.promoted_constants, false,
1393                      "TES");
1394       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1395          g.enable_debug(ralloc_asprintf(mem_ctx,
1396                                         "%s tessellation evaluation shader %s",
1397                                         nir->info.label ? nir->info.label
1398                                                         : "unnamed",
1399                                         nir->info.name));
1400       }
1401
1402       g.generate_code(v.cfg, 8);
1403
1404       return g.get_assembly(final_assembly_size);
1405    } else {
1406       unreachable("XXX: vec4 tessellation evalation shaders not merged yet.");
1407    }
1408 }