src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "glsl/ir_optimization.h"
  31 #include "glsl/glsl_parser_extras.h"
  32 #include "main/shaderapi.h"
  33
  34 struct gl_shader *
  35 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  36 {
  37    struct brw_shader *shader;
  38
  39    shader = rzalloc(NULL, struct brw_shader);
  40    if (shader) {
  41       shader->base.Type = type;
  42       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  43       shader->base.Name = name;
  44       _mesa_init_shader(ctx, &shader->base);
  45    }
  46
  47    return &shader->base;
  48 }
  49
  50 /**
  51  * Performs a compile of the shader stages even when we don't know
  52  * what non-orthogonal state will be set, in the hope that it reflects
  53  * the eventual NOS used, and thus allows us to produce link failures.
  54  */
  55 static bool
  56 brw_shader_precompile(struct gl_context *ctx,
  57                       struct gl_shader_program *sh_prog)
  58 {
  59    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  60    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  61    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  62
  63    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  64       return false;
  65
  66    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  67       return false;
  68
  69    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  70       return false;
  71
  72    return true;
  73 }
  74
  75 static inline bool
  76 is_scalar_shader_stage(struct brw_context *brw, int stage)
  77 {
  78    switch (stage) {
  79    case MESA_SHADER_FRAGMENT:
  80       return true;
  81    case MESA_SHADER_VERTEX:
  82       return brw->scalar_vs;
  83    default:
  84       return false;
  85    }
  86 }
  87
  88 static void
  89 brw_lower_packing_builtins(struct brw_context *brw,
  90                            gl_shader_stage shader_type,
  91                            exec_list *ir)
  92 {
  93    int ops = LOWER_PACK_SNORM_2x16
  94            | LOWER_UNPACK_SNORM_2x16
  95            | LOWER_PACK_UNORM_2x16
  96            | LOWER_UNPACK_UNORM_2x16;
  97
  98    if (is_scalar_shader_stage(brw, shader_type)) {
  99       ops |= LOWER_UNPACK_UNORM_4x8
 100            | LOWER_UNPACK_SNORM_4x8
 101            | LOWER_PACK_UNORM_4x8
 102            | LOWER_PACK_SNORM_4x8;
 103    }
 104
 105    if (brw->gen >= 7) {
 106       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 107        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 108        * lowering is needed. For SOA code, the Half2x16 ops must be
 109        * scalarized.
 110        */
 111       if (is_scalar_shader_stage(brw, shader_type)) {
 112          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 113              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 114       }
 115    } else {
 116       ops |= LOWER_PACK_HALF_2x16
 117           |  LOWER_UNPACK_HALF_2x16;
 118    }
 119
 120    lower_packing_builtins(ir, ops);
 121 }
 122
 123 static void
 124 process_glsl_ir(struct brw_context *brw,
 125                 struct gl_shader_program *shader_prog,
 126                 struct gl_shader *shader)
 127 {
 128    struct gl_context *ctx = &brw->ctx;
 129    const struct gl_shader_compiler_options *options =
 130       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 131
 132    /* Temporary memory context for any new IR. */
 133    void *mem_ctx = ralloc_context(NULL);
 134
 135    ralloc_adopt(mem_ctx, shader->ir);
 136
 137    /* lower_packing_builtins() inserts arithmetic instructions, so it
 138     * must precede lower_instructions().
 139     */
 140    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 141    do_mat_op_to_vec(shader->ir);
 142    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 143    lower_instructions(shader->ir,
 144                       MOD_TO_FLOOR |
 145                       DIV_TO_MUL_RCP |
 146                       SUB_TO_ADD_NEG |
 147                       EXP_TO_EXP2 |
 148                       LOG_TO_LOG2 |
 149                       bitfield_insert |
 150                       LDEXP_TO_ARITH);
 151
 152    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 153     * if-statements need to be flattened.
 154     */
 155    if (brw->gen < 6)
 156       lower_if_to_cond_assign(shader->ir, 16);
 157
 158    do_lower_texture_projection(shader->ir);
 159    brw_lower_texture_gradients(brw, shader->ir);
 160    do_vec_index_to_cond_assign(shader->ir);
 161    lower_vector_insert(shader->ir, true);
 162    if (options->NirOptions == NULL)
 163       brw_do_cubemap_normalize(shader->ir);
 164    lower_offset_arrays(shader->ir);
 165    brw_do_lower_unnormalized_offset(shader->ir);
 166    lower_noise(shader->ir);
 167    lower_quadop_vector(shader->ir, false);
 168
 169    bool lowered_variable_indexing =
 170       lower_variable_index_to_cond_assign(shader->ir,
 171                                           options->EmitNoIndirectInput,
 172                                           options->EmitNoIndirectOutput,
 173                                           options->EmitNoIndirectTemp,
 174                                           options->EmitNoIndirectUniform);
 175
 176    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 177       perf_debug("Unsupported form of variable indexing in FS; falling "
 178                  "back to very inefficient code generation\n");
 179    }
 180
 181    lower_ubo_reference(shader, shader->ir);
 182
 183    bool progress;
 184    do {
 185       progress = false;
 186
 187       if (is_scalar_shader_stage(brw, shader->Stage)) {
 188          brw_do_channel_expressions(shader->ir);
 189          brw_do_vector_splitting(shader->ir);
 190       }
 191
 192       progress = do_lower_jumps(shader->ir, true, true,
 193                                 true, /* main return */
 194                                 false, /* continue */
 195                                 false /* loops */
 196                                 ) || progress;
 197
 198       progress = do_common_optimization(shader->ir, true, true,
 199                                         options, ctx->Const.NativeIntegers) || progress;
 200    } while (progress);
 201
 202    if (options->NirOptions != NULL)
 203       lower_output_reads(shader->ir);
 204
 205    validate_ir_tree(shader->ir);
 206
 207    /* Now that we've finished altering the linked IR, reparent any live IR back
 208     * to the permanent memory context, and free the temporary one (discarding any
 209     * junk we optimized away).
 210     */
 211    reparent_ir(shader->ir, shader->ir);
 212    ralloc_free(mem_ctx);
 213
 214    if (ctx->_Shader->Flags & GLSL_DUMP) {
 215       fprintf(stderr, "\n");
 216       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 217               _mesa_shader_stage_to_string(shader->Stage),
 218               shader_prog->Name);
 219       _mesa_print_ir(stderr, shader->ir, NULL);
 220       fprintf(stderr, "\n");
 221    }
 222 }
 223
 224 GLboolean
 225 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 226 {
 227    struct brw_context *brw = brw_context(ctx);
 228    unsigned int stage;
 229
 230    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 231       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 232
 233       if (!shader)
 234          continue;
 235
 236       struct gl_program *prog =
 237          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 238                                 shader->Name);
 239       if (!prog)
 240         return false;
 241       prog->Parameters = _mesa_new_parameter_list();
 242
 243       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 244
 245       process_glsl_ir(brw, shProg, shader);
 246
 247       /* Make a pass over the IR to add state references for any built-in
 248        * uniforms that are used.  This has to be done now (during linking).
 249        * Code generation doesn't happen until the first time this shader is
 250        * used for rendering.  Waiting until then to generate the parameters is
 251        * too late.  At that point, the values for the built-in uniforms won't
 252        * get sent to the shader.
 253        */
 254       foreach_in_list(ir_instruction, node, shader->ir) {
 255          ir_variable *var = node->as_variable();
 256
 257          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 258              || (strncmp(var->name, "gl_", 3) != 0))
 259             continue;
 260
 261          const ir_state_slot *const slots = var->get_state_slots();
 262          assert(slots != NULL);
 263
 264          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 265             _mesa_add_state_reference(prog->Parameters,
 266                                       (gl_state_index *) slots[i].tokens);
 267          }
 268       }
 269
 270       do_set_program_inouts(shader->ir, prog, shader->Stage);
 271
 272       prog->SamplersUsed = shader->active_samplers;
 273       prog->ShadowSamplers = shader->shadow_samplers;
 274       _mesa_update_shader_textures_used(shProg, prog);
 275
 276       _mesa_reference_program(ctx, &shader->Program, prog);
 277
 278       brw_add_texrect_params(prog);
 279
 280       _mesa_reference_program(ctx, &prog, NULL);
 281    }
 282
 283    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 284       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 285          const struct gl_shader *sh = shProg->Shaders[i];
 286          if (!sh)
 287             continue;
 288
 289          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 290                  _mesa_shader_stage_to_string(sh->Stage),
 291                  i, shProg->Name);
 292          fprintf(stderr, "%s", sh->Source);
 293          fprintf(stderr, "\n");
 294       }
 295    }
 296
 297    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 298       return false;
 299
 300    return true;
 301 }
 302
 303
 304 enum brw_reg_type
 305 brw_type_for_base_type(const struct glsl_type *type)
 306 {
 307    switch (type->base_type) {
 308    case GLSL_TYPE_FLOAT:
 309       return BRW_REGISTER_TYPE_F;
 310    case GLSL_TYPE_INT:
 311    case GLSL_TYPE_BOOL:
 312       return BRW_REGISTER_TYPE_D;
 313    case GLSL_TYPE_UINT:
 314       return BRW_REGISTER_TYPE_UD;
 315    case GLSL_TYPE_ARRAY:
 316       return brw_type_for_base_type(type->fields.array);
 317    case GLSL_TYPE_STRUCT:
 318    case GLSL_TYPE_SAMPLER:
 319    case GLSL_TYPE_ATOMIC_UINT:
 320       /* These should be overridden with the type of the member when
 321        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 322        * way to trip up if we don't.
 323        */
 324       return BRW_REGISTER_TYPE_UD;
 325    case GLSL_TYPE_IMAGE:
 326       return BRW_REGISTER_TYPE_UD;
 327    case GLSL_TYPE_VOID:
 328    case GLSL_TYPE_ERROR:
 329    case GLSL_TYPE_INTERFACE:
 330    case GLSL_TYPE_DOUBLE:
 331       unreachable("not reached");
 332    }
 333
 334    return BRW_REGISTER_TYPE_F;
 335 }
 336
 337 enum brw_conditional_mod
 338 brw_conditional_for_comparison(unsigned int op)
 339 {
 340    switch (op) {
 341    case ir_binop_less:
 342       return BRW_CONDITIONAL_L;
 343    case ir_binop_greater:
 344       return BRW_CONDITIONAL_G;
 345    case ir_binop_lequal:
 346       return BRW_CONDITIONAL_LE;
 347    case ir_binop_gequal:
 348       return BRW_CONDITIONAL_GE;
 349    case ir_binop_equal:
 350    case ir_binop_all_equal: /* same as equal for scalars */
 351       return BRW_CONDITIONAL_Z;
 352    case ir_binop_nequal:
 353    case ir_binop_any_nequal: /* same as nequal for scalars */
 354       return BRW_CONDITIONAL_NZ;
 355    default:
 356       unreachable("not reached: bad operation for comparison");
 357    }
 358 }
 359
 360 uint32_t
 361 brw_math_function(enum opcode op)
 362 {
 363    switch (op) {
 364    case SHADER_OPCODE_RCP:
 365       return BRW_MATH_FUNCTION_INV;
 366    case SHADER_OPCODE_RSQ:
 367       return BRW_MATH_FUNCTION_RSQ;
 368    case SHADER_OPCODE_SQRT:
 369       return BRW_MATH_FUNCTION_SQRT;
 370    case SHADER_OPCODE_EXP2:
 371       return BRW_MATH_FUNCTION_EXP;
 372    case SHADER_OPCODE_LOG2:
 373       return BRW_MATH_FUNCTION_LOG;
 374    case SHADER_OPCODE_POW:
 375       return BRW_MATH_FUNCTION_POW;
 376    case SHADER_OPCODE_SIN:
 377       return BRW_MATH_FUNCTION_SIN;
 378    case SHADER_OPCODE_COS:
 379       return BRW_MATH_FUNCTION_COS;
 380    case SHADER_OPCODE_INT_QUOTIENT:
 381       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 382    case SHADER_OPCODE_INT_REMAINDER:
 383       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 384    default:
 385       unreachable("not reached: unknown math function");
 386    }
 387 }
 388
 389 uint32_t
 390 brw_texture_offset(struct gl_context *ctx, int *offsets,
 391                    unsigned num_components)
 392 {
 393    /* If the driver does not support GL_ARB_gpu_shader5, the offset
 394     * must be constant.
 395     */
 396    assert(offsets != NULL || ctx->Extensions.ARB_gpu_shader5);
 397
 398    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 399
 400    /* Combine all three offsets into a single unsigned dword:
 401     *
 402     *    bits 11:8 - U Offset (X component)
 403     *    bits  7:4 - V Offset (Y component)
 404     *    bits  3:0 - R Offset (Z component)
 405     */
 406    unsigned offset_bits = 0;
 407    for (unsigned i = 0; i < num_components; i++) {
 408       const unsigned shift = 4 * (2 - i);
 409       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 410    }
 411    return offset_bits;
 412 }
 413
 414 const char *
 415 brw_instruction_name(enum opcode op)
 416 {
 417    switch (op) {
 418    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 419       assert(opcode_descs[op].name);
 420       return opcode_descs[op].name;
 421    case FS_OPCODE_FB_WRITE:
 422       return "fb_write";
 423    case FS_OPCODE_BLORP_FB_WRITE:
 424       return "blorp_fb_write";
 425    case FS_OPCODE_REP_FB_WRITE:
 426       return "rep_fb_write";
 427
 428    case SHADER_OPCODE_RCP:
 429       return "rcp";
 430    case SHADER_OPCODE_RSQ:
 431       return "rsq";
 432    case SHADER_OPCODE_SQRT:
 433       return "sqrt";
 434    case SHADER_OPCODE_EXP2:
 435       return "exp2";
 436    case SHADER_OPCODE_LOG2:
 437       return "log2";
 438    case SHADER_OPCODE_POW:
 439       return "pow";
 440    case SHADER_OPCODE_INT_QUOTIENT:
 441       return "int_quot";
 442    case SHADER_OPCODE_INT_REMAINDER:
 443       return "int_rem";
 444    case SHADER_OPCODE_SIN:
 445       return "sin";
 446    case SHADER_OPCODE_COS:
 447       return "cos";
 448
 449    case SHADER_OPCODE_TEX:
 450       return "tex";
 451    case SHADER_OPCODE_TXD:
 452       return "txd";
 453    case SHADER_OPCODE_TXF:
 454       return "txf";
 455    case SHADER_OPCODE_TXL:
 456       return "txl";
 457    case SHADER_OPCODE_TXS:
 458       return "txs";
 459    case FS_OPCODE_TXB:
 460       return "txb";
 461    case SHADER_OPCODE_TXF_CMS:
 462       return "txf_cms";
 463    case SHADER_OPCODE_TXF_UMS:
 464       return "txf_ums";
 465    case SHADER_OPCODE_TXF_MCS:
 466       return "txf_mcs";
 467    case SHADER_OPCODE_LOD:
 468       return "lod";
 469    case SHADER_OPCODE_TG4:
 470       return "tg4";
 471    case SHADER_OPCODE_TG4_OFFSET:
 472       return "tg4_offset";
 473    case SHADER_OPCODE_SHADER_TIME_ADD:
 474       return "shader_time_add";
 475
 476    case SHADER_OPCODE_UNTYPED_ATOMIC:
 477       return "untyped_atomic";
 478    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 479       return "untyped_surface_read";
 480
 481    case SHADER_OPCODE_LOAD_PAYLOAD:
 482       return "load_payload";
 483
 484    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 485       return "gen4_scratch_read";
 486    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 487       return "gen4_scratch_write";
 488    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 489       return "gen7_scratch_read";
 490    case SHADER_OPCODE_URB_WRITE_SIMD8:
 491       return "gen8_urb_write_simd8";
 492
 493    case VEC4_OPCODE_MOV_BYTES:
 494       return "mov_bytes";
 495    case VEC4_OPCODE_PACK_BYTES:
 496       return "pack_bytes";
 497    case VEC4_OPCODE_UNPACK_UNIFORM:
 498       return "unpack_uniform";
 499
 500    case FS_OPCODE_DDX_COARSE:
 501       return "ddx_coarse";
 502    case FS_OPCODE_DDX_FINE:
 503       return "ddx_fine";
 504    case FS_OPCODE_DDY_COARSE:
 505       return "ddy_coarse";
 506    case FS_OPCODE_DDY_FINE:
 507       return "ddy_fine";
 508
 509    case FS_OPCODE_PIXEL_X:
 510       return "pixel_x";
 511    case FS_OPCODE_PIXEL_Y:
 512       return "pixel_y";
 513
 514    case FS_OPCODE_CINTERP:
 515       return "cinterp";
 516    case FS_OPCODE_LINTERP:
 517       return "linterp";
 518
 519    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 520       return "uniform_pull_const";
 521    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 522       return "uniform_pull_const_gen7";
 523    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 524       return "varying_pull_const";
 525    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 526       return "varying_pull_const_gen7";
 527
 528    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 529       return "mov_dispatch_to_flags";
 530    case FS_OPCODE_DISCARD_JUMP:
 531       return "discard_jump";
 532
 533    case FS_OPCODE_SET_OMASK:
 534       return "set_omask";
 535    case FS_OPCODE_SET_SAMPLE_ID:
 536       return "set_sample_id";
 537    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 538       return "set_simd4x2_offset";
 539
 540    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 541       return "pack_half_2x16_split";
 542    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 543       return "unpack_half_2x16_split_x";
 544    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 545       return "unpack_half_2x16_split_y";
 546
 547    case FS_OPCODE_PLACEHOLDER_HALT:
 548       return "placeholder_halt";
 549
 550    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 551       return "interp_centroid";
 552    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 553       return "interp_sample";
 554    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 555       return "interp_shared_offset";
 556    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 557       return "interp_per_slot_offset";
 558
 559    case VS_OPCODE_URB_WRITE:
 560       return "vs_urb_write";
 561    case VS_OPCODE_PULL_CONSTANT_LOAD:
 562       return "pull_constant_load";
 563    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 564       return "pull_constant_load_gen7";
 565    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 566       return "unpack_flags_simd4x2";
 567
 568    case GS_OPCODE_URB_WRITE:
 569       return "gs_urb_write";
 570    case GS_OPCODE_URB_WRITE_ALLOCATE:
 571       return "gs_urb_write_allocate";
 572    case GS_OPCODE_THREAD_END:
 573       return "gs_thread_end";
 574    case GS_OPCODE_SET_WRITE_OFFSET:
 575       return "set_write_offset";
 576    case GS_OPCODE_SET_VERTEX_COUNT:
 577       return "set_vertex_count";
 578    case GS_OPCODE_SET_DWORD_2:
 579       return "set_dword_2";
 580    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 581       return "prepare_channel_masks";
 582    case GS_OPCODE_SET_CHANNEL_MASKS:
 583       return "set_channel_masks";
 584    case GS_OPCODE_GET_INSTANCE_ID:
 585       return "get_instance_id";
 586    case GS_OPCODE_FF_SYNC:
 587       return "ff_sync";
 588    case GS_OPCODE_SET_PRIMITIVE_ID:
 589       return "set_primitive_id";
 590    case GS_OPCODE_SVB_WRITE:
 591       return "gs_svb_write";
 592    case GS_OPCODE_SVB_SET_DST_INDEX:
 593       return "gs_svb_set_dst_index";
 594    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 595       return "gs_ff_sync_set_primitives";
 596    }
 597
 598    unreachable("not reached");
 599 }
 600
 601 bool
 602 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 603 {
 604    union {
 605       unsigned ud;
 606       int d;
 607       float f;
 608    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 609
 610    switch (type) {
 611    case BRW_REGISTER_TYPE_UD:
 612    case BRW_REGISTER_TYPE_D:
 613    case BRW_REGISTER_TYPE_UQ:
 614    case BRW_REGISTER_TYPE_Q:
 615       /* Nothing to do. */
 616       return false;
 617    case BRW_REGISTER_TYPE_UW:
 618       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 619       break;
 620    case BRW_REGISTER_TYPE_W:
 621       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 622       break;
 623    case BRW_REGISTER_TYPE_F:
 624       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 625       break;
 626    case BRW_REGISTER_TYPE_UB:
 627    case BRW_REGISTER_TYPE_B:
 628       unreachable("no UB/B immediates");
 629    case BRW_REGISTER_TYPE_V:
 630    case BRW_REGISTER_TYPE_UV:
 631    case BRW_REGISTER_TYPE_VF:
 632       unreachable("unimplemented: saturate vector immediate");
 633    case BRW_REGISTER_TYPE_DF:
 634    case BRW_REGISTER_TYPE_HF:
 635       unreachable("unimplemented: saturate DF/HF immediate");
 636    }
 637
 638    if (imm.ud != sat_imm.ud) {
 639       reg->dw1.ud = sat_imm.ud;
 640       return true;
 641    }
 642    return false;
 643 }
 644
 645 bool
 646 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 647 {
 648    switch (type) {
 649    case BRW_REGISTER_TYPE_D:
 650    case BRW_REGISTER_TYPE_UD:
 651       reg->dw1.d = -reg->dw1.d;
 652       return true;
 653    case BRW_REGISTER_TYPE_W:
 654    case BRW_REGISTER_TYPE_UW:
 655       reg->dw1.d = -(int16_t)reg->dw1.ud;
 656       return true;
 657    case BRW_REGISTER_TYPE_F:
 658       reg->dw1.f = -reg->dw1.f;
 659       return true;
 660    case BRW_REGISTER_TYPE_VF:
 661       reg->dw1.ud ^= 0x80808080;
 662       return true;
 663    case BRW_REGISTER_TYPE_UB:
 664    case BRW_REGISTER_TYPE_B:
 665       unreachable("no UB/B immediates");
 666    case BRW_REGISTER_TYPE_UV:
 667    case BRW_REGISTER_TYPE_V:
 668       assert(!"unimplemented: negate UV/V immediate");
 669    case BRW_REGISTER_TYPE_UQ:
 670    case BRW_REGISTER_TYPE_Q:
 671       assert(!"unimplemented: negate UQ/Q immediate");
 672    case BRW_REGISTER_TYPE_DF:
 673    case BRW_REGISTER_TYPE_HF:
 674       assert(!"unimplemented: negate DF/HF immediate");
 675    }
 676
 677    return false;
 678 }
 679
 680 bool
 681 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 682 {
 683    switch (type) {
 684    case BRW_REGISTER_TYPE_D:
 685       reg->dw1.d = abs(reg->dw1.d);
 686       return true;
 687    case BRW_REGISTER_TYPE_W:
 688       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 689       return true;
 690    case BRW_REGISTER_TYPE_F:
 691       reg->dw1.f = fabsf(reg->dw1.f);
 692       return true;
 693    case BRW_REGISTER_TYPE_VF:
 694       reg->dw1.ud &= ~0x80808080;
 695       return true;
 696    case BRW_REGISTER_TYPE_UB:
 697    case BRW_REGISTER_TYPE_B:
 698       unreachable("no UB/B immediates");
 699    case BRW_REGISTER_TYPE_UQ:
 700    case BRW_REGISTER_TYPE_UD:
 701    case BRW_REGISTER_TYPE_UW:
 702    case BRW_REGISTER_TYPE_UV:
 703       /* Presumably the absolute value modifier on an unsigned source is a
 704        * nop, but it would be nice to confirm.
 705        */
 706       assert(!"unimplemented: abs unsigned immediate");
 707    case BRW_REGISTER_TYPE_V:
 708       assert(!"unimplemented: abs V immediate");
 709    case BRW_REGISTER_TYPE_Q:
 710       assert(!"unimplemented: abs Q immediate");
 711    case BRW_REGISTER_TYPE_DF:
 712    case BRW_REGISTER_TYPE_HF:
 713       assert(!"unimplemented: abs DF/HF immediate");
 714    }
 715
 716    return false;
 717 }
 718
 719 backend_visitor::backend_visitor(struct brw_context *brw,
 720                                  struct gl_shader_program *shader_prog,
 721                                  struct gl_program *prog,
 722                                  struct brw_stage_prog_data *stage_prog_data,
 723                                  gl_shader_stage stage)
 724    : brw(brw),
 725      ctx(&brw->ctx),
 726      shader(shader_prog ?
 727         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 728      shader_prog(shader_prog),
 729      prog(prog),
 730      stage_prog_data(stage_prog_data),
 731      cfg(NULL),
 732      stage(stage)
 733 {
 734    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 735    stage_name = _mesa_shader_stage_to_string(stage);
 736    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 737 }
 738
 739 bool
 740 backend_reg::is_zero() const
 741 {
 742    if (file != IMM)
 743       return false;
 744
 745    return fixed_hw_reg.dw1.d == 0;
 746 }
 747
 748 bool
 749 backend_reg::is_one() const
 750 {
 751    if (file != IMM)
 752       return false;
 753
 754    return type == BRW_REGISTER_TYPE_F
 755           ? fixed_hw_reg.dw1.f == 1.0
 756           : fixed_hw_reg.dw1.d == 1;
 757 }
 758
 759 bool
 760 backend_reg::is_negative_one() const
 761 {
 762    if (file != IMM)
 763       return false;
 764
 765    switch (type) {
 766    case BRW_REGISTER_TYPE_F:
 767       return fixed_hw_reg.dw1.f == -1.0;
 768    case BRW_REGISTER_TYPE_D:
 769       return fixed_hw_reg.dw1.d == -1;
 770    default:
 771       return false;
 772    }
 773 }
 774
 775 bool
 776 backend_reg::is_null() const
 777 {
 778    return file == HW_REG &&
 779           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 780           fixed_hw_reg.nr == BRW_ARF_NULL;
 781 }
 782
 783
 784 bool
 785 backend_reg::is_accumulator() const
 786 {
 787    return file == HW_REG &&
 788           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 789           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 790 }
 791
 792 bool
 793 backend_reg::in_range(const backend_reg &r, unsigned n) const
 794 {
 795    return (file == r.file &&
 796            reg == r.reg &&
 797            reg_offset >= r.reg_offset &&
 798            reg_offset < r.reg_offset + n);
 799 }
 800
 801 bool
 802 backend_instruction::is_commutative() const
 803 {
 804    switch (opcode) {
 805    case BRW_OPCODE_AND:
 806    case BRW_OPCODE_OR:
 807    case BRW_OPCODE_XOR:
 808    case BRW_OPCODE_ADD:
 809    case BRW_OPCODE_MUL:
 810       return true;
 811    case BRW_OPCODE_SEL:
 812       /* MIN and MAX are commutative. */
 813       if (conditional_mod == BRW_CONDITIONAL_GE ||
 814           conditional_mod == BRW_CONDITIONAL_L) {
 815          return true;
 816       }
 817       /* fallthrough */
 818    default:
 819       return false;
 820    }
 821 }
 822
 823 bool
 824 backend_instruction::is_3src() const
 825 {
 826    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 827 }
 828
 829 bool
 830 backend_instruction::is_tex() const
 831 {
 832    return (opcode == SHADER_OPCODE_TEX ||
 833            opcode == FS_OPCODE_TXB ||
 834            opcode == SHADER_OPCODE_TXD ||
 835            opcode == SHADER_OPCODE_TXF ||
 836            opcode == SHADER_OPCODE_TXF_CMS ||
 837            opcode == SHADER_OPCODE_TXF_UMS ||
 838            opcode == SHADER_OPCODE_TXF_MCS ||
 839            opcode == SHADER_OPCODE_TXL ||
 840            opcode == SHADER_OPCODE_TXS ||
 841            opcode == SHADER_OPCODE_LOD ||
 842            opcode == SHADER_OPCODE_TG4 ||
 843            opcode == SHADER_OPCODE_TG4_OFFSET);
 844 }
 845
 846 bool
 847 backend_instruction::is_math() const
 848 {
 849    return (opcode == SHADER_OPCODE_RCP ||
 850            opcode == SHADER_OPCODE_RSQ ||
 851            opcode == SHADER_OPCODE_SQRT ||
 852            opcode == SHADER_OPCODE_EXP2 ||
 853            opcode == SHADER_OPCODE_LOG2 ||
 854            opcode == SHADER_OPCODE_SIN ||
 855            opcode == SHADER_OPCODE_COS ||
 856            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 857            opcode == SHADER_OPCODE_INT_REMAINDER ||
 858            opcode == SHADER_OPCODE_POW);
 859 }
 860
 861 bool
 862 backend_instruction::is_control_flow() const
 863 {
 864    switch (opcode) {
 865    case BRW_OPCODE_DO:
 866    case BRW_OPCODE_WHILE:
 867    case BRW_OPCODE_IF:
 868    case BRW_OPCODE_ELSE:
 869    case BRW_OPCODE_ENDIF:
 870    case BRW_OPCODE_BREAK:
 871    case BRW_OPCODE_CONTINUE:
 872       return true;
 873    default:
 874       return false;
 875    }
 876 }
 877
 878 bool
 879 backend_instruction::can_do_source_mods() const
 880 {
 881    switch (opcode) {
 882    case BRW_OPCODE_ADDC:
 883    case BRW_OPCODE_BFE:
 884    case BRW_OPCODE_BFI1:
 885    case BRW_OPCODE_BFI2:
 886    case BRW_OPCODE_BFREV:
 887    case BRW_OPCODE_CBIT:
 888    case BRW_OPCODE_FBH:
 889    case BRW_OPCODE_FBL:
 890    case BRW_OPCODE_SUBB:
 891       return false;
 892    default:
 893       return true;
 894    }
 895 }
 896
 897 bool
 898 backend_instruction::can_do_saturate() const
 899 {
 900    switch (opcode) {
 901    case BRW_OPCODE_ADD:
 902    case BRW_OPCODE_ASR:
 903    case BRW_OPCODE_AVG:
 904    case BRW_OPCODE_DP2:
 905    case BRW_OPCODE_DP3:
 906    case BRW_OPCODE_DP4:
 907    case BRW_OPCODE_DPH:
 908    case BRW_OPCODE_F16TO32:
 909    case BRW_OPCODE_F32TO16:
 910    case BRW_OPCODE_LINE:
 911    case BRW_OPCODE_LRP:
 912    case BRW_OPCODE_MAC:
 913    case BRW_OPCODE_MACH:
 914    case BRW_OPCODE_MAD:
 915    case BRW_OPCODE_MATH:
 916    case BRW_OPCODE_MOV:
 917    case BRW_OPCODE_MUL:
 918    case BRW_OPCODE_PLN:
 919    case BRW_OPCODE_RNDD:
 920    case BRW_OPCODE_RNDE:
 921    case BRW_OPCODE_RNDU:
 922    case BRW_OPCODE_RNDZ:
 923    case BRW_OPCODE_SEL:
 924    case BRW_OPCODE_SHL:
 925    case BRW_OPCODE_SHR:
 926    case FS_OPCODE_LINTERP:
 927    case SHADER_OPCODE_COS:
 928    case SHADER_OPCODE_EXP2:
 929    case SHADER_OPCODE_LOG2:
 930    case SHADER_OPCODE_POW:
 931    case SHADER_OPCODE_RCP:
 932    case SHADER_OPCODE_RSQ:
 933    case SHADER_OPCODE_SIN:
 934    case SHADER_OPCODE_SQRT:
 935       return true;
 936    default:
 937       return false;
 938    }
 939 }
 940
 941 bool
 942 backend_instruction::can_do_cmod() const
 943 {
 944    switch (opcode) {
 945    case BRW_OPCODE_ADD:
 946    case BRW_OPCODE_ADDC:
 947    case BRW_OPCODE_AND:
 948    case BRW_OPCODE_ASR:
 949    case BRW_OPCODE_AVG:
 950    case BRW_OPCODE_CMP:
 951    case BRW_OPCODE_CMPN:
 952    case BRW_OPCODE_DP2:
 953    case BRW_OPCODE_DP3:
 954    case BRW_OPCODE_DP4:
 955    case BRW_OPCODE_DPH:
 956    case BRW_OPCODE_F16TO32:
 957    case BRW_OPCODE_F32TO16:
 958    case BRW_OPCODE_FRC:
 959    case BRW_OPCODE_LINE:
 960    case BRW_OPCODE_LRP:
 961    case BRW_OPCODE_LZD:
 962    case BRW_OPCODE_MAC:
 963    case BRW_OPCODE_MACH:
 964    case BRW_OPCODE_MAD:
 965    case BRW_OPCODE_MOV:
 966    case BRW_OPCODE_MUL:
 967    case BRW_OPCODE_NOT:
 968    case BRW_OPCODE_OR:
 969    case BRW_OPCODE_PLN:
 970    case BRW_OPCODE_RNDD:
 971    case BRW_OPCODE_RNDE:
 972    case BRW_OPCODE_RNDU:
 973    case BRW_OPCODE_RNDZ:
 974    case BRW_OPCODE_SAD2:
 975    case BRW_OPCODE_SADA2:
 976    case BRW_OPCODE_SHL:
 977    case BRW_OPCODE_SHR:
 978    case BRW_OPCODE_SUBB:
 979    case BRW_OPCODE_XOR:
 980    case FS_OPCODE_CINTERP:
 981    case FS_OPCODE_LINTERP:
 982       return true;
 983    default:
 984       return false;
 985    }
 986 }
 987
 988 bool
 989 backend_instruction::reads_accumulator_implicitly() const
 990 {
 991    switch (opcode) {
 992    case BRW_OPCODE_MAC:
 993    case BRW_OPCODE_MACH:
 994    case BRW_OPCODE_SADA2:
 995       return true;
 996    default:
 997       return false;
 998    }
 999 }
1000
1001 bool
1002 backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
1003 {
1004    return writes_accumulator ||
1005           (brw->gen < 6 &&
1006            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1007             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1008              opcode != FS_OPCODE_CINTERP)));
1009 }
1010
1011 bool
1012 backend_instruction::has_side_effects() const
1013 {
1014    switch (opcode) {
1015    case SHADER_OPCODE_UNTYPED_ATOMIC:
1016    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1017    case SHADER_OPCODE_URB_WRITE_SIMD8:
1018    case FS_OPCODE_FB_WRITE:
1019       return true;
1020    default:
1021       return false;
1022    }
1023 }
1024
1025 #ifndef NDEBUG
1026 static bool
1027 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1028 {
1029    bool found = false;
1030    foreach_inst_in_block (backend_instruction, i, block) {
1031       if (inst == i) {
1032          found = true;
1033       }
1034    }
1035    return found;
1036 }
1037 #endif
1038
1039 static void
1040 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1041 {
1042    for (bblock_t *block_iter = start_block->next();
1043         !block_iter->link.is_tail_sentinel();
1044         block_iter = block_iter->next()) {
1045       block_iter->start_ip += ip_adjustment;
1046       block_iter->end_ip += ip_adjustment;
1047    }
1048 }
1049
1050 void
1051 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1052 {
1053    if (!this->is_head_sentinel())
1054       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1055
1056    block->end_ip++;
1057
1058    adjust_later_block_ips(block, 1);
1059
1060    exec_node::insert_after(inst);
1061 }
1062
1063 void
1064 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1065 {
1066    if (!this->is_tail_sentinel())
1067       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1068
1069    block->end_ip++;
1070
1071    adjust_later_block_ips(block, 1);
1072
1073    exec_node::insert_before(inst);
1074 }
1075
1076 void
1077 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1078 {
1079    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1080
1081    unsigned num_inst = list->length();
1082
1083    block->end_ip += num_inst;
1084
1085    adjust_later_block_ips(block, num_inst);
1086
1087    exec_node::insert_before(list);
1088 }
1089
1090 void
1091 backend_instruction::remove(bblock_t *block)
1092 {
1093    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1094
1095    adjust_later_block_ips(block, -1);
1096
1097    if (block->start_ip == block->end_ip) {
1098       block->cfg->remove_block(block);
1099    } else {
1100       block->end_ip--;
1101    }
1102
1103    exec_node::remove();
1104 }
1105
1106 void
1107 backend_visitor::dump_instructions()
1108 {
1109    dump_instructions(NULL);
1110 }
1111
1112 void
1113 backend_visitor::dump_instructions(const char *name)
1114 {
1115    FILE *file = stderr;
1116    if (name && geteuid() != 0) {
1117       file = fopen(name, "w");
1118       if (!file)
1119          file = stderr;
1120    }
1121
1122    if (cfg) {
1123       int ip = 0;
1124       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1125          fprintf(file, "%4d: ", ip++);
1126          dump_instruction(inst, file);
1127       }
1128    } else {
1129       int ip = 0;
1130       foreach_in_list(backend_instruction, inst, &instructions) {
1131          fprintf(file, "%4d: ", ip++);
1132          dump_instruction(inst, file);
1133       }
1134    }
1135
1136    if (file != stderr) {
1137       fclose(file);
1138    }
1139 }
1140
1141 void
1142 backend_visitor::calculate_cfg()
1143 {
1144    if (this->cfg)
1145       return;
1146    cfg = new(mem_ctx) cfg_t(&this->instructions);
1147 }
1148
1149 void
1150 backend_visitor::invalidate_cfg()
1151 {
1152    ralloc_free(this->cfg);
1153    this->cfg = NULL;
1154 }
1155
1156 /**
1157  * Sets up the starting offsets for the groups of binding table entries
1158  * commong to all pipeline stages.
1159  *
1160  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1161  * unused but also make sure that addition of small offsets to them will
1162  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1163  */
1164 void
1165 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1166 {
1167    int num_textures = _mesa_fls(prog->SamplersUsed);
1168
1169    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1170    next_binding_table_offset += num_textures;
1171
1172    if (shader) {
1173       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1174       next_binding_table_offset += shader->base.NumUniformBlocks;
1175    } else {
1176       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1177    }
1178
1179    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1180       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1181       next_binding_table_offset++;
1182    } else {
1183       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1184    }
1185
1186    if (prog->UsesGather) {
1187       if (brw->gen >= 8) {
1188          stage_prog_data->binding_table.gather_texture_start =
1189             stage_prog_data->binding_table.texture_start;
1190       } else {
1191          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1192          next_binding_table_offset += num_textures;
1193       }
1194    } else {
1195       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1196    }
1197
1198    if (shader_prog && shader_prog->NumAtomicBuffers) {
1199       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1200       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1201    } else {
1202       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1203    }
1204
1205    if (shader && shader->base.NumImages) {
1206       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1207       next_binding_table_offset += shader->base.NumImages;
1208    } else {
1209       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1210    }
1211
1212    /* This may or may not be used depending on how the compile goes. */
1213    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1214    next_binding_table_offset++;
1215
1216    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1217
1218    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1219 }