src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/shaderobj.h"
  31 #include "main/uniforms.h"
  32 #include "util/debug.h"
  33
  34 static void
  35 shader_debug_log_mesa(void *data, const char *fmt, ...)
  36 {
  37    struct brw_context *brw = (struct brw_context *)data;
  38    va_list args;
  39
  40    va_start(args, fmt);
  41    GLuint msg_id = 0;
  42    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  43                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  44                    MESA_DEBUG_TYPE_OTHER,
  45                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  46    va_end(args);
  47 }
  48
  49 static void
  50 shader_perf_log_mesa(void *data, const char *fmt, ...)
  51 {
  52    struct brw_context *brw = (struct brw_context *)data;
  53
  54    va_list args;
  55    va_start(args, fmt);
  56
  57    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  58       va_list args_copy;
  59       va_copy(args_copy, args);
  60       vfprintf(stderr, fmt, args_copy);
  61       va_end(args_copy);
  62    }
  63
  64    if (brw->perf_debug) {
  65       GLuint msg_id = 0;
  66       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  67                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  68                       MESA_DEBUG_TYPE_PERFORMANCE,
  69                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  70    }
  71    va_end(args);
  72 }
  73
  74 struct brw_compiler *
  75 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  76 {
  77    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  78
  79    compiler->devinfo = devinfo;
  80    compiler->shader_debug_log = shader_debug_log_mesa;
  81    compiler->shader_perf_log = shader_perf_log_mesa;
  82
  83    brw_fs_alloc_reg_sets(compiler);
  84    brw_vec4_alloc_reg_set(compiler);
  85
  86    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  87       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  88    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = false;
  89    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
  90       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
  91    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  92       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  93    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  94    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  95
  96    nir_shader_compiler_options *nir_options =
  97       rzalloc(compiler, nir_shader_compiler_options);
  98    nir_options->native_integers = true;
  99    nir_options->vertex_id_zero_based = true;
 100    nir_options->lower_fdiv = true;
 101    /* In order to help allow for better CSE at the NIR level we tell NIR
 102     * to split all ffma instructions during opt_algebraic and we then
 103     * re-combine them as a later step.
 104     */
 105    nir_options->lower_ffma = true;
 106    nir_options->lower_sub = true;
 107    nir_options->lower_fdiv = true;
 108    nir_options->lower_scmp = true;
 109    nir_options->lower_fmod = true;
 110    nir_options->lower_bitfield_extract = true;
 111    nir_options->lower_bitfield_insert = true;
 112    nir_options->lower_uadd_carry = true;
 113    nir_options->lower_usub_borrow = true;
 114
 115    /* In the vec4 backend, our dpN instruction replicates its result to all
 116     * the components of a vec4.  We would like NIR to give us replicated fdot
 117     * instructions because it can optimize better for us.
 118     *
 119     * For the FS backend, it should be lowered away by the scalarizing pass so
 120     * we should never see fdot anyway.
 121     */
 122    nir_options->fdot_replicates = true;
 123
 124    /* We want the GLSL compiler to emit code that uses condition codes */
 125    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 126       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 127       compiler->glsl_compiler_options[i].MaxIfDepth =
 128          devinfo->gen < 6 ? 16 : UINT_MAX;
 129
 130       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 131       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 132       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 133       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 134       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 135       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 136
 137       bool is_scalar = compiler->scalar_stage[i];
 138
 139       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 140       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 141       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 142
 143       /* !ARB_gpu_shader5 */
 144       if (devinfo->gen < 7)
 145          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 146
 147       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 148
 149       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 150    }
 151
 152    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 153    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 154
 155    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 156       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 157
 158    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 159       .LowerShaderSharedVariables = true;
 160
 161    return compiler;
 162 }
 163
 164 extern "C" struct gl_shader *
 165 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 166 {
 167    struct brw_shader *shader;
 168
 169    shader = rzalloc(NULL, struct brw_shader);
 170    if (shader) {
 171       shader->base.Type = type;
 172       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 173       shader->base.Name = name;
 174       _mesa_init_shader(ctx, &shader->base);
 175    }
 176
 177    return &shader->base;
 178 }
 179
 180 extern "C" void
 181 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 182                       unsigned surf_index)
 183 {
 184    assert(surf_index < BRW_MAX_SURFACES);
 185
 186    prog_data->binding_table.size_bytes =
 187       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 188 }
 189
 190 enum brw_reg_type
 191 brw_type_for_base_type(const struct glsl_type *type)
 192 {
 193    switch (type->base_type) {
 194    case GLSL_TYPE_FLOAT:
 195       return BRW_REGISTER_TYPE_F;
 196    case GLSL_TYPE_INT:
 197    case GLSL_TYPE_BOOL:
 198    case GLSL_TYPE_SUBROUTINE:
 199       return BRW_REGISTER_TYPE_D;
 200    case GLSL_TYPE_UINT:
 201       return BRW_REGISTER_TYPE_UD;
 202    case GLSL_TYPE_ARRAY:
 203       return brw_type_for_base_type(type->fields.array);
 204    case GLSL_TYPE_STRUCT:
 205    case GLSL_TYPE_SAMPLER:
 206    case GLSL_TYPE_ATOMIC_UINT:
 207       /* These should be overridden with the type of the member when
 208        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 209        * way to trip up if we don't.
 210        */
 211       return BRW_REGISTER_TYPE_UD;
 212    case GLSL_TYPE_IMAGE:
 213       return BRW_REGISTER_TYPE_UD;
 214    case GLSL_TYPE_VOID:
 215    case GLSL_TYPE_ERROR:
 216    case GLSL_TYPE_INTERFACE:
 217    case GLSL_TYPE_DOUBLE:
 218    case GLSL_TYPE_FUNCTION:
 219       unreachable("not reached");
 220    }
 221
 222    return BRW_REGISTER_TYPE_F;
 223 }
 224
 225 enum brw_conditional_mod
 226 brw_conditional_for_comparison(unsigned int op)
 227 {
 228    switch (op) {
 229    case ir_binop_less:
 230       return BRW_CONDITIONAL_L;
 231    case ir_binop_greater:
 232       return BRW_CONDITIONAL_G;
 233    case ir_binop_lequal:
 234       return BRW_CONDITIONAL_LE;
 235    case ir_binop_gequal:
 236       return BRW_CONDITIONAL_GE;
 237    case ir_binop_equal:
 238    case ir_binop_all_equal: /* same as equal for scalars */
 239       return BRW_CONDITIONAL_Z;
 240    case ir_binop_nequal:
 241    case ir_binop_any_nequal: /* same as nequal for scalars */
 242       return BRW_CONDITIONAL_NZ;
 243    default:
 244       unreachable("not reached: bad operation for comparison");
 245    }
 246 }
 247
 248 uint32_t
 249 brw_math_function(enum opcode op)
 250 {
 251    switch (op) {
 252    case SHADER_OPCODE_RCP:
 253       return BRW_MATH_FUNCTION_INV;
 254    case SHADER_OPCODE_RSQ:
 255       return BRW_MATH_FUNCTION_RSQ;
 256    case SHADER_OPCODE_SQRT:
 257       return BRW_MATH_FUNCTION_SQRT;
 258    case SHADER_OPCODE_EXP2:
 259       return BRW_MATH_FUNCTION_EXP;
 260    case SHADER_OPCODE_LOG2:
 261       return BRW_MATH_FUNCTION_LOG;
 262    case SHADER_OPCODE_POW:
 263       return BRW_MATH_FUNCTION_POW;
 264    case SHADER_OPCODE_SIN:
 265       return BRW_MATH_FUNCTION_SIN;
 266    case SHADER_OPCODE_COS:
 267       return BRW_MATH_FUNCTION_COS;
 268    case SHADER_OPCODE_INT_QUOTIENT:
 269       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 270    case SHADER_OPCODE_INT_REMAINDER:
 271       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 272    default:
 273       unreachable("not reached: unknown math function");
 274    }
 275 }
 276
 277 uint32_t
 278 brw_texture_offset(int *offsets, unsigned num_components)
 279 {
 280    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 281
 282    /* Combine all three offsets into a single unsigned dword:
 283     *
 284     *    bits 11:8 - U Offset (X component)
 285     *    bits  7:4 - V Offset (Y component)
 286     *    bits  3:0 - R Offset (Z component)
 287     */
 288    unsigned offset_bits = 0;
 289    for (unsigned i = 0; i < num_components; i++) {
 290       const unsigned shift = 4 * (2 - i);
 291       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 292    }
 293    return offset_bits;
 294 }
 295
 296 const char *
 297 brw_instruction_name(enum opcode op)
 298 {
 299    switch (op) {
 300    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 301       assert(opcode_descs[op].name);
 302       return opcode_descs[op].name;
 303    case FS_OPCODE_FB_WRITE:
 304       return "fb_write";
 305    case FS_OPCODE_FB_WRITE_LOGICAL:
 306       return "fb_write_logical";
 307    case FS_OPCODE_PACK_STENCIL_REF:
 308       return "pack_stencil_ref";
 309    case FS_OPCODE_BLORP_FB_WRITE:
 310       return "blorp_fb_write";
 311    case FS_OPCODE_REP_FB_WRITE:
 312       return "rep_fb_write";
 313
 314    case SHADER_OPCODE_RCP:
 315       return "rcp";
 316    case SHADER_OPCODE_RSQ:
 317       return "rsq";
 318    case SHADER_OPCODE_SQRT:
 319       return "sqrt";
 320    case SHADER_OPCODE_EXP2:
 321       return "exp2";
 322    case SHADER_OPCODE_LOG2:
 323       return "log2";
 324    case SHADER_OPCODE_POW:
 325       return "pow";
 326    case SHADER_OPCODE_INT_QUOTIENT:
 327       return "int_quot";
 328    case SHADER_OPCODE_INT_REMAINDER:
 329       return "int_rem";
 330    case SHADER_OPCODE_SIN:
 331       return "sin";
 332    case SHADER_OPCODE_COS:
 333       return "cos";
 334
 335    case SHADER_OPCODE_TEX:
 336       return "tex";
 337    case SHADER_OPCODE_TEX_LOGICAL:
 338       return "tex_logical";
 339    case SHADER_OPCODE_TXD:
 340       return "txd";
 341    case SHADER_OPCODE_TXD_LOGICAL:
 342       return "txd_logical";
 343    case SHADER_OPCODE_TXF:
 344       return "txf";
 345    case SHADER_OPCODE_TXF_LOGICAL:
 346       return "txf_logical";
 347    case SHADER_OPCODE_TXL:
 348       return "txl";
 349    case SHADER_OPCODE_TXL_LOGICAL:
 350       return "txl_logical";
 351    case SHADER_OPCODE_TXS:
 352       return "txs";
 353    case SHADER_OPCODE_TXS_LOGICAL:
 354       return "txs_logical";
 355    case FS_OPCODE_TXB:
 356       return "txb";
 357    case FS_OPCODE_TXB_LOGICAL:
 358       return "txb_logical";
 359    case SHADER_OPCODE_TXF_CMS:
 360       return "txf_cms";
 361    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 362       return "txf_cms_logical";
 363    case SHADER_OPCODE_TXF_CMS_W:
 364       return "txf_cms_w";
 365    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 366       return "txf_cms_w_logical";
 367    case SHADER_OPCODE_TXF_UMS:
 368       return "txf_ums";
 369    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 370       return "txf_ums_logical";
 371    case SHADER_OPCODE_TXF_MCS:
 372       return "txf_mcs";
 373    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 374       return "txf_mcs_logical";
 375    case SHADER_OPCODE_LOD:
 376       return "lod";
 377    case SHADER_OPCODE_LOD_LOGICAL:
 378       return "lod_logical";
 379    case SHADER_OPCODE_TG4:
 380       return "tg4";
 381    case SHADER_OPCODE_TG4_LOGICAL:
 382       return "tg4_logical";
 383    case SHADER_OPCODE_TG4_OFFSET:
 384       return "tg4_offset";
 385    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 386       return "tg4_offset_logical";
 387    case SHADER_OPCODE_SAMPLEINFO:
 388       return "sampleinfo";
 389
 390    case SHADER_OPCODE_SHADER_TIME_ADD:
 391       return "shader_time_add";
 392
 393    case SHADER_OPCODE_UNTYPED_ATOMIC:
 394       return "untyped_atomic";
 395    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 396       return "untyped_atomic_logical";
 397    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 398       return "untyped_surface_read";
 399    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 400       return "untyped_surface_read_logical";
 401    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 402       return "untyped_surface_write";
 403    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 404       return "untyped_surface_write_logical";
 405    case SHADER_OPCODE_TYPED_ATOMIC:
 406       return "typed_atomic";
 407    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 408       return "typed_atomic_logical";
 409    case SHADER_OPCODE_TYPED_SURFACE_READ:
 410       return "typed_surface_read";
 411    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 412       return "typed_surface_read_logical";
 413    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 414       return "typed_surface_write";
 415    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 416       return "typed_surface_write_logical";
 417    case SHADER_OPCODE_MEMORY_FENCE:
 418       return "memory_fence";
 419
 420    case SHADER_OPCODE_LOAD_PAYLOAD:
 421       return "load_payload";
 422
 423    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 424       return "gen4_scratch_read";
 425    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 426       return "gen4_scratch_write";
 427    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 428       return "gen7_scratch_read";
 429    case SHADER_OPCODE_URB_WRITE_SIMD8:
 430       return "gen8_urb_write_simd8";
 431    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 432       return "gen8_urb_write_simd8_per_slot";
 433    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 434       return "gen8_urb_write_simd8_masked";
 435    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 436       return "gen8_urb_write_simd8_masked_per_slot";
 437    case SHADER_OPCODE_URB_READ_SIMD8:
 438       return "urb_read_simd8";
 439    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 440       return "urb_read_simd8_per_slot";
 441
 442    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 443       return "find_live_channel";
 444    case SHADER_OPCODE_BROADCAST:
 445       return "broadcast";
 446
 447    case VEC4_OPCODE_MOV_BYTES:
 448       return "mov_bytes";
 449    case VEC4_OPCODE_PACK_BYTES:
 450       return "pack_bytes";
 451    case VEC4_OPCODE_UNPACK_UNIFORM:
 452       return "unpack_uniform";
 453
 454    case FS_OPCODE_DDX_COARSE:
 455       return "ddx_coarse";
 456    case FS_OPCODE_DDX_FINE:
 457       return "ddx_fine";
 458    case FS_OPCODE_DDY_COARSE:
 459       return "ddy_coarse";
 460    case FS_OPCODE_DDY_FINE:
 461       return "ddy_fine";
 462
 463    case FS_OPCODE_CINTERP:
 464       return "cinterp";
 465    case FS_OPCODE_LINTERP:
 466       return "linterp";
 467
 468    case FS_OPCODE_PIXEL_X:
 469       return "pixel_x";
 470    case FS_OPCODE_PIXEL_Y:
 471       return "pixel_y";
 472
 473    case FS_OPCODE_GET_BUFFER_SIZE:
 474       return "fs_get_buffer_size";
 475
 476    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 477       return "uniform_pull_const";
 478    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 479       return "uniform_pull_const_gen7";
 480    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 481       return "varying_pull_const";
 482    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 483       return "varying_pull_const_gen7";
 484
 485    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 486       return "mov_dispatch_to_flags";
 487    case FS_OPCODE_DISCARD_JUMP:
 488       return "discard_jump";
 489
 490    case FS_OPCODE_SET_SAMPLE_ID:
 491       return "set_sample_id";
 492    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 493       return "set_simd4x2_offset";
 494
 495    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 496       return "pack_half_2x16_split";
 497    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 498       return "unpack_half_2x16_split_x";
 499    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 500       return "unpack_half_2x16_split_y";
 501
 502    case FS_OPCODE_PLACEHOLDER_HALT:
 503       return "placeholder_halt";
 504
 505    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 506       return "interp_centroid";
 507    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 508       return "interp_sample";
 509    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 510       return "interp_shared_offset";
 511    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 512       return "interp_per_slot_offset";
 513
 514    case VS_OPCODE_URB_WRITE:
 515       return "vs_urb_write";
 516    case VS_OPCODE_PULL_CONSTANT_LOAD:
 517       return "pull_constant_load";
 518    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 519       return "pull_constant_load_gen7";
 520
 521    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 522       return "set_simd4x2_header_gen9";
 523
 524    case VS_OPCODE_GET_BUFFER_SIZE:
 525       return "vs_get_buffer_size";
 526
 527    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 528       return "unpack_flags_simd4x2";
 529
 530    case GS_OPCODE_URB_WRITE:
 531       return "gs_urb_write";
 532    case GS_OPCODE_URB_WRITE_ALLOCATE:
 533       return "gs_urb_write_allocate";
 534    case GS_OPCODE_THREAD_END:
 535       return "gs_thread_end";
 536    case GS_OPCODE_SET_WRITE_OFFSET:
 537       return "set_write_offset";
 538    case GS_OPCODE_SET_VERTEX_COUNT:
 539       return "set_vertex_count";
 540    case GS_OPCODE_SET_DWORD_2:
 541       return "set_dword_2";
 542    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 543       return "prepare_channel_masks";
 544    case GS_OPCODE_SET_CHANNEL_MASKS:
 545       return "set_channel_masks";
 546    case GS_OPCODE_GET_INSTANCE_ID:
 547       return "get_instance_id";
 548    case GS_OPCODE_FF_SYNC:
 549       return "ff_sync";
 550    case GS_OPCODE_SET_PRIMITIVE_ID:
 551       return "set_primitive_id";
 552    case GS_OPCODE_SVB_WRITE:
 553       return "gs_svb_write";
 554    case GS_OPCODE_SVB_SET_DST_INDEX:
 555       return "gs_svb_set_dst_index";
 556    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 557       return "gs_ff_sync_set_primitives";
 558    case CS_OPCODE_CS_TERMINATE:
 559       return "cs_terminate";
 560    case SHADER_OPCODE_BARRIER:
 561       return "barrier";
 562    case SHADER_OPCODE_MULH:
 563       return "mulh";
 564    case SHADER_OPCODE_MOV_INDIRECT:
 565       return "mov_indirect";
 566
 567    case VEC4_OPCODE_URB_READ:
 568       return "urb_read";
 569    case TCS_OPCODE_GET_INSTANCE_ID:
 570       return "tcs_get_instance_id";
 571    case TCS_OPCODE_URB_WRITE:
 572       return "tcs_urb_write";
 573    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 574       return "tcs_set_input_urb_offsets";
 575    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 576       return "tcs_set_output_urb_offsets";
 577    case TCS_OPCODE_GET_PRIMITIVE_ID:
 578       return "tcs_get_primitive_id";
 579    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 580       return "tcs_create_barrier_header";
 581    case TCS_OPCODE_SRC0_010_IS_ZERO:
 582       return "tcs_src0<0,1,0>_is_zero";
 583    case TCS_OPCODE_RELEASE_INPUT:
 584       return "tcs_release_input";
 585    case TCS_OPCODE_THREAD_END:
 586       return "tcs_thread_end";
 587    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 588       return "tes_create_input_read_header";
 589    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 590       return "tes_add_indirect_urb_offset";
 591    case TES_OPCODE_GET_PRIMITIVE_ID:
 592       return "tes_get_primitive_id";
 593    }
 594
 595    unreachable("not reached");
 596 }
 597
 598 bool
 599 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 600 {
 601    union {
 602       unsigned ud;
 603       int d;
 604       float f;
 605    } imm = { reg->ud }, sat_imm = { 0 };
 606
 607    switch (type) {
 608    case BRW_REGISTER_TYPE_UD:
 609    case BRW_REGISTER_TYPE_D:
 610    case BRW_REGISTER_TYPE_UW:
 611    case BRW_REGISTER_TYPE_W:
 612    case BRW_REGISTER_TYPE_UQ:
 613    case BRW_REGISTER_TYPE_Q:
 614       /* Nothing to do. */
 615       return false;
 616    case BRW_REGISTER_TYPE_F:
 617       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 618       break;
 619    case BRW_REGISTER_TYPE_UB:
 620    case BRW_REGISTER_TYPE_B:
 621       unreachable("no UB/B immediates");
 622    case BRW_REGISTER_TYPE_V:
 623    case BRW_REGISTER_TYPE_UV:
 624    case BRW_REGISTER_TYPE_VF:
 625       unreachable("unimplemented: saturate vector immediate");
 626    case BRW_REGISTER_TYPE_DF:
 627    case BRW_REGISTER_TYPE_HF:
 628       unreachable("unimplemented: saturate DF/HF immediate");
 629    }
 630
 631    if (imm.ud != sat_imm.ud) {
 632       reg->ud = sat_imm.ud;
 633       return true;
 634    }
 635    return false;
 636 }
 637
 638 bool
 639 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 640 {
 641    switch (type) {
 642    case BRW_REGISTER_TYPE_D:
 643    case BRW_REGISTER_TYPE_UD:
 644       reg->d = -reg->d;
 645       return true;
 646    case BRW_REGISTER_TYPE_W:
 647    case BRW_REGISTER_TYPE_UW:
 648       reg->d = -(int16_t)reg->ud;
 649       return true;
 650    case BRW_REGISTER_TYPE_F:
 651       reg->f = -reg->f;
 652       return true;
 653    case BRW_REGISTER_TYPE_VF:
 654       reg->ud ^= 0x80808080;
 655       return true;
 656    case BRW_REGISTER_TYPE_UB:
 657    case BRW_REGISTER_TYPE_B:
 658       unreachable("no UB/B immediates");
 659    case BRW_REGISTER_TYPE_UV:
 660    case BRW_REGISTER_TYPE_V:
 661       assert(!"unimplemented: negate UV/V immediate");
 662    case BRW_REGISTER_TYPE_UQ:
 663    case BRW_REGISTER_TYPE_Q:
 664       assert(!"unimplemented: negate UQ/Q immediate");
 665    case BRW_REGISTER_TYPE_DF:
 666    case BRW_REGISTER_TYPE_HF:
 667       assert(!"unimplemented: negate DF/HF immediate");
 668    }
 669
 670    return false;
 671 }
 672
 673 bool
 674 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 675 {
 676    switch (type) {
 677    case BRW_REGISTER_TYPE_D:
 678       reg->d = abs(reg->d);
 679       return true;
 680    case BRW_REGISTER_TYPE_W:
 681       reg->d = abs((int16_t)reg->ud);
 682       return true;
 683    case BRW_REGISTER_TYPE_F:
 684       reg->f = fabsf(reg->f);
 685       return true;
 686    case BRW_REGISTER_TYPE_VF:
 687       reg->ud &= ~0x80808080;
 688       return true;
 689    case BRW_REGISTER_TYPE_UB:
 690    case BRW_REGISTER_TYPE_B:
 691       unreachable("no UB/B immediates");
 692    case BRW_REGISTER_TYPE_UQ:
 693    case BRW_REGISTER_TYPE_UD:
 694    case BRW_REGISTER_TYPE_UW:
 695    case BRW_REGISTER_TYPE_UV:
 696       /* Presumably the absolute value modifier on an unsigned source is a
 697        * nop, but it would be nice to confirm.
 698        */
 699       assert(!"unimplemented: abs unsigned immediate");
 700    case BRW_REGISTER_TYPE_V:
 701       assert(!"unimplemented: abs V immediate");
 702    case BRW_REGISTER_TYPE_Q:
 703       assert(!"unimplemented: abs Q immediate");
 704    case BRW_REGISTER_TYPE_DF:
 705    case BRW_REGISTER_TYPE_HF:
 706       assert(!"unimplemented: abs DF/HF immediate");
 707    }
 708
 709    return false;
 710 }
 711
 712 backend_shader::backend_shader(const struct brw_compiler *compiler,
 713                                void *log_data,
 714                                void *mem_ctx,
 715                                const nir_shader *shader,
 716                                struct brw_stage_prog_data *stage_prog_data)
 717    : compiler(compiler),
 718      log_data(log_data),
 719      devinfo(compiler->devinfo),
 720      nir(shader),
 721      stage_prog_data(stage_prog_data),
 722      mem_ctx(mem_ctx),
 723      cfg(NULL),
 724      stage(shader->stage)
 725 {
 726    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 727    stage_name = _mesa_shader_stage_to_string(stage);
 728    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 729 }
 730
 731 bool
 732 backend_reg::equals(const backend_reg &r) const
 733 {
 734    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 735           reg_offset == r.reg_offset;
 736 }
 737
 738 bool
 739 backend_reg::is_zero() const
 740 {
 741    if (file != IMM)
 742       return false;
 743
 744    return d == 0;
 745 }
 746
 747 bool
 748 backend_reg::is_one() const
 749 {
 750    if (file != IMM)
 751       return false;
 752
 753    return type == BRW_REGISTER_TYPE_F
 754           ? f == 1.0
 755           : d == 1;
 756 }
 757
 758 bool
 759 backend_reg::is_negative_one() const
 760 {
 761    if (file != IMM)
 762       return false;
 763
 764    switch (type) {
 765    case BRW_REGISTER_TYPE_F:
 766       return f == -1.0;
 767    case BRW_REGISTER_TYPE_D:
 768       return d == -1;
 769    default:
 770       return false;
 771    }
 772 }
 773
 774 bool
 775 backend_reg::is_null() const
 776 {
 777    return file == ARF && nr == BRW_ARF_NULL;
 778 }
 779
 780
 781 bool
 782 backend_reg::is_accumulator() const
 783 {
 784    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 785 }
 786
 787 bool
 788 backend_reg::in_range(const backend_reg &r, unsigned n) const
 789 {
 790    return (file == r.file &&
 791            nr == r.nr &&
 792            reg_offset >= r.reg_offset &&
 793            reg_offset < r.reg_offset + n);
 794 }
 795
 796 bool
 797 backend_instruction::is_commutative() const
 798 {
 799    switch (opcode) {
 800    case BRW_OPCODE_AND:
 801    case BRW_OPCODE_OR:
 802    case BRW_OPCODE_XOR:
 803    case BRW_OPCODE_ADD:
 804    case BRW_OPCODE_MUL:
 805    case SHADER_OPCODE_MULH:
 806       return true;
 807    case BRW_OPCODE_SEL:
 808       /* MIN and MAX are commutative. */
 809       if (conditional_mod == BRW_CONDITIONAL_GE ||
 810           conditional_mod == BRW_CONDITIONAL_L) {
 811          return true;
 812       }
 813       /* fallthrough */
 814    default:
 815       return false;
 816    }
 817 }
 818
 819 bool
 820 backend_instruction::is_3src() const
 821 {
 822    return ::is_3src(opcode);
 823 }
 824
 825 bool
 826 backend_instruction::is_tex() const
 827 {
 828    return (opcode == SHADER_OPCODE_TEX ||
 829            opcode == FS_OPCODE_TXB ||
 830            opcode == SHADER_OPCODE_TXD ||
 831            opcode == SHADER_OPCODE_TXF ||
 832            opcode == SHADER_OPCODE_TXF_CMS ||
 833            opcode == SHADER_OPCODE_TXF_CMS_W ||
 834            opcode == SHADER_OPCODE_TXF_UMS ||
 835            opcode == SHADER_OPCODE_TXF_MCS ||
 836            opcode == SHADER_OPCODE_TXL ||
 837            opcode == SHADER_OPCODE_TXS ||
 838            opcode == SHADER_OPCODE_LOD ||
 839            opcode == SHADER_OPCODE_TG4 ||
 840            opcode == SHADER_OPCODE_TG4_OFFSET);
 841 }
 842
 843 bool
 844 backend_instruction::is_math() const
 845 {
 846    return (opcode == SHADER_OPCODE_RCP ||
 847            opcode == SHADER_OPCODE_RSQ ||
 848            opcode == SHADER_OPCODE_SQRT ||
 849            opcode == SHADER_OPCODE_EXP2 ||
 850            opcode == SHADER_OPCODE_LOG2 ||
 851            opcode == SHADER_OPCODE_SIN ||
 852            opcode == SHADER_OPCODE_COS ||
 853            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 854            opcode == SHADER_OPCODE_INT_REMAINDER ||
 855            opcode == SHADER_OPCODE_POW);
 856 }
 857
 858 bool
 859 backend_instruction::is_control_flow() const
 860 {
 861    switch (opcode) {
 862    case BRW_OPCODE_DO:
 863    case BRW_OPCODE_WHILE:
 864    case BRW_OPCODE_IF:
 865    case BRW_OPCODE_ELSE:
 866    case BRW_OPCODE_ENDIF:
 867    case BRW_OPCODE_BREAK:
 868    case BRW_OPCODE_CONTINUE:
 869       return true;
 870    default:
 871       return false;
 872    }
 873 }
 874
 875 bool
 876 backend_instruction::can_do_source_mods() const
 877 {
 878    switch (opcode) {
 879    case BRW_OPCODE_ADDC:
 880    case BRW_OPCODE_BFE:
 881    case BRW_OPCODE_BFI1:
 882    case BRW_OPCODE_BFI2:
 883    case BRW_OPCODE_BFREV:
 884    case BRW_OPCODE_CBIT:
 885    case BRW_OPCODE_FBH:
 886    case BRW_OPCODE_FBL:
 887    case BRW_OPCODE_SUBB:
 888       return false;
 889    default:
 890       return true;
 891    }
 892 }
 893
 894 bool
 895 backend_instruction::can_do_saturate() const
 896 {
 897    switch (opcode) {
 898    case BRW_OPCODE_ADD:
 899    case BRW_OPCODE_ASR:
 900    case BRW_OPCODE_AVG:
 901    case BRW_OPCODE_DP2:
 902    case BRW_OPCODE_DP3:
 903    case BRW_OPCODE_DP4:
 904    case BRW_OPCODE_DPH:
 905    case BRW_OPCODE_F16TO32:
 906    case BRW_OPCODE_F32TO16:
 907    case BRW_OPCODE_LINE:
 908    case BRW_OPCODE_LRP:
 909    case BRW_OPCODE_MAC:
 910    case BRW_OPCODE_MAD:
 911    case BRW_OPCODE_MATH:
 912    case BRW_OPCODE_MOV:
 913    case BRW_OPCODE_MUL:
 914    case SHADER_OPCODE_MULH:
 915    case BRW_OPCODE_PLN:
 916    case BRW_OPCODE_RNDD:
 917    case BRW_OPCODE_RNDE:
 918    case BRW_OPCODE_RNDU:
 919    case BRW_OPCODE_RNDZ:
 920    case BRW_OPCODE_SEL:
 921    case BRW_OPCODE_SHL:
 922    case BRW_OPCODE_SHR:
 923    case FS_OPCODE_LINTERP:
 924    case SHADER_OPCODE_COS:
 925    case SHADER_OPCODE_EXP2:
 926    case SHADER_OPCODE_LOG2:
 927    case SHADER_OPCODE_POW:
 928    case SHADER_OPCODE_RCP:
 929    case SHADER_OPCODE_RSQ:
 930    case SHADER_OPCODE_SIN:
 931    case SHADER_OPCODE_SQRT:
 932       return true;
 933    default:
 934       return false;
 935    }
 936 }
 937
 938 bool
 939 backend_instruction::can_do_cmod() const
 940 {
 941    switch (opcode) {
 942    case BRW_OPCODE_ADD:
 943    case BRW_OPCODE_ADDC:
 944    case BRW_OPCODE_AND:
 945    case BRW_OPCODE_ASR:
 946    case BRW_OPCODE_AVG:
 947    case BRW_OPCODE_CMP:
 948    case BRW_OPCODE_CMPN:
 949    case BRW_OPCODE_DP2:
 950    case BRW_OPCODE_DP3:
 951    case BRW_OPCODE_DP4:
 952    case BRW_OPCODE_DPH:
 953    case BRW_OPCODE_F16TO32:
 954    case BRW_OPCODE_F32TO16:
 955    case BRW_OPCODE_FRC:
 956    case BRW_OPCODE_LINE:
 957    case BRW_OPCODE_LRP:
 958    case BRW_OPCODE_LZD:
 959    case BRW_OPCODE_MAC:
 960    case BRW_OPCODE_MACH:
 961    case BRW_OPCODE_MAD:
 962    case BRW_OPCODE_MOV:
 963    case BRW_OPCODE_MUL:
 964    case BRW_OPCODE_NOT:
 965    case BRW_OPCODE_OR:
 966    case BRW_OPCODE_PLN:
 967    case BRW_OPCODE_RNDD:
 968    case BRW_OPCODE_RNDE:
 969    case BRW_OPCODE_RNDU:
 970    case BRW_OPCODE_RNDZ:
 971    case BRW_OPCODE_SAD2:
 972    case BRW_OPCODE_SADA2:
 973    case BRW_OPCODE_SHL:
 974    case BRW_OPCODE_SHR:
 975    case BRW_OPCODE_SUBB:
 976    case BRW_OPCODE_XOR:
 977    case FS_OPCODE_CINTERP:
 978    case FS_OPCODE_LINTERP:
 979       return true;
 980    default:
 981       return false;
 982    }
 983 }
 984
 985 bool
 986 backend_instruction::reads_accumulator_implicitly() const
 987 {
 988    switch (opcode) {
 989    case BRW_OPCODE_MAC:
 990    case BRW_OPCODE_MACH:
 991    case BRW_OPCODE_SADA2:
 992       return true;
 993    default:
 994       return false;
 995    }
 996 }
 997
 998 bool
 999 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1000 {
1001    return writes_accumulator ||
1002           (devinfo->gen < 6 &&
1003            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1004             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1005              opcode != FS_OPCODE_CINTERP)));
1006 }
1007
1008 bool
1009 backend_instruction::has_side_effects() const
1010 {
1011    switch (opcode) {
1012    case SHADER_OPCODE_UNTYPED_ATOMIC:
1013    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1014    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1015    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1016    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1017    case SHADER_OPCODE_TYPED_ATOMIC:
1018    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1019    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1020    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1021    case SHADER_OPCODE_MEMORY_FENCE:
1022    case SHADER_OPCODE_URB_WRITE_SIMD8:
1023    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1024    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1025    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1026    case FS_OPCODE_FB_WRITE:
1027    case SHADER_OPCODE_BARRIER:
1028    case TCS_OPCODE_URB_WRITE:
1029    case TCS_OPCODE_RELEASE_INPUT:
1030       return true;
1031    default:
1032       return false;
1033    }
1034 }
1035
1036 bool
1037 backend_instruction::is_volatile() const
1038 {
1039    switch (opcode) {
1040    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1041    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1042    case SHADER_OPCODE_TYPED_SURFACE_READ:
1043    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1044       return true;
1045    default:
1046       return false;
1047    }
1048 }
1049
1050 #ifndef NDEBUG
1051 static bool
1052 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1053 {
1054    bool found = false;
1055    foreach_inst_in_block (backend_instruction, i, block) {
1056       if (inst == i) {
1057          found = true;
1058       }
1059    }
1060    return found;
1061 }
1062 #endif
1063
1064 static void
1065 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1066 {
1067    for (bblock_t *block_iter = start_block->next();
1068         !block_iter->link.is_tail_sentinel();
1069         block_iter = block_iter->next()) {
1070       block_iter->start_ip += ip_adjustment;
1071       block_iter->end_ip += ip_adjustment;
1072    }
1073 }
1074
1075 void
1076 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1077 {
1078    if (!this->is_head_sentinel())
1079       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1080
1081    block->end_ip++;
1082
1083    adjust_later_block_ips(block, 1);
1084
1085    exec_node::insert_after(inst);
1086 }
1087
1088 void
1089 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1090 {
1091    if (!this->is_tail_sentinel())
1092       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1093
1094    block->end_ip++;
1095
1096    adjust_later_block_ips(block, 1);
1097
1098    exec_node::insert_before(inst);
1099 }
1100
1101 void
1102 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1103 {
1104    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1105
1106    unsigned num_inst = list->length();
1107
1108    block->end_ip += num_inst;
1109
1110    adjust_later_block_ips(block, num_inst);
1111
1112    exec_node::insert_before(list);
1113 }
1114
1115 void
1116 backend_instruction::remove(bblock_t *block)
1117 {
1118    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1119
1120    adjust_later_block_ips(block, -1);
1121
1122    if (block->start_ip == block->end_ip) {
1123       block->cfg->remove_block(block);
1124    } else {
1125       block->end_ip--;
1126    }
1127
1128    exec_node::remove();
1129 }
1130
1131 void
1132 backend_shader::dump_instructions()
1133 {
1134    dump_instructions(NULL);
1135 }
1136
1137 void
1138 backend_shader::dump_instructions(const char *name)
1139 {
1140    FILE *file = stderr;
1141    if (name && geteuid() != 0) {
1142       file = fopen(name, "w");
1143       if (!file)
1144          file = stderr;
1145    }
1146
1147    if (cfg) {
1148       int ip = 0;
1149       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1150          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1151             fprintf(file, "%4d: ", ip++);
1152          dump_instruction(inst, file);
1153       }
1154    } else {
1155       int ip = 0;
1156       foreach_in_list(backend_instruction, inst, &instructions) {
1157          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1158             fprintf(file, "%4d: ", ip++);
1159          dump_instruction(inst, file);
1160       }
1161    }
1162
1163    if (file != stderr) {
1164       fclose(file);
1165    }
1166 }
1167
1168 void
1169 backend_shader::calculate_cfg()
1170 {
1171    if (this->cfg)
1172       return;
1173    cfg = new(mem_ctx) cfg_t(&this->instructions);
1174 }
1175
1176 void
1177 backend_shader::invalidate_cfg()
1178 {
1179    ralloc_free(this->cfg);
1180    this->cfg = NULL;
1181 }
1182
1183 /**
1184  * Sets up the starting offsets for the groups of binding table entries
1185  * commong to all pipeline stages.
1186  *
1187  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1188  * unused but also make sure that addition of small offsets to them will
1189  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1190  */
1191 void
1192 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1193                                         const struct brw_device_info *devinfo,
1194                                         const struct gl_shader_program *shader_prog,
1195                                         const struct gl_program *prog,
1196                                         struct brw_stage_prog_data *stage_prog_data,
1197                                         uint32_t next_binding_table_offset)
1198 {
1199    const struct gl_shader *shader = NULL;
1200    int num_textures = _mesa_fls(prog->SamplersUsed);
1201
1202    if (shader_prog)
1203       shader = shader_prog->_LinkedShaders[stage];
1204
1205    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1206    next_binding_table_offset += num_textures;
1207
1208    if (shader) {
1209       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1210       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1211       next_binding_table_offset += shader->NumUniformBlocks;
1212
1213       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1214       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1215       next_binding_table_offset += shader->NumShaderStorageBlocks;
1216    } else {
1217       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1218       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1219    }
1220
1221    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1222       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1223       next_binding_table_offset++;
1224    } else {
1225       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1226    }
1227
1228    if (prog->UsesGather) {
1229       if (devinfo->gen >= 8) {
1230          stage_prog_data->binding_table.gather_texture_start =
1231             stage_prog_data->binding_table.texture_start;
1232       } else {
1233          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1234          next_binding_table_offset += num_textures;
1235       }
1236    } else {
1237       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1238    }
1239
1240    if (shader && shader->NumAtomicBuffers) {
1241       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1242       next_binding_table_offset += shader->NumAtomicBuffers;
1243    } else {
1244       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1245    }
1246
1247    if (shader && shader->NumImages) {
1248       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1249       next_binding_table_offset += shader->NumImages;
1250    } else {
1251       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1252    }
1253
1254    /* This may or may not be used depending on how the compile goes. */
1255    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1256    next_binding_table_offset++;
1257
1258    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1259
1260    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1261 }
1262
1263 static void
1264 setup_vec4_uniform_value(const gl_constant_value **params,
1265                          const gl_constant_value *values,
1266                          unsigned n)
1267 {
1268    static const gl_constant_value zero = { 0 };
1269
1270    for (unsigned i = 0; i < n; ++i)
1271       params[i] = &values[i];
1272
1273    for (unsigned i = n; i < 4; ++i)
1274       params[i] = &zero;
1275 }
1276
1277 void
1278 brw_setup_image_uniform_values(gl_shader_stage stage,
1279                                struct brw_stage_prog_data *stage_prog_data,
1280                                unsigned param_start_index,
1281                                const gl_uniform_storage *storage)
1282 {
1283    const gl_constant_value **param =
1284       &stage_prog_data->param[param_start_index];
1285
1286    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1287       const unsigned image_idx = storage->opaque[stage].index + i;
1288       const brw_image_param *image_param =
1289          &stage_prog_data->image_param[image_idx];
1290
1291       /* Upload the brw_image_param structure.  The order is expected to match
1292        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1293        */
1294       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1295          (const gl_constant_value *)&image_param->surface_idx, 1);
1296       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1297          (const gl_constant_value *)image_param->offset, 2);
1298       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1299          (const gl_constant_value *)image_param->size, 3);
1300       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1301          (const gl_constant_value *)image_param->stride, 4);
1302       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1303          (const gl_constant_value *)image_param->tiling, 3);
1304       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1305          (const gl_constant_value *)image_param->swizzling, 2);
1306       param += BRW_IMAGE_PARAM_SIZE;
1307
1308       brw_mark_surface_used(
1309          stage_prog_data,
1310          stage_prog_data->binding_table.image_start + image_idx);
1311    }
1312 }
1313
1314 /**
1315  * Decide which set of clip planes should be used when clipping via
1316  * gl_Position or gl_ClipVertex.
1317  */
1318 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1319 {
1320    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1321       /* There is currently a GLSL vertex shader, so clip according to GLSL
1322        * rules, which means compare gl_ClipVertex (or gl_Position, if
1323        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1324        * that were stored in EyeUserPlane at the time the clip planes were
1325        * specified.
1326        */
1327       return ctx->Transform.EyeUserPlane;
1328    } else {
1329       /* Either we are using fixed function or an ARB vertex program.  In
1330        * either case the clip planes are going to be compared against
1331        * gl_Position (which is in clip coordinates) so we have to clip using
1332        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1333        * core.
1334        */
1335       return ctx->Transform._ClipUserPlane;
1336    }
1337 }
1338
1339 extern "C" const unsigned *
1340 brw_compile_tes(const struct brw_compiler *compiler,
1341                 void *log_data,
1342                 void *mem_ctx,
1343                 const struct brw_tes_prog_key *key,
1344                 struct brw_tes_prog_data *prog_data,
1345                 const nir_shader *src_shader,
1346                 struct gl_shader_program *shader_prog,
1347                 int shader_time_index,
1348                 unsigned *final_assembly_size,
1349                 char **error_str)
1350 {
1351    const struct brw_device_info *devinfo = compiler->devinfo;
1352    struct gl_shader *shader =
1353       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
1354    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1355
1356    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1357    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
1358    nir->info.inputs_read = key->inputs_read;
1359    nir->info.patch_inputs_read = key->patch_inputs_read;
1360    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
1361    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
1362
1363    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1364                        nir->info.outputs_written,
1365                        nir->info.separate_shader);
1366
1367    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1368
1369    assert(output_size_bytes >= 1);
1370    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1371       if (error_str)
1372          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1373       return NULL;
1374    }
1375
1376    /* URB entry sizes are stored as a multiple of 64 bytes. */
1377    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1378
1379    struct brw_vue_map input_vue_map;
1380    brw_compute_tess_vue_map(&input_vue_map,
1381                             nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
1382                             nir->info.patch_inputs_read);
1383
1384    bool need_patch_header = nir->info.system_values_read &
1385       (BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
1386        BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
1387
1388    /* The TES will pull most inputs using URB read messages.
1389     *
1390     * However, we push the patch header for TessLevel factors when required,
1391     * as it's a tiny amount of extra data.
1392     */
1393    prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
1394
1395    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1396       fprintf(stderr, "TES Input ");
1397       brw_print_vue_map(stderr, &input_vue_map);
1398       fprintf(stderr, "TES Output ");
1399       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1400    }
1401
1402    if (is_scalar) {
1403       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1404                    &prog_data->base.base, shader->Program, nir, 8,
1405                    shader_time_index, &input_vue_map);
1406       if (!v.run_tes()) {
1407          if (error_str)
1408             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1409          return NULL;
1410       }
1411
1412       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1413
1414       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1415                      &prog_data->base.base, v.promoted_constants, false,
1416                      MESA_SHADER_TESS_EVAL);
1417       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1418          g.enable_debug(ralloc_asprintf(mem_ctx,
1419                                         "%s tessellation evaluation shader %s",
1420                                         nir->info.label ? nir->info.label
1421                                                         : "unnamed",
1422                                         nir->info.name));
1423       }
1424
1425       g.generate_code(v.cfg, 8);
1426
1427       return g.get_assembly(final_assembly_size);
1428    } else {
1429       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1430                               nir, mem_ctx, shader_time_index);
1431       if (!v.run()) {
1432          if (error_str)
1433             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1434          return NULL;
1435       }
1436
1437       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1438          v.dump_instructions();
1439
1440       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1441                                         &prog_data->base, v.cfg,
1442                                         final_assembly_size);
1443    }
1444 }