src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "brw_context.h"
  27 }
  28 #include "brw_vs.h"
  29 #include "brw_vec4_gs.h"
  30 #include "brw_fs.h"
  31 #include "brw_cfg.h"
  32 #include "glsl/ir_optimization.h"
  33 #include "glsl/glsl_parser_extras.h"
  34 #include "main/shaderapi.h"
  35
  36 struct gl_shader *
  37 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  38 {
  39    struct brw_shader *shader;
  40
  41    shader = rzalloc(NULL, struct brw_shader);
  42    if (shader) {
  43       shader->base.Type = type;
  44       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  45       shader->base.Name = name;
  46       _mesa_init_shader(ctx, &shader->base);
  47    }
  48
  49    return &shader->base;
  50 }
  51
  52 struct gl_shader_program *
  53 brw_new_shader_program(struct gl_context *ctx, GLuint name)
  54 {
  55    struct gl_shader_program *prog = rzalloc(NULL, struct gl_shader_program);
  56    if (prog) {
  57       prog->Name = name;
  58       _mesa_init_shader_program(ctx, prog);
  59    }
  60    return prog;
  61 }
  62
  63 /**
  64  * Performs a compile of the shader stages even when we don't know
  65  * what non-orthogonal state will be set, in the hope that it reflects
  66  * the eventual NOS used, and thus allows us to produce link failures.
  67  */
  68 static bool
  69 brw_shader_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
  70 {
  71    struct brw_context *brw = brw_context(ctx);
  72
  73    if (brw->precompile && !brw_fs_precompile(ctx, prog))
  74       return false;
  75
  76    if (brw->precompile && !brw_gs_precompile(ctx, prog))
  77       return false;
  78
  79    if (brw->precompile && !brw_vs_precompile(ctx, prog))
  80       return false;
  81
  82    return true;
  83 }
  84
  85 static void
  86 brw_lower_packing_builtins(struct brw_context *brw,
  87                            gl_shader_stage shader_type,
  88                            exec_list *ir)
  89 {
  90    int ops = LOWER_PACK_SNORM_2x16
  91            | LOWER_UNPACK_SNORM_2x16
  92            | LOWER_PACK_UNORM_2x16
  93            | LOWER_UNPACK_UNORM_2x16
  94            | LOWER_PACK_SNORM_4x8
  95            | LOWER_UNPACK_SNORM_4x8
  96            | LOWER_PACK_UNORM_4x8
  97            | LOWER_UNPACK_UNORM_4x8;
  98
  99    if (brw->gen >= 7) {
 100       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 101        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 102        * lowering is needed. For SOA code, the Half2x16 ops must be
 103        * scalarized.
 104        */
 105       if (shader_type == MESA_SHADER_FRAGMENT) {
 106          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 107              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 108       }
 109    } else {
 110       ops |= LOWER_PACK_HALF_2x16
 111           |  LOWER_UNPACK_HALF_2x16;
 112    }
 113
 114    lower_packing_builtins(ir, ops);
 115 }
 116
 117 GLboolean
 118 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 119 {
 120    struct brw_context *brw = brw_context(ctx);
 121    unsigned int stage;
 122
 123    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 124       const struct gl_shader_compiler_options *options =
 125          &ctx->ShaderCompilerOptions[stage];
 126       struct brw_shader *shader =
 127          (struct brw_shader *)shProg->_LinkedShaders[stage];
 128
 129       if (!shader)
 130          continue;
 131
 132       struct gl_program *prog =
 133          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 134                                 shader->base.Name);
 135       if (!prog)
 136         return false;
 137       prog->Parameters = _mesa_new_parameter_list();
 138
 139       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 140
 141       bool progress;
 142
 143       /* lower_packing_builtins() inserts arithmetic instructions, so it
 144        * must precede lower_instructions().
 145        */
 146       brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->base.ir);
 147       do_mat_op_to_vec(shader->base.ir);
 148       const int bitfield_insert = brw->gen >= 7
 149                                   ? BITFIELD_INSERT_TO_BFM_BFI
 150                                   : 0;
 151       lower_instructions(shader->base.ir,
 152                          MOD_TO_FRACT |
 153                          DIV_TO_MUL_RCP |
 154                          SUB_TO_ADD_NEG |
 155                          EXP_TO_EXP2 |
 156                          LOG_TO_LOG2 |
 157                          bitfield_insert |
 158                          LDEXP_TO_ARITH);
 159
 160       /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 161        * if-statements need to be flattened.
 162        */
 163       if (brw->gen < 6)
 164          lower_if_to_cond_assign(shader->base.ir, 16);
 165
 166       do_lower_texture_projection(shader->base.ir);
 167       brw_lower_texture_gradients(brw, shader->base.ir);
 168       do_vec_index_to_cond_assign(shader->base.ir);
 169       lower_vector_insert(shader->base.ir, true);
 170       brw_do_cubemap_normalize(shader->base.ir);
 171       lower_offset_arrays(shader->base.ir);
 172       brw_do_lower_unnormalized_offset(shader->base.ir);
 173       lower_noise(shader->base.ir);
 174       lower_quadop_vector(shader->base.ir, false);
 175
 176       bool lowered_variable_indexing =
 177          lower_variable_index_to_cond_assign(shader->base.ir,
 178                                              options->EmitNoIndirectInput,
 179                                              options->EmitNoIndirectOutput,
 180                                              options->EmitNoIndirectTemp,
 181                                              options->EmitNoIndirectUniform);
 182
 183       if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 184          perf_debug("Unsupported form of variable indexing in FS; falling "
 185                     "back to very inefficient code generation\n");
 186       }
 187
 188       lower_ubo_reference(&shader->base, shader->base.ir);
 189
 190       do {
 191          progress = false;
 192
 193          if (stage == MESA_SHADER_FRAGMENT) {
 194             brw_do_channel_expressions(shader->base.ir);
 195             brw_do_vector_splitting(shader->base.ir);
 196          }
 197
 198          progress = do_lower_jumps(shader->base.ir, true, true,
 199                                    true, /* main return */
 200                                    false, /* continue */
 201                                    false /* loops */
 202                                    ) || progress;
 203
 204          progress = do_common_optimization(shader->base.ir, true, true,
 205                                            options, ctx->Const.NativeIntegers)
 206            || progress;
 207       } while (progress);
 208
 209       /* Make a pass over the IR to add state references for any built-in
 210        * uniforms that are used.  This has to be done now (during linking).
 211        * Code generation doesn't happen until the first time this shader is
 212        * used for rendering.  Waiting until then to generate the parameters is
 213        * too late.  At that point, the values for the built-in uniforms won't
 214        * get sent to the shader.
 215        */
 216       foreach_list(node, shader->base.ir) {
 217          ir_variable *var = ((ir_instruction *) node)->as_variable();
 218
 219          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 220              || (strncmp(var->name, "gl_", 3) != 0))
 221             continue;
 222
 223          const ir_state_slot *const slots = var->state_slots;
 224          assert(var->state_slots != NULL);
 225
 226          for (unsigned int i = 0; i < var->num_state_slots; i++) {
 227             _mesa_add_state_reference(prog->Parameters,
 228                                       (gl_state_index *) slots[i].tokens);
 229          }
 230       }
 231
 232       validate_ir_tree(shader->base.ir);
 233
 234       do_set_program_inouts(shader->base.ir, prog, shader->base.Stage);
 235
 236       prog->SamplersUsed = shader->base.active_samplers;
 237       _mesa_update_shader_textures_used(shProg, prog);
 238
 239       _mesa_reference_program(ctx, &shader->base.Program, prog);
 240
 241       brw_add_texrect_params(prog);
 242
 243       /* This has to be done last.  Any operation that can cause
 244        * prog->ParameterValues to get reallocated (e.g., anything that adds a
 245        * program constant) has to happen before creating this linkage.
 246        */
 247       _mesa_associate_uniform_storage(ctx, shProg, prog->Parameters);
 248
 249       _mesa_reference_program(ctx, &prog, NULL);
 250
 251       if (ctx->_Shader->Flags & GLSL_DUMP) {
 252          fprintf(stderr, "\n");
 253          fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 254                  _mesa_shader_stage_to_string(shader->base.Stage),
 255                  shProg->Name);
 256          _mesa_print_ir(stderr, shader->base.ir, NULL);
 257          fprintf(stderr, "\n");
 258       }
 259    }
 260
 261    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 262       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 263          const struct gl_shader *sh = shProg->Shaders[i];
 264          if (!sh)
 265             continue;
 266
 267          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 268                  _mesa_shader_stage_to_string(sh->Stage),
 269                  i, shProg->Name);
 270          fprintf(stderr, "%s", sh->Source);
 271          fprintf(stderr, "\n");
 272       }
 273    }
 274
 275    if (!brw_shader_precompile(ctx, shProg))
 276       return false;
 277
 278    return true;
 279 }
 280
 281
 282 int
 283 brw_type_for_base_type(const struct glsl_type *type)
 284 {
 285    switch (type->base_type) {
 286    case GLSL_TYPE_FLOAT:
 287       return BRW_REGISTER_TYPE_F;
 288    case GLSL_TYPE_INT:
 289    case GLSL_TYPE_BOOL:
 290       return BRW_REGISTER_TYPE_D;
 291    case GLSL_TYPE_UINT:
 292       return BRW_REGISTER_TYPE_UD;
 293    case GLSL_TYPE_ARRAY:
 294       return brw_type_for_base_type(type->fields.array);
 295    case GLSL_TYPE_STRUCT:
 296    case GLSL_TYPE_SAMPLER:
 297    case GLSL_TYPE_ATOMIC_UINT:
 298       /* These should be overridden with the type of the member when
 299        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 300        * way to trip up if we don't.
 301        */
 302       return BRW_REGISTER_TYPE_UD;
 303    case GLSL_TYPE_IMAGE:
 304       return BRW_REGISTER_TYPE_UD;
 305    case GLSL_TYPE_VOID:
 306    case GLSL_TYPE_ERROR:
 307    case GLSL_TYPE_INTERFACE:
 308       assert(!"not reached");
 309       break;
 310    }
 311
 312    return BRW_REGISTER_TYPE_F;
 313 }
 314
 315 uint32_t
 316 brw_conditional_for_comparison(unsigned int op)
 317 {
 318    switch (op) {
 319    case ir_binop_less:
 320       return BRW_CONDITIONAL_L;
 321    case ir_binop_greater:
 322       return BRW_CONDITIONAL_G;
 323    case ir_binop_lequal:
 324       return BRW_CONDITIONAL_LE;
 325    case ir_binop_gequal:
 326       return BRW_CONDITIONAL_GE;
 327    case ir_binop_equal:
 328    case ir_binop_all_equal: /* same as equal for scalars */
 329       return BRW_CONDITIONAL_Z;
 330    case ir_binop_nequal:
 331    case ir_binop_any_nequal: /* same as nequal for scalars */
 332       return BRW_CONDITIONAL_NZ;
 333    default:
 334       assert(!"not reached: bad operation for comparison");
 335       return BRW_CONDITIONAL_NZ;
 336    }
 337 }
 338
 339 uint32_t
 340 brw_math_function(enum opcode op)
 341 {
 342    switch (op) {
 343    case SHADER_OPCODE_RCP:
 344       return BRW_MATH_FUNCTION_INV;
 345    case SHADER_OPCODE_RSQ:
 346       return BRW_MATH_FUNCTION_RSQ;
 347    case SHADER_OPCODE_SQRT:
 348       return BRW_MATH_FUNCTION_SQRT;
 349    case SHADER_OPCODE_EXP2:
 350       return BRW_MATH_FUNCTION_EXP;
 351    case SHADER_OPCODE_LOG2:
 352       return BRW_MATH_FUNCTION_LOG;
 353    case SHADER_OPCODE_POW:
 354       return BRW_MATH_FUNCTION_POW;
 355    case SHADER_OPCODE_SIN:
 356       return BRW_MATH_FUNCTION_SIN;
 357    case SHADER_OPCODE_COS:
 358       return BRW_MATH_FUNCTION_COS;
 359    case SHADER_OPCODE_INT_QUOTIENT:
 360       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 361    case SHADER_OPCODE_INT_REMAINDER:
 362       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 363    default:
 364       assert(!"not reached: unknown math function");
 365       return 0;
 366    }
 367 }
 368
 369 uint32_t
 370 brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
 371 {
 372    /* If the driver does not support GL_ARB_gpu_shader5, the offset
 373     * must be constant.
 374     */
 375    assert(offset != NULL || ctx->Extensions.ARB_gpu_shader5);
 376
 377    if (!offset) return 0;  /* nonconstant offset; caller will handle it. */
 378
 379    signed char offsets[3];
 380    for (unsigned i = 0; i < offset->type->vector_elements; i++)
 381       offsets[i] = (signed char) offset->value.i[i];
 382
 383    /* Combine all three offsets into a single unsigned dword:
 384     *
 385     *    bits 11:8 - U Offset (X component)
 386     *    bits  7:4 - V Offset (Y component)
 387     *    bits  3:0 - R Offset (Z component)
 388     */
 389    unsigned offset_bits = 0;
 390    for (unsigned i = 0; i < offset->type->vector_elements; i++) {
 391       const unsigned shift = 4 * (2 - i);
 392       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 393    }
 394    return offset_bits;
 395 }
 396
 397 const char *
 398 brw_instruction_name(enum opcode op)
 399 {
 400    char *fallback;
 401
 402    if (op < ARRAY_SIZE(opcode_descs) && opcode_descs[op].name)
 403       return opcode_descs[op].name;
 404
 405    switch (op) {
 406    case FS_OPCODE_FB_WRITE:
 407       return "fb_write";
 408    case FS_OPCODE_BLORP_FB_WRITE:
 409       return "blorp_fb_write";
 410
 411    case SHADER_OPCODE_RCP:
 412       return "rcp";
 413    case SHADER_OPCODE_RSQ:
 414       return "rsq";
 415    case SHADER_OPCODE_SQRT:
 416       return "sqrt";
 417    case SHADER_OPCODE_EXP2:
 418       return "exp2";
 419    case SHADER_OPCODE_LOG2:
 420       return "log2";
 421    case SHADER_OPCODE_POW:
 422       return "pow";
 423    case SHADER_OPCODE_INT_QUOTIENT:
 424       return "int_quot";
 425    case SHADER_OPCODE_INT_REMAINDER:
 426       return "int_rem";
 427    case SHADER_OPCODE_SIN:
 428       return "sin";
 429    case SHADER_OPCODE_COS:
 430       return "cos";
 431
 432    case SHADER_OPCODE_TEX:
 433       return "tex";
 434    case SHADER_OPCODE_TXD:
 435       return "txd";
 436    case SHADER_OPCODE_TXF:
 437       return "txf";
 438    case SHADER_OPCODE_TXL:
 439       return "txl";
 440    case SHADER_OPCODE_TXS:
 441       return "txs";
 442    case FS_OPCODE_TXB:
 443       return "txb";
 444    case SHADER_OPCODE_TXF_CMS:
 445       return "txf_cms";
 446    case SHADER_OPCODE_TXF_UMS:
 447       return "txf_ums";
 448    case SHADER_OPCODE_TXF_MCS:
 449       return "txf_mcs";
 450    case SHADER_OPCODE_TG4:
 451       return "tg4";
 452    case SHADER_OPCODE_TG4_OFFSET:
 453       return "tg4_offset";
 454    case SHADER_OPCODE_SHADER_TIME_ADD:
 455       return "shader_time_add";
 456
 457    case SHADER_OPCODE_LOAD_PAYLOAD:
 458       return "load_payload";
 459
 460    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 461       return "gen4_scratch_read";
 462    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 463       return "gen4_scratch_write";
 464    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 465       return "gen7_scratch_read";
 466
 467    case FS_OPCODE_DDX:
 468       return "ddx";
 469    case FS_OPCODE_DDY:
 470       return "ddy";
 471
 472    case FS_OPCODE_PIXEL_X:
 473       return "pixel_x";
 474    case FS_OPCODE_PIXEL_Y:
 475       return "pixel_y";
 476
 477    case FS_OPCODE_CINTERP:
 478       return "cinterp";
 479    case FS_OPCODE_LINTERP:
 480       return "linterp";
 481
 482    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 483       return "uniform_pull_const";
 484    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 485       return "uniform_pull_const_gen7";
 486    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 487       return "varying_pull_const";
 488    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 489       return "varying_pull_const_gen7";
 490
 491    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 492       return "mov_dispatch_to_flags";
 493    case FS_OPCODE_DISCARD_JUMP:
 494       return "discard_jump";
 495
 496    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 497       return "set_simd4x2_offset";
 498
 499    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 500       return "pack_half_2x16_split";
 501    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 502       return "unpack_half_2x16_split_x";
 503    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 504       return "unpack_half_2x16_split_y";
 505
 506    case FS_OPCODE_PLACEHOLDER_HALT:
 507       return "placeholder_halt";
 508
 509    case VS_OPCODE_URB_WRITE:
 510       return "vs_urb_write";
 511    case VS_OPCODE_PULL_CONSTANT_LOAD:
 512       return "pull_constant_load";
 513    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 514       return "pull_constant_load_gen7";
 515    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 516       return "unpack_flags_simd4x2";
 517
 518    case GS_OPCODE_URB_WRITE:
 519       return "gs_urb_write";
 520    case GS_OPCODE_THREAD_END:
 521       return "gs_thread_end";
 522    case GS_OPCODE_SET_WRITE_OFFSET:
 523       return "set_write_offset";
 524    case GS_OPCODE_SET_VERTEX_COUNT:
 525       return "set_vertex_count";
 526    case GS_OPCODE_SET_DWORD_2_IMMED:
 527       return "set_dword_2_immed";
 528    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 529       return "prepare_channel_masks";
 530    case GS_OPCODE_SET_CHANNEL_MASKS:
 531       return "set_channel_masks";
 532    case GS_OPCODE_GET_INSTANCE_ID:
 533       return "get_instance_id";
 534
 535    default:
 536       /* Yes, this leaks.  It's in debug code, it should never occur, and if
 537        * it does, you should just add the case to the list above.
 538        */
 539       asprintf(&fallback, "op%d", op);
 540       return fallback;
 541    }
 542 }
 543
 544 backend_visitor::backend_visitor(struct brw_context *brw,
 545                                  struct gl_shader_program *shader_prog,
 546                                  struct gl_program *prog,
 547                                  struct brw_stage_prog_data *stage_prog_data,
 548                                  gl_shader_stage stage)
 549    : brw(brw),
 550      ctx(&brw->ctx),
 551      shader(shader_prog ?
 552         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 553      shader_prog(shader_prog),
 554      prog(prog),
 555      stage_prog_data(stage_prog_data)
 556 {
 557 }
 558
 559 bool
 560 backend_instruction::is_tex() const
 561 {
 562    return (opcode == SHADER_OPCODE_TEX ||
 563            opcode == FS_OPCODE_TXB ||
 564            opcode == SHADER_OPCODE_TXD ||
 565            opcode == SHADER_OPCODE_TXF ||
 566            opcode == SHADER_OPCODE_TXF_CMS ||
 567            opcode == SHADER_OPCODE_TXF_UMS ||
 568            opcode == SHADER_OPCODE_TXF_MCS ||
 569            opcode == SHADER_OPCODE_TXL ||
 570            opcode == SHADER_OPCODE_TXS ||
 571            opcode == SHADER_OPCODE_LOD ||
 572            opcode == SHADER_OPCODE_TG4 ||
 573            opcode == SHADER_OPCODE_TG4_OFFSET);
 574 }
 575
 576 bool
 577 backend_instruction::is_math() const
 578 {
 579    return (opcode == SHADER_OPCODE_RCP ||
 580            opcode == SHADER_OPCODE_RSQ ||
 581            opcode == SHADER_OPCODE_SQRT ||
 582            opcode == SHADER_OPCODE_EXP2 ||
 583            opcode == SHADER_OPCODE_LOG2 ||
 584            opcode == SHADER_OPCODE_SIN ||
 585            opcode == SHADER_OPCODE_COS ||
 586            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 587            opcode == SHADER_OPCODE_INT_REMAINDER ||
 588            opcode == SHADER_OPCODE_POW);
 589 }
 590
 591 bool
 592 backend_instruction::is_control_flow() const
 593 {
 594    switch (opcode) {
 595    case BRW_OPCODE_DO:
 596    case BRW_OPCODE_WHILE:
 597    case BRW_OPCODE_IF:
 598    case BRW_OPCODE_ELSE:
 599    case BRW_OPCODE_ENDIF:
 600    case BRW_OPCODE_BREAK:
 601    case BRW_OPCODE_CONTINUE:
 602       return true;
 603    default:
 604       return false;
 605    }
 606 }
 607
 608 bool
 609 backend_instruction::can_do_source_mods() const
 610 {
 611    switch (opcode) {
 612    case BRW_OPCODE_ADDC:
 613    case BRW_OPCODE_BFE:
 614    case BRW_OPCODE_BFI1:
 615    case BRW_OPCODE_BFI2:
 616    case BRW_OPCODE_BFREV:
 617    case BRW_OPCODE_CBIT:
 618    case BRW_OPCODE_FBH:
 619    case BRW_OPCODE_FBL:
 620    case BRW_OPCODE_SUBB:
 621       return false;
 622    default:
 623       return true;
 624    }
 625 }
 626
 627 bool
 628 backend_instruction::can_do_saturate() const
 629 {
 630    switch (opcode) {
 631    case BRW_OPCODE_ADD:
 632    case BRW_OPCODE_ASR:
 633    case BRW_OPCODE_AVG:
 634    case BRW_OPCODE_DP2:
 635    case BRW_OPCODE_DP3:
 636    case BRW_OPCODE_DP4:
 637    case BRW_OPCODE_DPH:
 638    case BRW_OPCODE_F16TO32:
 639    case BRW_OPCODE_F32TO16:
 640    case BRW_OPCODE_LINE:
 641    case BRW_OPCODE_LRP:
 642    case BRW_OPCODE_MAC:
 643    case BRW_OPCODE_MACH:
 644    case BRW_OPCODE_MAD:
 645    case BRW_OPCODE_MATH:
 646    case BRW_OPCODE_MOV:
 647    case BRW_OPCODE_MUL:
 648    case BRW_OPCODE_PLN:
 649    case BRW_OPCODE_RNDD:
 650    case BRW_OPCODE_RNDE:
 651    case BRW_OPCODE_RNDU:
 652    case BRW_OPCODE_RNDZ:
 653    case BRW_OPCODE_SEL:
 654    case BRW_OPCODE_SHL:
 655    case BRW_OPCODE_SHR:
 656    case FS_OPCODE_LINTERP:
 657    case SHADER_OPCODE_COS:
 658    case SHADER_OPCODE_EXP2:
 659    case SHADER_OPCODE_LOG2:
 660    case SHADER_OPCODE_POW:
 661    case SHADER_OPCODE_RCP:
 662    case SHADER_OPCODE_RSQ:
 663    case SHADER_OPCODE_SIN:
 664    case SHADER_OPCODE_SQRT:
 665       return true;
 666    default:
 667       return false;
 668    }
 669 }
 670
 671 bool
 672 backend_instruction::reads_accumulator_implicitly() const
 673 {
 674    switch (opcode) {
 675    case BRW_OPCODE_MAC:
 676    case BRW_OPCODE_MACH:
 677    case BRW_OPCODE_SADA2:
 678       return true;
 679    default:
 680       return false;
 681    }
 682 }
 683
 684 bool
 685 backend_instruction::writes_accumulator_implicitly(struct brw_context *brw) const
 686 {
 687    return writes_accumulator ||
 688           (brw->gen < 6 &&
 689            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 690             (opcode >= FS_OPCODE_DDX && opcode <= FS_OPCODE_LINTERP &&
 691              opcode != FS_OPCODE_CINTERP)));
 692 }
 693
 694 bool
 695 backend_instruction::has_side_effects() const
 696 {
 697    switch (opcode) {
 698    case SHADER_OPCODE_UNTYPED_ATOMIC:
 699       return true;
 700    default:
 701       return false;
 702    }
 703 }
 704
 705 void
 706 backend_visitor::dump_instructions()
 707 {
 708    dump_instructions(NULL);
 709 }
 710
 711 void
 712 backend_visitor::dump_instructions(const char *name)
 713 {
 714    FILE *file = stderr;
 715    if (name && geteuid() != 0) {
 716       file = fopen(name, "w");
 717       if (!file)
 718          file = stderr;
 719    }
 720
 721    int ip = 0;
 722    foreach_list(node, &this->instructions) {
 723       backend_instruction *inst = (backend_instruction *)node;
 724       if (!name)
 725          fprintf(stderr, "%d: ", ip++);
 726       dump_instruction(inst, file);
 727    }
 728
 729    if (file != stderr) {
 730       fclose(file);
 731    }
 732 }
 733
 734
 735 /**
 736  * Sets up the starting offsets for the groups of binding table entries
 737  * commong to all pipeline stages.
 738  *
 739  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
 740  * unused but also make sure that addition of small offsets to them will
 741  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
 742  */
 743 void
 744 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
 745 {
 746    int num_textures = _mesa_fls(prog->SamplersUsed);
 747
 748    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
 749    next_binding_table_offset += num_textures;
 750
 751    if (shader) {
 752       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
 753       next_binding_table_offset += shader->base.NumUniformBlocks;
 754    } else {
 755       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
 756    }
 757
 758    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
 759       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
 760       next_binding_table_offset++;
 761    } else {
 762       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
 763    }
 764
 765    if (prog->UsesGather) {
 766       if (brw->gen >= 8) {
 767          stage_prog_data->binding_table.gather_texture_start =
 768             stage_prog_data->binding_table.texture_start;
 769       } else {
 770          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
 771          next_binding_table_offset += num_textures;
 772       }
 773    } else {
 774       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
 775    }
 776
 777    if (shader_prog && shader_prog->NumAtomicBuffers) {
 778       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
 779       next_binding_table_offset += shader_prog->NumAtomicBuffers;
 780    } else {
 781       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
 782    }
 783
 784    /* This may or may not be used depending on how the compile goes. */
 785    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
 786    next_binding_table_offset++;
 787
 788    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
 789
 790    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
 791 }
 792
 793 void annotate(struct brw_context *brw,
 794               struct annotation_info *annotation, cfg_t *cfg,
 795               backend_instruction *inst, unsigned offset)
 796 {
 797    if (annotation->ann_size <= annotation->ann_count) {
 798       annotation->ann_size = MAX2(1024, annotation->ann_size * 2);
 799       annotation->ann = reralloc(annotation->mem_ctx, annotation->ann,
 800                                  struct annotation, annotation->ann_size);
 801       if (!annotation->ann)
 802          return;
 803    }
 804
 805    struct annotation *ann = &annotation->ann[annotation->ann_count++];
 806    ann->offset = offset;
 807    if ((INTEL_DEBUG & DEBUG_NO_ANNOTATION) == 0) {
 808       ann->ir = inst->ir;
 809       ann->annotation = inst->annotation;
 810    }
 811
 812    if (cfg->blocks[annotation->cur_block]->start == inst) {
 813       ann->block_start = cfg->blocks[annotation->cur_block];
 814    }
 815
 816    /* There is no hardware DO instruction on Gen6+, so since DO always
 817     * starts a basic block, we need to set the .block_start of the next
 818     * instruction's annotation with a pointer to the bblock started by
 819     * the DO.
 820     *
 821     * There's also only complication from emitting an annotation without
 822     * a corresponding hardware instruction to disassemble.
 823     */
 824    if (brw->gen >= 6 && inst->opcode == BRW_OPCODE_DO) {
 825       annotation->ann_count--;
 826    }
 827
 828    if (cfg->blocks[annotation->cur_block]->end == inst) {
 829       ann->block_end = cfg->blocks[annotation->cur_block];
 830       annotation->cur_block++;
 831    }
 832 }
 833
 834 void
 835 annotation_finalize(struct annotation_info *annotation,
 836                     unsigned next_inst_offset)
 837 {
 838    if (!annotation->ann_count)
 839       return;
 840
 841    if (annotation->ann_count == annotation->ann_size) {
 842       annotation->ann = reralloc(annotation->mem_ctx, annotation->ann,
 843                                  struct annotation, annotation->ann_size + 1);
 844    }
 845    annotation->ann[annotation->ann_count].offset = next_inst_offset;
 846 }