2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_defines.h"
27 #include "main/compiler.h"
31 #include "brw_ir_allocator.h"
36 enum PACKED register_file
{
41 HW_REG
, /* a struct brw_reg */
43 UNIFORM
, /* prog_data->params[reg] */
52 bool is_accumulator() const;
55 enum register_file file
; /**< Register file: GRF, MRF, IMM. */
56 enum brw_reg_type type
; /**< Register type: BRW_REGISTER_TYPE_* */
61 * For GRF, it's a virtual register number until register allocation.
63 * For MRF, it's the hardware register.
68 * Offset within the virtual register.
70 * In the scalar backend, this is in units of a float per pixel for pre-
71 * register allocation registers (i.e., one register in SIMD8 mode and two
72 * registers in SIMD16 mode).
74 * For uniforms, this is in units of 1 float.
78 struct brw_reg fixed_hw_reg
;
88 struct backend_instruction
: public exec_node
{
92 bool is_control_flow() const;
93 bool can_do_source_mods() const;
94 bool can_do_saturate() const;
95 bool can_do_cmod() const;
96 bool reads_accumulator_implicitly() const;
97 bool writes_accumulator_implicitly(struct brw_context
*brw
) const;
99 void remove(bblock_t
*block
);
100 void insert_after(bblock_t
*block
, backend_instruction
*inst
);
101 void insert_before(bblock_t
*block
, backend_instruction
*inst
);
102 void insert_before(bblock_t
*block
, exec_list
*list
);
105 * True if the instruction has side effects other than writing to
106 * its destination registers. You are expected not to reorder or
107 * optimize these out unless you know what you are doing.
109 bool has_side_effects() const;
111 struct backend_instruction
{
112 struct exec_node link
;
115 * Annotation for the generated IR. One of the two can be set.
118 const char *annotation
;
121 uint32_t offset
; /**< spill/unspill offset or texture offset bitfield */
122 uint8_t mlen
; /**< SEND message length */
123 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
124 uint8_t target
; /**< MRT target. */
125 uint8_t regs_written
; /**< Number of registers written by the instruction. */
127 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
128 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
129 enum brw_predicate predicate
;
130 bool predicate_inverse
:1;
131 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
132 bool force_writemask_all
:1;
136 bool shadow_compare
:1;
137 bool header_present
:1;
142 enum instruction_scheduler_mode
{
144 SCHEDULE_PRE_NON_LIFO
,
149 class backend_visitor
: public ir_visitor
{
152 backend_visitor(struct brw_context
*brw
,
153 struct gl_shader_program
*shader_prog
,
154 struct gl_program
*prog
,
155 struct brw_stage_prog_data
*stage_prog_data
,
156 gl_shader_stage stage
);
160 struct brw_context
* const brw
;
161 struct gl_context
* const ctx
;
162 struct brw_shader
* const shader
;
163 struct gl_shader_program
* const shader_prog
;
164 struct gl_program
* const prog
;
165 struct brw_stage_prog_data
* const stage_prog_data
;
167 /** ralloc context for temporary data used during compile */
171 * List of either fs_inst or vec4_instruction (inheriting from
172 * backend_instruction)
174 exec_list instructions
;
178 gl_shader_stage stage
;
180 brw::simple_allocator alloc
;
182 virtual void dump_instruction(backend_instruction
*inst
) = 0;
183 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
184 virtual void dump_instructions();
185 virtual void dump_instructions(const char *name
);
187 void calculate_cfg();
188 void invalidate_cfg();
190 void assign_common_binding_table_offsets(uint32_t next_binding_table_offset
);
192 virtual void invalidate_live_intervals() = 0;
195 uint32_t brw_texture_offset(struct gl_context
*ctx
, int *offsets
,
196 unsigned num_components
);
198 #endif /* __cplusplus */
200 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
201 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
202 uint32_t brw_math_function(enum opcode op
);
203 const char *brw_instruction_name(enum opcode op
);
204 bool brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
205 bool brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
206 bool brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
212 bool brw_vs_precompile(struct gl_context
*ctx
,
213 struct gl_shader_program
*shader_prog
,
214 struct gl_program
*prog
);
215 bool brw_gs_precompile(struct gl_context
*ctx
,
216 struct gl_shader_program
*shader_prog
,
217 struct gl_program
*prog
);
218 bool brw_fs_precompile(struct gl_context
*ctx
,
219 struct gl_shader_program
*shader_prog
,
220 struct gl_program
*prog
);