2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_defines.h"
27 #include "main/compiler.h"
32 enum PACKED register_file
{
37 HW_REG
, /* a struct brw_reg */
39 UNIFORM
, /* prog_data->params[reg] */
48 bool is_accumulator() const;
51 enum register_file file
; /**< Register file: GRF, MRF, IMM. */
52 enum brw_reg_type type
; /**< Register type: BRW_REGISTER_TYPE_* */
57 * For GRF, it's a virtual register number until register allocation.
59 * For MRF, it's the hardware register.
64 * Offset within the virtual register.
66 * In the scalar backend, this is in units of a float per pixel for pre-
67 * register allocation registers (i.e., one register in SIMD8 mode and two
68 * registers in SIMD16 mode).
70 * For uniforms, this is in units of 1 float.
74 struct brw_reg fixed_hw_reg
;
84 struct backend_instruction
: public exec_node
{
87 bool is_control_flow() const;
88 bool can_do_source_mods() const;
89 bool can_do_saturate() const;
90 bool reads_accumulator_implicitly() const;
91 bool writes_accumulator_implicitly(struct brw_context
*brw
) const;
93 void remove(bblock_t
*block
);
94 void insert_after(bblock_t
*block
, backend_instruction
*inst
);
95 void insert_before(bblock_t
*block
, backend_instruction
*inst
);
96 void insert_before(bblock_t
*block
, exec_list
*list
);
99 * True if the instruction has side effects other than writing to
100 * its destination registers. You are expected not to reorder or
101 * optimize these out unless you know what you are doing.
103 bool has_side_effects() const;
105 struct backend_instruction
{
106 struct exec_node link
;
109 * Annotation for the generated IR. One of the two can be set.
112 const char *annotation
;
115 uint32_t offset
; /**< spill/unspill offset or texture offset bitfield */
116 uint8_t mlen
; /**< SEND message length */
117 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
118 uint8_t target
; /**< MRT target. */
120 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
121 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
122 enum brw_predicate predicate
;
123 bool predicate_inverse
:1;
124 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
125 bool force_writemask_all
:1;
129 bool shadow_compare
:1;
130 bool header_present
:1;
135 enum instruction_scheduler_mode
{
137 SCHEDULE_PRE_NON_LIFO
,
142 class backend_visitor
: public ir_visitor
{
145 backend_visitor(struct brw_context
*brw
,
146 struct gl_shader_program
*shader_prog
,
147 struct gl_program
*prog
,
148 struct brw_stage_prog_data
*stage_prog_data
,
149 gl_shader_stage stage
);
153 struct brw_context
* const brw
;
154 struct gl_context
* const ctx
;
155 struct brw_shader
* const shader
;
156 struct gl_shader_program
* const shader_prog
;
157 struct gl_program
* const prog
;
158 struct brw_stage_prog_data
* const stage_prog_data
;
160 /** ralloc context for temporary data used during compile */
164 * List of either fs_inst or vec4_instruction (inheriting from
165 * backend_instruction)
167 exec_list instructions
;
171 gl_shader_stage stage
;
173 virtual void dump_instruction(backend_instruction
*inst
) = 0;
174 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
175 virtual void dump_instructions();
176 virtual void dump_instructions(const char *name
);
178 void calculate_cfg();
179 void invalidate_cfg();
181 void assign_common_binding_table_offsets(uint32_t next_binding_table_offset
);
183 virtual void invalidate_live_intervals() = 0;
186 uint32_t brw_texture_offset(struct gl_context
*ctx
, int *offsets
,
187 unsigned num_components
);
189 #endif /* __cplusplus */
191 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
192 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
193 uint32_t brw_math_function(enum opcode op
);
194 const char *brw_instruction_name(enum opcode op
);
200 bool brw_vs_precompile(struct gl_context
*ctx
,
201 struct gl_shader_program
*shader_prog
,
202 struct gl_program
*prog
);
203 bool brw_gs_precompile(struct gl_context
*ctx
,
204 struct gl_shader_program
*shader_prog
,
205 struct gl_program
*prog
);
206 bool brw_fs_precompile(struct gl_context
*ctx
,
207 struct gl_shader_program
*shader_prog
,
208 struct gl_program
*prog
);