2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_defines.h"
27 #include "main/compiler.h"
32 enum PACKED register_file
{
37 HW_REG
, /* a struct brw_reg */
39 UNIFORM
, /* prog_data->params[reg] */
48 bool is_accumulator() const;
51 enum register_file file
; /**< Register file: GRF, MRF, IMM. */
52 enum brw_reg_type type
; /**< Register type: BRW_REGISTER_TYPE_* */
57 * For GRF, it's a virtual register number until register allocation.
59 * For MRF, it's the hardware register.
64 * Offset within the virtual register.
66 * In the scalar backend, this is in units of a float per pixel for pre-
67 * register allocation registers (i.e., one register in SIMD8 mode and two
68 * registers in SIMD16 mode).
70 * For uniforms, this is in units of 1 float.
74 struct brw_reg fixed_hw_reg
;
83 struct backend_instruction
: public exec_node
{
86 bool is_control_flow() const;
87 bool can_do_source_mods() const;
88 bool can_do_saturate() const;
89 bool reads_accumulator_implicitly() const;
90 bool writes_accumulator_implicitly(struct brw_context
*brw
) const;
93 * True if the instruction has side effects other than writing to
94 * its destination registers. You are expected not to reorder or
95 * optimize these out unless you know what you are doing.
97 bool has_side_effects() const;
99 struct backend_instruction
{
100 struct exec_node link
;
103 * Annotation for the generated IR. One of the two can be set.
106 const char *annotation
;
109 uint32_t texture_offset
; /**< Texture offset bitfield */
110 uint32_t offset
; /**< spill/unspill offset */
112 uint8_t mlen
; /**< SEND message length */
113 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
114 uint8_t target
; /**< MRT target. */
116 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
117 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
118 enum brw_predicate predicate
;
119 bool predicate_inverse
:1;
120 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
121 bool force_writemask_all
:1;
129 enum instruction_scheduler_mode
{
131 SCHEDULE_PRE_NON_LIFO
,
136 class backend_visitor
: public ir_visitor
{
139 backend_visitor(struct brw_context
*brw
,
140 struct gl_shader_program
*shader_prog
,
141 struct gl_program
*prog
,
142 struct brw_stage_prog_data
*stage_prog_data
,
143 gl_shader_stage stage
);
147 struct brw_context
* const brw
;
148 struct gl_context
* const ctx
;
149 struct brw_shader
* const shader
;
150 struct gl_shader_program
* const shader_prog
;
151 struct gl_program
* const prog
;
152 struct brw_stage_prog_data
* const stage_prog_data
;
154 /** ralloc context for temporary data used during compile */
158 * List of either fs_inst or vec4_instruction (inheriting from
159 * backend_instruction)
161 exec_list instructions
;
165 virtual void dump_instruction(backend_instruction
*inst
) = 0;
166 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
167 virtual void dump_instructions();
168 virtual void dump_instructions(const char *name
);
170 void calculate_cfg();
171 void invalidate_cfg();
173 void assign_common_binding_table_offsets(uint32_t next_binding_table_offset
);
175 virtual void invalidate_live_intervals() = 0;
178 uint32_t brw_texture_offset(struct gl_context
*ctx
, ir_constant
*offset
);
180 #endif /* __cplusplus */
182 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
183 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
184 uint32_t brw_math_function(enum opcode op
);
185 const char *brw_instruction_name(enum opcode op
);