src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_reg.h"
  26 #include "brw_defines.h"
  27 #include "main/compiler.h"
  28 #include "glsl/ir.h"
  29
  30 #ifdef __cplusplus
  31 #include "brw_ir_allocator.h"
  32 #endif
  33
  34 #pragma once
  35
  36 enum PACKED register_file {
  37    BAD_FILE,
  38    GRF,
  39    MRF,
  40    IMM,
  41    HW_REG, /* a struct brw_reg */
  42    ATTR,
  43    UNIFORM, /* prog_data->params[reg] */
  44 };
  45
  46 struct backend_reg
  47 {
  48 #ifdef __cplusplus
  49    bool is_zero() const;
  50    bool is_one() const;
  51    bool is_null() const;
  52    bool is_accumulator() const;
  53 #endif
  54
  55    enum register_file file; /**< Register file: GRF, MRF, IMM. */
  56    enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
  57
  58    /**
  59     * Register number.
  60     *
  61     * For GRF, it's a virtual register number until register allocation.
  62     *
  63     * For MRF, it's the hardware register.
  64     */
  65    uint16_t reg;
  66
  67    /**
  68     * Offset within the virtual register.
  69     *
  70     * In the scalar backend, this is in units of a float per pixel for pre-
  71     * register allocation registers (i.e., one register in SIMD8 mode and two
  72     * registers in SIMD16 mode).
  73     *
  74     * For uniforms, this is in units of 1 float.
  75     */
  76    int reg_offset;
  77
  78    struct brw_reg fixed_hw_reg;
  79
  80    bool negate;
  81    bool abs;
  82 };
  83
  84 struct cfg_t;
  85 struct bblock_t;
  86
  87 #ifdef __cplusplus
  88 struct backend_instruction : public exec_node {
  89    bool is_3src() const;
  90    bool is_tex() const;
  91    bool is_math() const;
  92    bool is_control_flow() const;
  93    bool can_do_source_mods() const;
  94    bool can_do_saturate() const;
  95    bool can_do_cmod() const;
  96    bool reads_accumulator_implicitly() const;
  97    bool writes_accumulator_implicitly(struct brw_context *brw) const;
  98
  99    void remove(bblock_t *block);
 100    void insert_after(bblock_t *block, backend_instruction *inst);
 101    void insert_before(bblock_t *block, backend_instruction *inst);
 102    void insert_before(bblock_t *block, exec_list *list);
 103
 104    /**
 105     * True if the instruction has side effects other than writing to
 106     * its destination registers.  You are expected not to reorder or
 107     * optimize these out unless you know what you are doing.
 108     */
 109    bool has_side_effects() const;
 110 #else
 111 struct backend_instruction {
 112    struct exec_node link;
 113 #endif
 114    /** @{
 115     * Annotation for the generated IR.  One of the two can be set.
 116     */
 117    const void *ir;
 118    const char *annotation;
 119    /** @} */
 120
 121    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 122    uint8_t mlen; /**< SEND message length */
 123    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 124    uint8_t target; /**< MRT target. */
 125    uint8_t regs_written; /**< Number of registers written by the instruction. */
 126
 127    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 128    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 129    enum brw_predicate predicate;
 130    bool predicate_inverse:1;
 131    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 132    bool force_writemask_all:1;
 133    bool no_dd_clear:1;
 134    bool no_dd_check:1;
 135    bool saturate:1;
 136    bool shadow_compare:1;
 137    bool header_present:1;
 138
 139    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 140     * mod and predication.
 141     */
 142    unsigned flag_subreg:1;
 143 };
 144
 145 #ifdef __cplusplus
 146
 147 enum instruction_scheduler_mode {
 148    SCHEDULE_PRE,
 149    SCHEDULE_PRE_NON_LIFO,
 150    SCHEDULE_PRE_LIFO,
 151    SCHEDULE_POST,
 152 };
 153
 154 class backend_visitor : public ir_visitor {
 155 protected:
 156
 157    backend_visitor(struct brw_context *brw,
 158                    struct gl_shader_program *shader_prog,
 159                    struct gl_program *prog,
 160                    struct brw_stage_prog_data *stage_prog_data,
 161                    gl_shader_stage stage);
 162
 163 public:
 164
 165    struct brw_context * const brw;
 166    struct gl_context * const ctx;
 167    struct brw_shader * const shader;
 168    struct gl_shader_program * const shader_prog;
 169    struct gl_program * const prog;
 170    struct brw_stage_prog_data * const stage_prog_data;
 171
 172    /** ralloc context for temporary data used during compile */
 173    void *mem_ctx;
 174
 175    /**
 176     * List of either fs_inst or vec4_instruction (inheriting from
 177     * backend_instruction)
 178     */
 179    exec_list instructions;
 180
 181    cfg_t *cfg;
 182
 183    gl_shader_stage stage;
 184
 185    brw::simple_allocator alloc;
 186
 187    virtual void dump_instruction(backend_instruction *inst) = 0;
 188    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 189    virtual void dump_instructions();
 190    virtual void dump_instructions(const char *name);
 191
 192    void calculate_cfg();
 193    void invalidate_cfg();
 194
 195    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 196
 197    virtual void invalidate_live_intervals() = 0;
 198 };
 199
 200 uint32_t brw_texture_offset(struct gl_context *ctx, int *offsets,
 201                             unsigned num_components);
 202
 203 #endif /* __cplusplus */
 204
 205 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 206 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 207 uint32_t brw_math_function(enum opcode op);
 208 const char *brw_instruction_name(enum opcode op);
 209 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 210 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 211 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 212
 213 #ifdef __cplusplus
 214 extern "C" {
 215 #endif
 216
 217 bool brw_vs_precompile(struct gl_context *ctx,
 218                        struct gl_shader_program *shader_prog,
 219                        struct gl_program *prog);
 220 bool brw_gs_precompile(struct gl_context *ctx,
 221                        struct gl_shader_program *shader_prog,
 222                        struct gl_program *prog);
 223 bool brw_fs_precompile(struct gl_context *ctx,
 224                        struct gl_shader_program *shader_prog,
 225                        struct gl_program *prog);
 226
 227 #ifdef __cplusplus
 228 }
 229 #endif