src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_reg.h"
  26 #include "brw_defines.h"
  27 #include "brw_context.h"
  28 #include "main/compiler.h"
  29 #include "glsl/ir.h"
  30 #include "program/prog_parameter.h"
  31
  32 #ifdef __cplusplus
  33 #include "brw_ir_allocator.h"
  34 #endif
  35
  36 #pragma once
  37
  38 #define MAX_SAMPLER_MESSAGE_SIZE 11
  39 #define MAX_VGRF_SIZE 16
  40
  41 enum PACKED register_file {
  42    BAD_FILE,
  43    GRF,
  44    MRF,
  45    IMM,
  46    HW_REG, /* a struct brw_reg */
  47    ATTR,
  48    UNIFORM, /* prog_data->params[reg] */
  49 };
  50
  51 struct backend_reg
  52 {
  53 #ifdef __cplusplus
  54    bool is_zero() const;
  55    bool is_one() const;
  56    bool is_negative_one() const;
  57    bool is_null() const;
  58    bool is_accumulator() const;
  59    bool in_range(const backend_reg &r, unsigned n) const;
  60 #endif
  61
  62    enum register_file file; /**< Register file: GRF, MRF, IMM. */
  63    enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
  64
  65    /**
  66     * Register number.
  67     *
  68     * For GRF, it's a virtual register number until register allocation.
  69     *
  70     * For MRF, it's the hardware register.
  71     */
  72    uint16_t reg;
  73
  74    /**
  75     * Offset within the virtual register.
  76     *
  77     * In the scalar backend, this is in units of a float per pixel for pre-
  78     * register allocation registers (i.e., one register in SIMD8 mode and two
  79     * registers in SIMD16 mode).
  80     *
  81     * For uniforms, this is in units of 1 float.
  82     */
  83    uint16_t reg_offset;
  84
  85    struct brw_reg fixed_hw_reg;
  86
  87    bool negate;
  88    bool abs;
  89 };
  90
  91 struct cfg_t;
  92 struct bblock_t;
  93
  94 #ifdef __cplusplus
  95 struct backend_instruction : public exec_node {
  96    bool is_3src() const;
  97    bool is_tex() const;
  98    bool is_math() const;
  99    bool is_control_flow() const;
 100    bool is_commutative() const;
 101    bool can_do_source_mods() const;
 102    bool can_do_saturate() const;
 103    bool can_do_cmod() const;
 104    bool reads_accumulator_implicitly() const;
 105    bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
 106
 107    void remove(bblock_t *block);
 108    void insert_after(bblock_t *block, backend_instruction *inst);
 109    void insert_before(bblock_t *block, backend_instruction *inst);
 110    void insert_before(bblock_t *block, exec_list *list);
 111
 112    /**
 113     * True if the instruction has side effects other than writing to
 114     * its destination registers.  You are expected not to reorder or
 115     * optimize these out unless you know what you are doing.
 116     */
 117    bool has_side_effects() const;
 118
 119    /**
 120     * True if the instruction might be affected by side effects of other
 121     * instructions.
 122     */
 123    bool is_volatile() const;
 124 #else
 125 struct backend_instruction {
 126    struct exec_node link;
 127 #endif
 128    /** @{
 129     * Annotation for the generated IR.  One of the two can be set.
 130     */
 131    const void *ir;
 132    const char *annotation;
 133    /** @} */
 134
 135    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 136    uint8_t mlen; /**< SEND message length */
 137    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 138    uint8_t target; /**< MRT target. */
 139    uint8_t regs_written; /**< Number of registers written by the instruction. */
 140
 141    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 142    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 143    enum brw_predicate predicate;
 144    bool predicate_inverse:1;
 145    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 146    bool force_writemask_all:1;
 147    bool no_dd_clear:1;
 148    bool no_dd_check:1;
 149    bool saturate:1;
 150    bool shadow_compare:1;
 151
 152    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 153     * mod and predication.
 154     */
 155    unsigned flag_subreg:1;
 156
 157    /** The number of hardware registers used for a message header. */
 158    uint8_t header_size;
 159 };
 160
 161 #ifdef __cplusplus
 162
 163 enum instruction_scheduler_mode {
 164    SCHEDULE_PRE,
 165    SCHEDULE_PRE_NON_LIFO,
 166    SCHEDULE_PRE_LIFO,
 167    SCHEDULE_POST,
 168 };
 169
 170 struct backend_shader {
 171 protected:
 172
 173    backend_shader(const struct brw_compiler *compiler,
 174                   void *log_data,
 175                   void *mem_ctx,
 176                   const nir_shader *shader,
 177                   struct brw_stage_prog_data *stage_prog_data);
 178
 179 public:
 180
 181    const struct brw_compiler *compiler;
 182    void *log_data; /* Passed to compiler->*_log functions */
 183
 184    const struct brw_device_info * const devinfo;
 185    const nir_shader *nir;
 186    struct brw_stage_prog_data * const stage_prog_data;
 187
 188    /** ralloc context for temporary data used during compile */
 189    void *mem_ctx;
 190
 191    /**
 192     * List of either fs_inst or vec4_instruction (inheriting from
 193     * backend_instruction)
 194     */
 195    exec_list instructions;
 196
 197    cfg_t *cfg;
 198
 199    gl_shader_stage stage;
 200    bool debug_enabled;
 201    const char *stage_name;
 202    const char *stage_abbrev;
 203
 204    brw::simple_allocator alloc;
 205
 206    virtual void dump_instruction(backend_instruction *inst) = 0;
 207    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 208    virtual void dump_instructions();
 209    virtual void dump_instructions(const char *name);
 210
 211    void calculate_cfg();
 212    void invalidate_cfg();
 213
 214    virtual void invalidate_live_intervals() = 0;
 215 };
 216
 217 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
 218
 219 void brw_setup_image_uniform_values(gl_shader_stage stage,
 220                                     struct brw_stage_prog_data *stage_prog_data,
 221                                     unsigned param_start_index,
 222                                     const gl_uniform_storage *storage);
 223
 224 #else
 225 struct backend_shader;
 226 #endif /* __cplusplus */
 227
 228 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 229 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 230 uint32_t brw_math_function(enum opcode op);
 231 const char *brw_instruction_name(enum opcode op);
 232 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 233 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 234 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 235
 236 bool opt_predicated_break(struct backend_shader *s);
 237
 238 #ifdef __cplusplus
 239 extern "C" {
 240 #endif
 241
 242 /**
 243  * Scratch data used when compiling a GLSL geometry shader.
 244  */
 245 struct brw_gs_compile
 246 {
 247    struct brw_gs_prog_key key;
 248    struct brw_vue_map input_vue_map;
 249
 250    unsigned control_data_bits_per_vertex;
 251    unsigned control_data_header_size_bits;
 252 };
 253
 254 struct brw_compiler *
 255 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
 256
 257 void
 258 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
 259                                         const struct brw_device_info *devinfo,
 260                                         const struct gl_shader_program *shader_prog,
 261                                         const struct gl_program *prog,
 262                                         struct brw_stage_prog_data *stage_prog_data,
 263                                         uint32_t next_binding_table_offset);
 264
 265 bool brw_vs_precompile(struct gl_context *ctx,
 266                        struct gl_shader_program *shader_prog,
 267                        struct gl_program *prog);
 268 bool brw_gs_precompile(struct gl_context *ctx,
 269                        struct gl_shader_program *shader_prog,
 270                        struct gl_program *prog);
 271 bool brw_fs_precompile(struct gl_context *ctx,
 272                        struct gl_shader_program *shader_prog,
 273                        struct gl_program *prog);
 274 bool brw_cs_precompile(struct gl_context *ctx,
 275                        struct gl_shader_program *shader_prog,
 276                        struct gl_program *prog);
 277
 278 int type_size_scalar(const struct glsl_type *type);
 279 int type_size_vec4(const struct glsl_type *type);
 280 int type_size_vec4_times_4(const struct glsl_type *type);
 281
 282 bool is_scalar_shader_stage(const struct brw_compiler *compiler, int stage);
 283
 284 #ifdef __cplusplus
 285 }
 286 #endif