2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_defines.h"
27 #include "main/compiler.h"
32 enum PACKED register_file
{
37 HW_REG
, /* a struct brw_reg */
39 UNIFORM
, /* prog_data->params[reg] */
48 bool is_accumulator() const;
51 enum register_file file
; /**< Register file: GRF, MRF, IMM. */
52 enum brw_reg_type type
; /**< Register type: BRW_REGISTER_TYPE_* */
57 * For GRF, it's a virtual register number until register allocation.
59 * For MRF, it's the hardware register.
64 * Offset within the virtual register.
66 * In the scalar backend, this is in units of a float per pixel for pre-
67 * register allocation registers (i.e., one register in SIMD8 mode and two
68 * registers in SIMD16 mode).
70 * For uniforms, this is in units of 1 float.
74 struct brw_reg fixed_hw_reg
;
84 struct backend_instruction
: public exec_node
{
88 bool is_control_flow() const;
89 bool can_do_source_mods() const;
90 bool can_do_saturate() const;
91 bool can_do_cmod() const;
92 bool reads_accumulator_implicitly() const;
93 bool writes_accumulator_implicitly(struct brw_context
*brw
) const;
95 void remove(bblock_t
*block
);
96 void insert_after(bblock_t
*block
, backend_instruction
*inst
);
97 void insert_before(bblock_t
*block
, backend_instruction
*inst
);
98 void insert_before(bblock_t
*block
, exec_list
*list
);
101 * True if the instruction has side effects other than writing to
102 * its destination registers. You are expected not to reorder or
103 * optimize these out unless you know what you are doing.
105 bool has_side_effects() const;
107 struct backend_instruction
{
108 struct exec_node link
;
111 * Annotation for the generated IR. One of the two can be set.
114 const char *annotation
;
117 uint32_t offset
; /**< spill/unspill offset or texture offset bitfield */
118 uint8_t mlen
; /**< SEND message length */
119 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
120 uint8_t target
; /**< MRT target. */
122 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
123 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
124 enum brw_predicate predicate
;
125 bool predicate_inverse
:1;
126 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
127 bool force_writemask_all
:1;
131 bool shadow_compare
:1;
132 bool header_present
:1;
137 enum instruction_scheduler_mode
{
139 SCHEDULE_PRE_NON_LIFO
,
144 class backend_visitor
: public ir_visitor
{
147 backend_visitor(struct brw_context
*brw
,
148 struct gl_shader_program
*shader_prog
,
149 struct gl_program
*prog
,
150 struct brw_stage_prog_data
*stage_prog_data
,
151 gl_shader_stage stage
);
155 struct brw_context
* const brw
;
156 struct gl_context
* const ctx
;
157 struct brw_shader
* const shader
;
158 struct gl_shader_program
* const shader_prog
;
159 struct gl_program
* const prog
;
160 struct brw_stage_prog_data
* const stage_prog_data
;
162 /** ralloc context for temporary data used during compile */
166 * List of either fs_inst or vec4_instruction (inheriting from
167 * backend_instruction)
169 exec_list instructions
;
173 gl_shader_stage stage
;
175 virtual void dump_instruction(backend_instruction
*inst
) = 0;
176 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
177 virtual void dump_instructions();
178 virtual void dump_instructions(const char *name
);
180 void calculate_cfg();
181 void invalidate_cfg();
183 void assign_common_binding_table_offsets(uint32_t next_binding_table_offset
);
185 virtual void invalidate_live_intervals() = 0;
188 uint32_t brw_texture_offset(struct gl_context
*ctx
, int *offsets
,
189 unsigned num_components
);
191 #endif /* __cplusplus */
193 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
194 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
195 uint32_t brw_math_function(enum opcode op
);
196 const char *brw_instruction_name(enum opcode op
);
197 bool brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
198 bool brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
204 bool brw_vs_precompile(struct gl_context
*ctx
,
205 struct gl_shader_program
*shader_prog
,
206 struct gl_program
*prog
);
207 bool brw_gs_precompile(struct gl_context
*ctx
,
208 struct gl_shader_program
*shader_prog
,
209 struct gl_program
*prog
);
210 bool brw_fs_precompile(struct gl_context
*ctx
,
211 struct gl_shader_program
*shader_prog
,
212 struct gl_program
*prog
);