i965: add brw_imm_df
[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #pragma once
25
26 #include <stdint.h>
27 #include "brw_reg.h"
28 #include "brw_defines.h"
29 #include "brw_context.h"
30
31 #ifdef __cplusplus
32 #include "brw_ir_allocator.h"
33 #endif
34
35 #define MAX_SAMPLER_MESSAGE_SIZE 11
36 #define MAX_VGRF_SIZE 16
37
38 #ifdef __cplusplus
39 struct backend_reg : private brw_reg
40 {
41 backend_reg() {}
42 backend_reg(const struct brw_reg &reg) : brw_reg(reg) {}
43
44 const brw_reg &as_brw_reg() const
45 {
46 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
47 assert(reg_offset == 0);
48 return static_cast<const brw_reg &>(*this);
49 }
50
51 brw_reg &as_brw_reg()
52 {
53 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
54 assert(reg_offset == 0);
55 return static_cast<brw_reg &>(*this);
56 }
57
58 bool equals(const backend_reg &r) const;
59
60 bool is_zero() const;
61 bool is_one() const;
62 bool is_negative_one() const;
63 bool is_null() const;
64 bool is_accumulator() const;
65 bool in_range(const backend_reg &r, unsigned n) const;
66
67 /**
68 * Offset within the virtual register.
69 *
70 * In the scalar backend, this is in units of a float per pixel for pre-
71 * register allocation registers (i.e., one register in SIMD8 mode and two
72 * registers in SIMD16 mode).
73 *
74 * For uniforms, this is in units of 1 float.
75 */
76 uint16_t reg_offset;
77
78 using brw_reg::type;
79 using brw_reg::file;
80 using brw_reg::negate;
81 using brw_reg::abs;
82 using brw_reg::address_mode;
83 using brw_reg::subnr;
84 using brw_reg::nr;
85
86 using brw_reg::swizzle;
87 using brw_reg::writemask;
88 using brw_reg::indirect_offset;
89 using brw_reg::vstride;
90 using brw_reg::width;
91 using brw_reg::hstride;
92
93 using brw_reg::df;
94 using brw_reg::f;
95 using brw_reg::d;
96 using brw_reg::ud;
97 };
98 #endif
99
100 struct cfg_t;
101 struct bblock_t;
102
103 #ifdef __cplusplus
104 struct backend_instruction : public exec_node {
105 bool is_3src(const struct brw_device_info *devinfo) const;
106 bool is_tex() const;
107 bool is_math() const;
108 bool is_control_flow() const;
109 bool is_commutative() const;
110 bool can_do_source_mods() const;
111 bool can_do_saturate() const;
112 bool can_do_cmod() const;
113 bool reads_accumulator_implicitly() const;
114 bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
115
116 void remove(bblock_t *block);
117 void insert_after(bblock_t *block, backend_instruction *inst);
118 void insert_before(bblock_t *block, backend_instruction *inst);
119 void insert_before(bblock_t *block, exec_list *list);
120
121 /**
122 * True if the instruction has side effects other than writing to
123 * its destination registers. You are expected not to reorder or
124 * optimize these out unless you know what you are doing.
125 */
126 bool has_side_effects() const;
127
128 /**
129 * True if the instruction might be affected by side effects of other
130 * instructions.
131 */
132 bool is_volatile() const;
133 #else
134 struct backend_instruction {
135 struct exec_node link;
136 #endif
137 /** @{
138 * Annotation for the generated IR. One of the two can be set.
139 */
140 const void *ir;
141 const char *annotation;
142 /** @} */
143
144 uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
145 uint8_t mlen; /**< SEND message length */
146 int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
147 uint8_t target; /**< MRT target. */
148 uint8_t regs_written; /**< Number of registers written by the instruction. */
149
150 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
151 enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
152 enum brw_predicate predicate;
153 bool predicate_inverse:1;
154 bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
155 bool force_writemask_all:1;
156 bool no_dd_clear:1;
157 bool no_dd_check:1;
158 bool saturate:1;
159 bool shadow_compare:1;
160
161 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
162 * mod and predication.
163 */
164 unsigned flag_subreg:1;
165
166 /** The number of hardware registers used for a message header. */
167 uint8_t header_size;
168 };
169
170 #ifdef __cplusplus
171
172 enum instruction_scheduler_mode {
173 SCHEDULE_PRE,
174 SCHEDULE_PRE_NON_LIFO,
175 SCHEDULE_PRE_LIFO,
176 SCHEDULE_POST,
177 };
178
179 struct backend_shader {
180 protected:
181
182 backend_shader(const struct brw_compiler *compiler,
183 void *log_data,
184 void *mem_ctx,
185 const nir_shader *shader,
186 struct brw_stage_prog_data *stage_prog_data);
187
188 public:
189
190 const struct brw_compiler *compiler;
191 void *log_data; /* Passed to compiler->*_log functions */
192
193 const struct brw_device_info * const devinfo;
194 const nir_shader *nir;
195 struct brw_stage_prog_data * const stage_prog_data;
196
197 /** ralloc context for temporary data used during compile */
198 void *mem_ctx;
199
200 /**
201 * List of either fs_inst or vec4_instruction (inheriting from
202 * backend_instruction)
203 */
204 exec_list instructions;
205
206 cfg_t *cfg;
207
208 gl_shader_stage stage;
209 bool debug_enabled;
210 const char *stage_name;
211 const char *stage_abbrev;
212 bool is_passthrough_shader;
213
214 brw::simple_allocator alloc;
215
216 virtual void dump_instruction(backend_instruction *inst) = 0;
217 virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
218 virtual void dump_instructions();
219 virtual void dump_instructions(const char *name);
220
221 void calculate_cfg();
222
223 virtual void invalidate_live_intervals() = 0;
224 };
225
226 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
227
228 void brw_setup_image_uniform_values(gl_shader_stage stage,
229 struct brw_stage_prog_data *stage_prog_data,
230 unsigned param_start_index,
231 const gl_uniform_storage *storage);
232
233 #else
234 struct backend_shader;
235 #endif /* __cplusplus */
236
237 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
238 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
239 uint32_t brw_math_function(enum opcode op);
240 const char *brw_instruction_name(const struct brw_device_info *devinfo,
241 enum opcode op);
242 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
243 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
244 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
245
246 bool opt_predicated_break(struct backend_shader *s);
247
248 #ifdef __cplusplus
249 extern "C" {
250 #endif
251
252 /**
253 * Scratch data used when compiling a GLSL geometry shader.
254 */
255 struct brw_gs_compile
256 {
257 struct brw_gs_prog_key key;
258 struct brw_vue_map input_vue_map;
259
260 unsigned control_data_bits_per_vertex;
261 unsigned control_data_header_size_bits;
262 };
263
264 void
265 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
266 const struct brw_device_info *devinfo,
267 const struct gl_shader_program *shader_prog,
268 const struct gl_program *prog,
269 struct brw_stage_prog_data *stage_prog_data,
270 uint32_t next_binding_table_offset);
271
272 bool brw_vs_precompile(struct gl_context *ctx,
273 struct gl_shader_program *shader_prog,
274 struct gl_program *prog);
275 bool brw_tcs_precompile(struct gl_context *ctx,
276 struct gl_shader_program *shader_prog,
277 struct gl_program *prog);
278 bool brw_tes_precompile(struct gl_context *ctx,
279 struct gl_shader_program *shader_prog,
280 struct gl_program *prog);
281 bool brw_gs_precompile(struct gl_context *ctx,
282 struct gl_shader_program *shader_prog,
283 struct gl_program *prog);
284 bool brw_fs_precompile(struct gl_context *ctx,
285 struct gl_shader_program *shader_prog,
286 struct gl_program *prog);
287 bool brw_cs_precompile(struct gl_context *ctx,
288 struct gl_shader_program *shader_prog,
289 struct gl_program *prog);
290
291 GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog);
292 struct gl_shader *brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type);
293
294 int type_size_scalar(const struct glsl_type *type);
295 int type_size_vec4(const struct glsl_type *type);
296 int type_size_vec4_times_4(const struct glsl_type *type);
297
298 unsigned tesslevel_outer_components(GLenum tes_primitive_mode);
299 unsigned tesslevel_inner_components(GLenum tes_primitive_mode);
300 unsigned writemask_for_backwards_vector(unsigned mask);
301
302 #ifdef __cplusplus
303 }
304 #endif