src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_reg.h"
  26 #include "brw_defines.h"
  27 #include "main/compiler.h"
  28 #include "glsl/ir.h"
  29 #include "intel_asm_printer.h"
  30
  31 #pragma once
  32
  33 enum PACKED register_file {
  34    BAD_FILE,
  35    GRF,
  36    MRF,
  37    IMM,
  38    HW_REG, /* a struct brw_reg */
  39    ATTR,
  40    UNIFORM, /* prog_data->params[reg] */
  41 };
  42
  43 struct backend_reg
  44 {
  45 #ifdef __cplusplus
  46    bool is_zero() const;
  47    bool is_one() const;
  48    bool is_null() const;
  49    bool is_accumulator() const;
  50 #endif
  51
  52    enum register_file file; /**< Register file: GRF, MRF, IMM. */
  53    enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
  54
  55    /**
  56     * Register number.
  57     *
  58     * For GRF, it's a virtual register number until register allocation.
  59     *
  60     * For MRF, it's the hardware register.
  61     */
  62    uint16_t reg;
  63
  64    /**
  65     * Offset within the virtual register.
  66     *
  67     * In the scalar backend, this is in units of a float per pixel for pre-
  68     * register allocation registers (i.e., one register in SIMD8 mode and two
  69     * registers in SIMD16 mode).
  70     *
  71     * For uniforms, this is in units of 1 float.
  72     */
  73    int reg_offset;
  74
  75    struct brw_reg fixed_hw_reg;
  76
  77    bool negate;
  78    bool abs;
  79 };
  80
  81 #ifdef __cplusplus
  82
  83 class cfg_t;
  84
  85 struct backend_instruction : public exec_node {
  86 public:
  87    bool is_tex() const;
  88    bool is_math() const;
  89    bool is_control_flow() const;
  90    bool can_do_source_mods() const;
  91    bool can_do_saturate() const;
  92    bool reads_accumulator_implicitly() const;
  93    bool writes_accumulator_implicitly(struct brw_context *brw) const;
  94
  95    /**
  96     * True if the instruction has side effects other than writing to
  97     * its destination registers.  You are expected not to reorder or
  98     * optimize these out unless you know what you are doing.
  99     */
 100    bool has_side_effects() const;
 101
 102    /** @{
 103     * Annotation for the generated IR.  One of the two can be set.
 104     */
 105    const void *ir;
 106    const char *annotation;
 107    /** @} */
 108
 109    uint32_t texture_offset; /**< Texture offset bitfield */
 110    uint32_t offset; /**< spill/unspill offset */
 111    uint8_t sampler;
 112    uint8_t mlen; /**< SEND message length */
 113    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 114    uint8_t target; /**< MRT target. */
 115
 116    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 117    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 118    enum brw_predicate predicate;
 119    bool predicate_inverse:1;
 120    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 121    bool force_writemask_all:1;
 122    bool no_dd_clear:1;
 123    bool no_dd_check:1;
 124    bool saturate:1;
 125 };
 126
 127 enum instruction_scheduler_mode {
 128    SCHEDULE_PRE,
 129    SCHEDULE_PRE_NON_LIFO,
 130    SCHEDULE_PRE_LIFO,
 131    SCHEDULE_POST,
 132 };
 133
 134 class backend_visitor : public ir_visitor {
 135 protected:
 136
 137    backend_visitor(struct brw_context *brw,
 138                    struct gl_shader_program *shader_prog,
 139                    struct gl_program *prog,
 140                    struct brw_stage_prog_data *stage_prog_data,
 141                    gl_shader_stage stage);
 142
 143 public:
 144
 145    struct brw_context * const brw;
 146    struct gl_context * const ctx;
 147    struct brw_shader * const shader;
 148    struct gl_shader_program * const shader_prog;
 149    struct gl_program * const prog;
 150    struct brw_stage_prog_data * const stage_prog_data;
 151
 152    /** ralloc context for temporary data used during compile */
 153    void *mem_ctx;
 154
 155    /**
 156     * List of either fs_inst or vec4_instruction (inheriting from
 157     * backend_instruction)
 158     */
 159    exec_list instructions;
 160
 161    virtual void dump_instruction(backend_instruction *inst) = 0;
 162    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 163    virtual void dump_instructions();
 164    virtual void dump_instructions(const char *name);
 165
 166    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 167
 168    virtual void invalidate_live_intervals() = 0;
 169 };
 170
 171 uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
 172
 173 void annotate(struct brw_context *brw,
 174               struct annotation_info *annotation, cfg_t *cfg,
 175               backend_instruction *inst, unsigned offset);
 176 void annotation_finalize(struct annotation_info *annotation, unsigned offset);
 177
 178 #endif /* __cplusplus */
 179
 180 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 181 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 182 uint32_t brw_math_function(enum opcode op);
 183 const char *brw_instruction_name(enum opcode op);