src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_reg.h"
  26 #include "brw_defines.h"
  27 #include "main/compiler.h"
  28 #include "glsl/ir.h"
  29
  30 #ifdef __cplusplus
  31 #include "brw_ir_allocator.h"
  32 #endif
  33
  34 #pragma once
  35
  36 #define MAX_SAMPLER_MESSAGE_SIZE 11
  37 #define MAX_VGRF_SIZE 16
  38
  39 enum PACKED register_file {
  40    BAD_FILE,
  41    GRF,
  42    MRF,
  43    IMM,
  44    HW_REG, /* a struct brw_reg */
  45    ATTR,
  46    UNIFORM, /* prog_data->params[reg] */
  47 };
  48
  49 struct backend_reg
  50 {
  51 #ifdef __cplusplus
  52    bool is_zero() const;
  53    bool is_one() const;
  54    bool is_negative_one() const;
  55    bool is_null() const;
  56    bool is_accumulator() const;
  57 #endif
  58
  59    enum register_file file; /**< Register file: GRF, MRF, IMM. */
  60    enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
  61
  62    /**
  63     * Register number.
  64     *
  65     * For GRF, it's a virtual register number until register allocation.
  66     *
  67     * For MRF, it's the hardware register.
  68     */
  69    uint16_t reg;
  70
  71    /**
  72     * Offset within the virtual register.
  73     *
  74     * In the scalar backend, this is in units of a float per pixel for pre-
  75     * register allocation registers (i.e., one register in SIMD8 mode and two
  76     * registers in SIMD16 mode).
  77     *
  78     * For uniforms, this is in units of 1 float.
  79     */
  80    int reg_offset;
  81
  82    struct brw_reg fixed_hw_reg;
  83
  84    bool negate;
  85    bool abs;
  86 };
  87
  88 struct cfg_t;
  89 struct bblock_t;
  90
  91 #ifdef __cplusplus
  92 struct backend_instruction : public exec_node {
  93    bool is_3src() const;
  94    bool is_tex() const;
  95    bool is_math() const;
  96    bool is_control_flow() const;
  97    bool can_do_source_mods() const;
  98    bool can_do_saturate() const;
  99    bool can_do_cmod() const;
 100    bool reads_accumulator_implicitly() const;
 101    bool writes_accumulator_implicitly(struct brw_context *brw) const;
 102
 103    void remove(bblock_t *block);
 104    void insert_after(bblock_t *block, backend_instruction *inst);
 105    void insert_before(bblock_t *block, backend_instruction *inst);
 106    void insert_before(bblock_t *block, exec_list *list);
 107
 108    /**
 109     * True if the instruction has side effects other than writing to
 110     * its destination registers.  You are expected not to reorder or
 111     * optimize these out unless you know what you are doing.
 112     */
 113    bool has_side_effects() const;
 114 #else
 115 struct backend_instruction {
 116    struct exec_node link;
 117 #endif
 118    /** @{
 119     * Annotation for the generated IR.  One of the two can be set.
 120     */
 121    const void *ir;
 122    const char *annotation;
 123    /** @} */
 124
 125    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 126    uint8_t mlen; /**< SEND message length */
 127    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 128    uint8_t target; /**< MRT target. */
 129    uint8_t regs_written; /**< Number of registers written by the instruction. */
 130
 131    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 132    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 133    enum brw_predicate predicate;
 134    bool predicate_inverse:1;
 135    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 136    bool force_writemask_all:1;
 137    bool no_dd_clear:1;
 138    bool no_dd_check:1;
 139    bool saturate:1;
 140    bool shadow_compare:1;
 141    bool header_present:1;
 142
 143    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 144     * mod and predication.
 145     */
 146    unsigned flag_subreg:1;
 147 };
 148
 149 #ifdef __cplusplus
 150
 151 enum instruction_scheduler_mode {
 152    SCHEDULE_PRE,
 153    SCHEDULE_PRE_NON_LIFO,
 154    SCHEDULE_PRE_LIFO,
 155    SCHEDULE_POST,
 156 };
 157
 158 class backend_visitor : public ir_visitor {
 159 protected:
 160
 161    backend_visitor(struct brw_context *brw,
 162                    struct gl_shader_program *shader_prog,
 163                    struct gl_program *prog,
 164                    struct brw_stage_prog_data *stage_prog_data,
 165                    gl_shader_stage stage);
 166
 167 public:
 168
 169    struct brw_context * const brw;
 170    struct gl_context * const ctx;
 171    struct brw_shader * const shader;
 172    struct gl_shader_program * const shader_prog;
 173    struct gl_program * const prog;
 174    struct brw_stage_prog_data * const stage_prog_data;
 175
 176    /** ralloc context for temporary data used during compile */
 177    void *mem_ctx;
 178
 179    /**
 180     * List of either fs_inst or vec4_instruction (inheriting from
 181     * backend_instruction)
 182     */
 183    exec_list instructions;
 184
 185    cfg_t *cfg;
 186
 187    gl_shader_stage stage;
 188
 189    brw::simple_allocator alloc;
 190
 191    virtual void dump_instruction(backend_instruction *inst) = 0;
 192    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 193    virtual void dump_instructions();
 194    virtual void dump_instructions(const char *name);
 195
 196    void calculate_cfg();
 197    void invalidate_cfg();
 198
 199    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 200
 201    virtual void invalidate_live_intervals() = 0;
 202 };
 203
 204 uint32_t brw_texture_offset(struct gl_context *ctx, int *offsets,
 205                             unsigned num_components);
 206
 207 #endif /* __cplusplus */
 208
 209 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 210 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 211 uint32_t brw_math_function(enum opcode op);
 212 const char *brw_instruction_name(enum opcode op);
 213 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 214 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 215 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 216
 217 #ifdef __cplusplus
 218 extern "C" {
 219 #endif
 220
 221 bool brw_vs_precompile(struct gl_context *ctx,
 222                        struct gl_shader_program *shader_prog,
 223                        struct gl_program *prog);
 224 bool brw_gs_precompile(struct gl_context *ctx,
 225                        struct gl_shader_program *shader_prog,
 226                        struct gl_program *prog);
 227 bool brw_fs_precompile(struct gl_context *ctx,
 228                        struct gl_shader_program *shader_prog,
 229                        struct gl_program *prog);
 230
 231 #ifdef __cplusplus
 232 }
 233 #endif