src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_reg.h"
  26 #include "brw_defines.h"
  27 #include "main/compiler.h"
  28 #include "glsl/ir.h"
  29
  30 #ifdef __cplusplus
  31 #include "brw_ir_allocator.h"
  32 #endif
  33
  34 #pragma once
  35
  36 #define MAX_SAMPLER_MESSAGE_SIZE 11
  37 #define MAX_VGRF_SIZE 16
  38
  39 struct brw_compiler {
  40    const struct brw_device_info *devinfo;
  41
  42    struct {
  43       struct ra_regs *regs;
  44
  45       /**
  46        * Array of the ra classes for the unaligned contiguous register
  47        * block sizes used.
  48        */
  49       int *classes;
  50
  51       /**
  52        * Mapping for register-allocated objects in *regs to the first
  53        * GRF for that object.
  54        */
  55       uint8_t *ra_reg_to_grf;
  56    } vec4_reg_set;
  57
  58    struct {
  59       struct ra_regs *regs;
  60
  61       /**
  62        * Array of the ra classes for the unaligned contiguous register
  63        * block sizes used, indexed by register size.
  64        */
  65       int classes[16];
  66
  67       /**
  68        * Mapping from classes to ra_reg ranges.  Each of the per-size
  69        * classes corresponds to a range of ra_reg nodes.  This array stores
  70        * those ranges in the form of first ra_reg in each class and the
  71        * total number of ra_reg elements in the last array element.  This
  72        * way the range of the i'th class is given by:
  73        * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
  74        */
  75       int class_to_ra_reg_range[17];
  76
  77       /**
  78        * Mapping for register-allocated objects in *regs to the first
  79        * GRF for that object.
  80        */
  81       uint8_t *ra_reg_to_grf;
  82
  83       /**
  84        * ra class for the aligned pairs we use for PLN, which doesn't
  85        * appear in *classes.
  86        */
  87       int aligned_pairs_class;
  88    } fs_reg_sets[2];
  89
  90    void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  91    void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  92
  93    bool scalar_vs;
  94    struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
  95 };
  96
  97 enum PACKED register_file {
  98    BAD_FILE,
  99    GRF,
 100    MRF,
 101    IMM,
 102    HW_REG, /* a struct brw_reg */
 103    ATTR,
 104    UNIFORM, /* prog_data->params[reg] */
 105 };
 106
 107 struct backend_reg
 108 {
 109 #ifdef __cplusplus
 110    bool is_zero() const;
 111    bool is_one() const;
 112    bool is_negative_one() const;
 113    bool is_null() const;
 114    bool is_accumulator() const;
 115    bool in_range(const backend_reg &r, unsigned n) const;
 116 #endif
 117
 118    enum register_file file; /**< Register file: GRF, MRF, IMM. */
 119    enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
 120
 121    /**
 122     * Register number.
 123     *
 124     * For GRF, it's a virtual register number until register allocation.
 125     *
 126     * For MRF, it's the hardware register.
 127     */
 128    uint16_t reg;
 129
 130    /**
 131     * Offset within the virtual register.
 132     *
 133     * In the scalar backend, this is in units of a float per pixel for pre-
 134     * register allocation registers (i.e., one register in SIMD8 mode and two
 135     * registers in SIMD16 mode).
 136     *
 137     * For uniforms, this is in units of 1 float.
 138     */
 139    uint16_t reg_offset;
 140
 141    struct brw_reg fixed_hw_reg;
 142
 143    bool negate;
 144    bool abs;
 145 };
 146
 147 struct cfg_t;
 148 struct bblock_t;
 149
 150 #ifdef __cplusplus
 151 struct backend_instruction : public exec_node {
 152    bool is_3src() const;
 153    bool is_tex() const;
 154    bool is_math() const;
 155    bool is_control_flow() const;
 156    bool is_commutative() const;
 157    bool can_do_source_mods() const;
 158    bool can_do_saturate() const;
 159    bool can_do_cmod() const;
 160    bool reads_accumulator_implicitly() const;
 161    bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
 162
 163    void remove(bblock_t *block);
 164    void insert_after(bblock_t *block, backend_instruction *inst);
 165    void insert_before(bblock_t *block, backend_instruction *inst);
 166    void insert_before(bblock_t *block, exec_list *list);
 167
 168    /**
 169     * True if the instruction has side effects other than writing to
 170     * its destination registers.  You are expected not to reorder or
 171     * optimize these out unless you know what you are doing.
 172     */
 173    bool has_side_effects() const;
 174 #else
 175 struct backend_instruction {
 176    struct exec_node link;
 177 #endif
 178    /** @{
 179     * Annotation for the generated IR.  One of the two can be set.
 180     */
 181    const void *ir;
 182    const char *annotation;
 183    /** @} */
 184
 185    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 186    uint8_t mlen; /**< SEND message length */
 187    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 188    uint8_t target; /**< MRT target. */
 189    uint8_t regs_written; /**< Number of registers written by the instruction. */
 190
 191    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 192    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 193    enum brw_predicate predicate;
 194    bool predicate_inverse:1;
 195    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 196    bool force_writemask_all:1;
 197    bool no_dd_clear:1;
 198    bool no_dd_check:1;
 199    bool saturate:1;
 200    bool shadow_compare:1;
 201
 202    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 203     * mod and predication.
 204     */
 205    unsigned flag_subreg:1;
 206
 207    /** The number of hardware registers used for a message header. */
 208    uint8_t header_size;
 209 };
 210
 211 #ifdef __cplusplus
 212
 213 enum instruction_scheduler_mode {
 214    SCHEDULE_PRE,
 215    SCHEDULE_PRE_NON_LIFO,
 216    SCHEDULE_PRE_LIFO,
 217    SCHEDULE_POST,
 218 };
 219
 220 class backend_shader {
 221 protected:
 222
 223    backend_shader(const struct brw_compiler *compiler,
 224                   void *log_data,
 225                   void *mem_ctx,
 226                   struct gl_shader_program *shader_prog,
 227                   struct gl_program *prog,
 228                   struct brw_stage_prog_data *stage_prog_data,
 229                   gl_shader_stage stage);
 230
 231 public:
 232
 233    const struct brw_compiler *compiler;
 234    void *log_data; /* Passed to compiler->*_log functions */
 235
 236    const struct brw_device_info * const devinfo;
 237    struct brw_shader * const shader;
 238    struct gl_shader_program * const shader_prog;
 239    struct gl_program * const prog;
 240    struct brw_stage_prog_data * const stage_prog_data;
 241
 242    /** ralloc context for temporary data used during compile */
 243    void *mem_ctx;
 244
 245    /**
 246     * List of either fs_inst or vec4_instruction (inheriting from
 247     * backend_instruction)
 248     */
 249    exec_list instructions;
 250
 251    cfg_t *cfg;
 252
 253    gl_shader_stage stage;
 254    bool debug_enabled;
 255    const char *stage_name;
 256    const char *stage_abbrev;
 257
 258    brw::simple_allocator alloc;
 259
 260    virtual void dump_instruction(backend_instruction *inst) = 0;
 261    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 262    virtual void dump_instructions();
 263    virtual void dump_instructions(const char *name);
 264
 265    void calculate_cfg();
 266    void invalidate_cfg();
 267
 268    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 269
 270    virtual void invalidate_live_intervals() = 0;
 271 };
 272
 273 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
 274
 275 #endif /* __cplusplus */
 276
 277 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 278 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 279 uint32_t brw_math_function(enum opcode op);
 280 const char *brw_instruction_name(enum opcode op);
 281 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 282 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 283 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 284
 285 #ifdef __cplusplus
 286 extern "C" {
 287 #endif
 288
 289 struct brw_compiler *
 290 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
 291
 292 bool brw_vs_precompile(struct gl_context *ctx,
 293                        struct gl_shader_program *shader_prog,
 294                        struct gl_program *prog);
 295 bool brw_gs_precompile(struct gl_context *ctx,
 296                        struct gl_shader_program *shader_prog,
 297                        struct gl_program *prog);
 298 bool brw_fs_precompile(struct gl_context *ctx,
 299                        struct gl_shader_program *shader_prog,
 300                        struct gl_program *prog);
 301 bool brw_cs_precompile(struct gl_context *ctx,
 302                        struct gl_shader_program *shader_prog,
 303                        struct gl_program *prog);
 304
 305 #ifdef __cplusplus
 306 }
 307 #endif