i965: Enable EGL_KHR_gl_texture_3D_image
[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #pragma once
25
26 #include <stdint.h>
27 #include "brw_reg.h"
28 #include "brw_defines.h"
29 #include "brw_context.h"
30
31 #ifdef __cplusplus
32 #include "brw_ir_allocator.h"
33 #endif
34
35 #define MAX_SAMPLER_MESSAGE_SIZE 11
36 #define MAX_VGRF_SIZE 16
37
38 #ifdef __cplusplus
39 struct backend_reg : private brw_reg
40 {
41 backend_reg() {}
42 backend_reg(const struct brw_reg &reg) : brw_reg(reg) {}
43
44 const brw_reg &as_brw_reg() const
45 {
46 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
47 assert(offset == 0);
48 return static_cast<const brw_reg &>(*this);
49 }
50
51 brw_reg &as_brw_reg()
52 {
53 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
54 assert(offset == 0);
55 return static_cast<brw_reg &>(*this);
56 }
57
58 bool equals(const backend_reg &r) const;
59
60 bool is_zero() const;
61 bool is_one() const;
62 bool is_negative_one() const;
63 bool is_null() const;
64 bool is_accumulator() const;
65
66 /** Offset from the start of the (virtual) register in bytes. */
67 uint16_t offset;
68
69 using brw_reg::type;
70 using brw_reg::file;
71 using brw_reg::negate;
72 using brw_reg::abs;
73 using brw_reg::address_mode;
74 using brw_reg::subnr;
75 using brw_reg::nr;
76
77 using brw_reg::swizzle;
78 using brw_reg::writemask;
79 using brw_reg::indirect_offset;
80 using brw_reg::vstride;
81 using brw_reg::width;
82 using brw_reg::hstride;
83
84 using brw_reg::df;
85 using brw_reg::f;
86 using brw_reg::d;
87 using brw_reg::ud;
88 };
89 #endif
90
91 struct cfg_t;
92 struct bblock_t;
93
94 #ifdef __cplusplus
95 struct backend_instruction : public exec_node {
96 bool is_3src(const struct gen_device_info *devinfo) const;
97 bool is_tex() const;
98 bool is_math() const;
99 bool is_control_flow() const;
100 bool is_commutative() const;
101 bool can_do_source_mods() const;
102 bool can_do_saturate() const;
103 bool can_do_cmod() const;
104 bool reads_accumulator_implicitly() const;
105 bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const;
106
107 void remove(bblock_t *block);
108 void insert_after(bblock_t *block, backend_instruction *inst);
109 void insert_before(bblock_t *block, backend_instruction *inst);
110 void insert_before(bblock_t *block, exec_list *list);
111
112 /**
113 * True if the instruction has side effects other than writing to
114 * its destination registers. You are expected not to reorder or
115 * optimize these out unless you know what you are doing.
116 */
117 bool has_side_effects() const;
118
119 /**
120 * True if the instruction might be affected by side effects of other
121 * instructions.
122 */
123 bool is_volatile() const;
124 #else
125 struct backend_instruction {
126 struct exec_node link;
127 #endif
128 /** @{
129 * Annotation for the generated IR. One of the two can be set.
130 */
131 const void *ir;
132 const char *annotation;
133 /** @} */
134
135 uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
136 uint8_t mlen; /**< SEND message length */
137 int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
138 uint8_t target; /**< MRT target. */
139 unsigned size_written; /**< Data written to the destination register in bytes. */
140
141 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
142 enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
143 enum brw_predicate predicate;
144 bool predicate_inverse:1;
145 bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
146 bool force_writemask_all:1;
147 bool no_dd_clear:1;
148 bool no_dd_check:1;
149 bool saturate:1;
150 bool shadow_compare:1;
151
152 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
153 * mod and predication.
154 */
155 unsigned flag_subreg:1;
156
157 /** The number of hardware registers used for a message header. */
158 uint8_t header_size;
159 };
160
161 #ifdef __cplusplus
162
163 enum instruction_scheduler_mode {
164 SCHEDULE_PRE,
165 SCHEDULE_PRE_NON_LIFO,
166 SCHEDULE_PRE_LIFO,
167 SCHEDULE_POST,
168 };
169
170 struct backend_shader {
171 protected:
172
173 backend_shader(const struct brw_compiler *compiler,
174 void *log_data,
175 void *mem_ctx,
176 const nir_shader *shader,
177 struct brw_stage_prog_data *stage_prog_data);
178
179 public:
180
181 const struct brw_compiler *compiler;
182 void *log_data; /* Passed to compiler->*_log functions */
183
184 const struct gen_device_info * const devinfo;
185 const nir_shader *nir;
186 struct brw_stage_prog_data * const stage_prog_data;
187
188 /** ralloc context for temporary data used during compile */
189 void *mem_ctx;
190
191 /**
192 * List of either fs_inst or vec4_instruction (inheriting from
193 * backend_instruction)
194 */
195 exec_list instructions;
196
197 cfg_t *cfg;
198
199 gl_shader_stage stage;
200 bool debug_enabled;
201 const char *stage_name;
202 const char *stage_abbrev;
203 bool is_passthrough_shader;
204
205 brw::simple_allocator alloc;
206
207 virtual void dump_instruction(backend_instruction *inst) = 0;
208 virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
209 virtual void dump_instructions();
210 virtual void dump_instructions(const char *name);
211
212 void calculate_cfg();
213
214 virtual void invalidate_live_intervals() = 0;
215 };
216
217 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
218
219 void brw_setup_image_uniform_values(gl_shader_stage stage,
220 struct brw_stage_prog_data *stage_prog_data,
221 unsigned param_start_index,
222 const gl_uniform_storage *storage);
223
224 #else
225 struct backend_shader;
226 #endif /* __cplusplus */
227
228 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
229 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
230 uint32_t brw_math_function(enum opcode op);
231 const char *brw_instruction_name(const struct gen_device_info *devinfo,
232 enum opcode op);
233 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
234 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
235 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
236
237 bool opt_predicated_break(struct backend_shader *s);
238
239 #ifdef __cplusplus
240 extern "C" {
241 #endif
242
243 /**
244 * Scratch data used when compiling a GLSL geometry shader.
245 */
246 struct brw_gs_compile
247 {
248 struct brw_gs_prog_key key;
249 struct brw_vue_map input_vue_map;
250
251 unsigned control_data_bits_per_vertex;
252 unsigned control_data_header_size_bits;
253 };
254
255 uint32_t
256 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
257 const struct gen_device_info *devinfo,
258 const struct gl_shader_program *shader_prog,
259 const struct gl_program *prog,
260 struct brw_stage_prog_data *stage_prog_data,
261 uint32_t next_binding_table_offset);
262
263 bool brw_vs_precompile(struct gl_context *ctx,
264 struct gl_shader_program *shader_prog,
265 struct gl_program *prog);
266 bool brw_tcs_precompile(struct gl_context *ctx,
267 struct gl_shader_program *shader_prog,
268 struct gl_program *prog);
269 bool brw_tes_precompile(struct gl_context *ctx,
270 struct gl_shader_program *shader_prog,
271 struct gl_program *prog);
272 bool brw_gs_precompile(struct gl_context *ctx,
273 struct gl_shader_program *shader_prog,
274 struct gl_program *prog);
275 bool brw_fs_precompile(struct gl_context *ctx,
276 struct gl_shader_program *shader_prog,
277 struct gl_program *prog);
278 bool brw_cs_precompile(struct gl_context *ctx,
279 struct gl_shader_program *shader_prog,
280 struct gl_program *prog);
281
282 GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog);
283 struct gl_linked_shader *brw_new_shader(gl_shader_stage stage);
284
285 unsigned tesslevel_outer_components(GLenum tes_primitive_mode);
286 unsigned tesslevel_inner_components(GLenum tes_primitive_mode);
287 unsigned writemask_for_backwards_vector(unsigned mask);
288
289 #ifdef __cplusplus
290 }
291 #endif