src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_reg.h"
  26 #include "brw_defines.h"
  27 #include "main/compiler.h"
  28 #include "glsl/ir.h"
  29 #include "program/prog_parameter.h"
  30
  31 #ifdef __cplusplus
  32 #include "brw_ir_allocator.h"
  33 #endif
  34
  35 #pragma once
  36
  37 #define MAX_SAMPLER_MESSAGE_SIZE 11
  38 #define MAX_VGRF_SIZE 16
  39
  40 struct brw_compiler {
  41    const struct brw_device_info *devinfo;
  42
  43    struct {
  44       struct ra_regs *regs;
  45
  46       /**
  47        * Array of the ra classes for the unaligned contiguous register
  48        * block sizes used.
  49        */
  50       int *classes;
  51
  52       /**
  53        * Mapping for register-allocated objects in *regs to the first
  54        * GRF for that object.
  55        */
  56       uint8_t *ra_reg_to_grf;
  57    } vec4_reg_set;
  58
  59    struct {
  60       struct ra_regs *regs;
  61
  62       /**
  63        * Array of the ra classes for the unaligned contiguous register
  64        * block sizes used, indexed by register size.
  65        */
  66       int classes[16];
  67
  68       /**
  69        * Mapping from classes to ra_reg ranges.  Each of the per-size
  70        * classes corresponds to a range of ra_reg nodes.  This array stores
  71        * those ranges in the form of first ra_reg in each class and the
  72        * total number of ra_reg elements in the last array element.  This
  73        * way the range of the i'th class is given by:
  74        * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
  75        */
  76       int class_to_ra_reg_range[17];
  77
  78       /**
  79        * Mapping for register-allocated objects in *regs to the first
  80        * GRF for that object.
  81        */
  82       uint8_t *ra_reg_to_grf;
  83
  84       /**
  85        * ra class for the aligned pairs we use for PLN, which doesn't
  86        * appear in *classes.
  87        */
  88       int aligned_pairs_class;
  89    } fs_reg_sets[2];
  90
  91    void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  92    void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  93
  94    bool scalar_vs;
  95    struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
  96 };
  97
  98 enum PACKED register_file {
  99    BAD_FILE,
 100    GRF,
 101    MRF,
 102    IMM,
 103    HW_REG, /* a struct brw_reg */
 104    ATTR,
 105    UNIFORM, /* prog_data->params[reg] */
 106 };
 107
 108 struct backend_reg
 109 {
 110 #ifdef __cplusplus
 111    bool is_zero() const;
 112    bool is_one() const;
 113    bool is_negative_one() const;
 114    bool is_null() const;
 115    bool is_accumulator() const;
 116    bool in_range(const backend_reg &r, unsigned n) const;
 117 #endif
 118
 119    enum register_file file; /**< Register file: GRF, MRF, IMM. */
 120    enum brw_reg_type type;  /**< Register type: BRW_REGISTER_TYPE_* */
 121
 122    /**
 123     * Register number.
 124     *
 125     * For GRF, it's a virtual register number until register allocation.
 126     *
 127     * For MRF, it's the hardware register.
 128     */
 129    uint16_t reg;
 130
 131    /**
 132     * Offset within the virtual register.
 133     *
 134     * In the scalar backend, this is in units of a float per pixel for pre-
 135     * register allocation registers (i.e., one register in SIMD8 mode and two
 136     * registers in SIMD16 mode).
 137     *
 138     * For uniforms, this is in units of 1 float.
 139     */
 140    uint16_t reg_offset;
 141
 142    struct brw_reg fixed_hw_reg;
 143
 144    bool negate;
 145    bool abs;
 146 };
 147
 148 struct cfg_t;
 149 struct bblock_t;
 150
 151 #ifdef __cplusplus
 152 struct backend_instruction : public exec_node {
 153    bool is_3src() const;
 154    bool is_tex() const;
 155    bool is_math() const;
 156    bool is_control_flow() const;
 157    bool is_commutative() const;
 158    bool can_do_source_mods() const;
 159    bool can_do_saturate() const;
 160    bool can_do_cmod() const;
 161    bool reads_accumulator_implicitly() const;
 162    bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
 163
 164    void remove(bblock_t *block);
 165    void insert_after(bblock_t *block, backend_instruction *inst);
 166    void insert_before(bblock_t *block, backend_instruction *inst);
 167    void insert_before(bblock_t *block, exec_list *list);
 168
 169    /**
 170     * True if the instruction has side effects other than writing to
 171     * its destination registers.  You are expected not to reorder or
 172     * optimize these out unless you know what you are doing.
 173     */
 174    bool has_side_effects() const;
 175 #else
 176 struct backend_instruction {
 177    struct exec_node link;
 178 #endif
 179    /** @{
 180     * Annotation for the generated IR.  One of the two can be set.
 181     */
 182    const void *ir;
 183    const char *annotation;
 184    /** @} */
 185
 186    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 187    uint8_t mlen; /**< SEND message length */
 188    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 189    uint8_t target; /**< MRT target. */
 190    uint8_t regs_written; /**< Number of registers written by the instruction. */
 191
 192    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 193    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 194    enum brw_predicate predicate;
 195    bool predicate_inverse:1;
 196    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 197    bool force_writemask_all:1;
 198    bool no_dd_clear:1;
 199    bool no_dd_check:1;
 200    bool saturate:1;
 201    bool shadow_compare:1;
 202
 203    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 204     * mod and predication.
 205     */
 206    unsigned flag_subreg:1;
 207
 208    /** The number of hardware registers used for a message header. */
 209    uint8_t header_size;
 210 };
 211
 212 #ifdef __cplusplus
 213
 214 enum instruction_scheduler_mode {
 215    SCHEDULE_PRE,
 216    SCHEDULE_PRE_NON_LIFO,
 217    SCHEDULE_PRE_LIFO,
 218    SCHEDULE_POST,
 219 };
 220
 221 class backend_shader {
 222 protected:
 223
 224    backend_shader(const struct brw_compiler *compiler,
 225                   void *log_data,
 226                   void *mem_ctx,
 227                   struct gl_shader_program *shader_prog,
 228                   struct gl_program *prog,
 229                   struct brw_stage_prog_data *stage_prog_data,
 230                   gl_shader_stage stage);
 231
 232 public:
 233
 234    const struct brw_compiler *compiler;
 235    void *log_data; /* Passed to compiler->*_log functions */
 236
 237    const struct brw_device_info * const devinfo;
 238    struct brw_shader * const shader;
 239    struct gl_shader_program * const shader_prog;
 240    struct gl_program * const prog;
 241    struct brw_stage_prog_data * const stage_prog_data;
 242
 243    /** ralloc context for temporary data used during compile */
 244    void *mem_ctx;
 245
 246    /**
 247     * List of either fs_inst or vec4_instruction (inheriting from
 248     * backend_instruction)
 249     */
 250    exec_list instructions;
 251
 252    cfg_t *cfg;
 253
 254    gl_shader_stage stage;
 255    bool debug_enabled;
 256    const char *stage_name;
 257    const char *stage_abbrev;
 258
 259    brw::simple_allocator alloc;
 260
 261    virtual void dump_instruction(backend_instruction *inst) = 0;
 262    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 263    virtual void dump_instructions();
 264    virtual void dump_instructions(const char *name);
 265
 266    void calculate_cfg();
 267    void invalidate_cfg();
 268
 269    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 270
 271    virtual void invalidate_live_intervals() = 0;
 272
 273    virtual void setup_vec4_uniform_value(unsigned param_offset,
 274                                          const gl_constant_value *values,
 275                                          unsigned n) = 0;
 276    void setup_image_uniform_values(unsigned param_offset,
 277                                    const gl_uniform_storage *storage);
 278 };
 279
 280 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
 281
 282 #endif /* __cplusplus */
 283
 284 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 285 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 286 uint32_t brw_math_function(enum opcode op);
 287 const char *brw_instruction_name(enum opcode op);
 288 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 289 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 290 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 291
 292 #ifdef __cplusplus
 293 extern "C" {
 294 #endif
 295
 296 struct brw_compiler *
 297 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
 298
 299 bool brw_vs_precompile(struct gl_context *ctx,
 300                        struct gl_shader_program *shader_prog,
 301                        struct gl_program *prog);
 302 bool brw_gs_precompile(struct gl_context *ctx,
 303                        struct gl_shader_program *shader_prog,
 304                        struct gl_program *prog);
 305 bool brw_fs_precompile(struct gl_context *ctx,
 306                        struct gl_shader_program *shader_prog,
 307                        struct gl_program *prog);
 308 bool brw_cs_precompile(struct gl_context *ctx,
 309                        struct gl_shader_program *shader_prog,
 310                        struct gl_program *prog);
 311
 312 int type_size_scalar(const struct glsl_type *type);
 313 int type_size_vec4(const struct glsl_type *type);
 314
 315 #ifdef __cplusplus
 316 }
 317 #endif