2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_defines.h"
27 #include "main/compiler.h"
31 #include "brw_ir_allocator.h"
36 #define MAX_SAMPLER_MESSAGE_SIZE 11
37 #define MAX_VGRF_SIZE 16
40 const struct brw_device_info
*devinfo
;
46 * Array of the ra classes for the unaligned contiguous register
52 * Mapping for register-allocated objects in *regs to the first
53 * GRF for that object.
55 uint8_t *ra_reg_to_grf
;
62 * Array of the ra classes for the unaligned contiguous register
63 * block sizes used, indexed by register size.
68 * Mapping from classes to ra_reg ranges. Each of the per-size
69 * classes corresponds to a range of ra_reg nodes. This array stores
70 * those ranges in the form of first ra_reg in each class and the
71 * total number of ra_reg elements in the last array element. This
72 * way the range of the i'th class is given by:
73 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
75 int class_to_ra_reg_range
[17];
78 * Mapping for register-allocated objects in *regs to the first
79 * GRF for that object.
81 uint8_t *ra_reg_to_grf
;
84 * ra class for the aligned pairs we use for PLN, which doesn't
87 int aligned_pairs_class
;
91 enum PACKED register_file
{
96 HW_REG
, /* a struct brw_reg */
98 UNIFORM
, /* prog_data->params[reg] */
104 bool is_zero() const;
106 bool is_negative_one() const;
107 bool is_null() const;
108 bool is_accumulator() const;
109 bool in_range(const backend_reg
&r
, unsigned n
) const;
112 enum register_file file
; /**< Register file: GRF, MRF, IMM. */
113 enum brw_reg_type type
; /**< Register type: BRW_REGISTER_TYPE_* */
118 * For GRF, it's a virtual register number until register allocation.
120 * For MRF, it's the hardware register.
125 * Offset within the virtual register.
127 * In the scalar backend, this is in units of a float per pixel for pre-
128 * register allocation registers (i.e., one register in SIMD8 mode and two
129 * registers in SIMD16 mode).
131 * For uniforms, this is in units of 1 float.
135 struct brw_reg fixed_hw_reg
;
145 struct backend_instruction
: public exec_node
{
146 bool is_3src() const;
148 bool is_math() const;
149 bool is_control_flow() const;
150 bool is_commutative() const;
151 bool can_do_source_mods() const;
152 bool can_do_saturate() const;
153 bool can_do_cmod() const;
154 bool reads_accumulator_implicitly() const;
155 bool writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const;
157 void remove(bblock_t
*block
);
158 void insert_after(bblock_t
*block
, backend_instruction
*inst
);
159 void insert_before(bblock_t
*block
, backend_instruction
*inst
);
160 void insert_before(bblock_t
*block
, exec_list
*list
);
163 * True if the instruction has side effects other than writing to
164 * its destination registers. You are expected not to reorder or
165 * optimize these out unless you know what you are doing.
167 bool has_side_effects() const;
169 struct backend_instruction
{
170 struct exec_node link
;
173 * Annotation for the generated IR. One of the two can be set.
176 const char *annotation
;
179 uint32_t offset
; /**< spill/unspill offset or texture offset bitfield */
180 uint8_t mlen
; /**< SEND message length */
181 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
182 uint8_t target
; /**< MRT target. */
183 uint8_t regs_written
; /**< Number of registers written by the instruction. */
185 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
186 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
187 enum brw_predicate predicate
;
188 bool predicate_inverse
:1;
189 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
190 bool force_writemask_all
:1;
194 bool shadow_compare
:1;
196 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
197 * mod and predication.
199 unsigned flag_subreg
:1;
201 /** The number of hardware registers used for a message header. */
207 enum instruction_scheduler_mode
{
209 SCHEDULE_PRE_NON_LIFO
,
214 class backend_shader
{
217 backend_shader(struct brw_context
*brw
,
218 struct gl_shader_program
*shader_prog
,
219 struct gl_program
*prog
,
220 struct brw_stage_prog_data
*stage_prog_data
,
221 gl_shader_stage stage
);
225 struct brw_context
* const brw
;
226 const struct brw_device_info
* const devinfo
;
227 struct gl_context
* const ctx
;
228 struct brw_shader
* const shader
;
229 struct gl_shader_program
* const shader_prog
;
230 struct gl_program
* const prog
;
231 struct brw_stage_prog_data
* const stage_prog_data
;
233 /** ralloc context for temporary data used during compile */
237 * List of either fs_inst or vec4_instruction (inheriting from
238 * backend_instruction)
240 exec_list instructions
;
244 gl_shader_stage stage
;
246 const char *stage_name
;
247 const char *stage_abbrev
;
249 brw::simple_allocator alloc
;
251 virtual void dump_instruction(backend_instruction
*inst
) = 0;
252 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
253 virtual void dump_instructions();
254 virtual void dump_instructions(const char *name
);
256 void calculate_cfg();
257 void invalidate_cfg();
259 void assign_common_binding_table_offsets(uint32_t next_binding_table_offset
);
261 virtual void invalidate_live_intervals() = 0;
264 uint32_t brw_texture_offset(int *offsets
, unsigned num_components
);
266 #endif /* __cplusplus */
268 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
269 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
270 uint32_t brw_math_function(enum opcode op
);
271 const char *brw_instruction_name(enum opcode op
);
272 bool brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
273 bool brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
274 bool brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
280 struct brw_compiler
*
281 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
283 bool brw_vs_precompile(struct gl_context
*ctx
,
284 struct gl_shader_program
*shader_prog
,
285 struct gl_program
*prog
);
286 bool brw_gs_precompile(struct gl_context
*ctx
,
287 struct gl_shader_program
*shader_prog
,
288 struct gl_program
*prog
);
289 bool brw_fs_precompile(struct gl_context
*ctx
,
290 struct gl_shader_program
*shader_prog
,
291 struct gl_program
*prog
);
292 bool brw_cs_precompile(struct gl_context
*ctx
,
293 struct gl_shader_program
*shader_prog
,
294 struct gl_program
*prog
);