src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_defines.h"
  26 #include "main/compiler.h"
  27 #include "glsl/ir.h"
  28 #include "intel_asm_printer.h"
  29
  30 #pragma once
  31
  32 enum PACKED register_file {
  33    BAD_FILE,
  34    GRF,
  35    MRF,
  36    IMM,
  37    HW_REG, /* a struct brw_reg */
  38    ATTR,
  39    UNIFORM, /* prog_data->params[reg] */
  40 };
  41
  42 #ifdef __cplusplus
  43
  44 class cfg_t;
  45
  46 struct backend_instruction : public exec_node {
  47 public:
  48    bool is_tex() const;
  49    bool is_math() const;
  50    bool is_control_flow() const;
  51    bool can_do_source_mods() const;
  52    bool can_do_saturate() const;
  53    bool reads_accumulator_implicitly() const;
  54    bool writes_accumulator_implicitly(struct brw_context *brw) const;
  55
  56    /**
  57     * True if the instruction has side effects other than writing to
  58     * its destination registers.  You are expected not to reorder or
  59     * optimize these out unless you know what you are doing.
  60     */
  61    bool has_side_effects() const;
  62
  63    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
  64
  65    uint8_t predicate;
  66    bool predicate_inverse;
  67    bool writes_accumulator; /**< instruction implicitly writes accumulator */
  68
  69    /** @{
  70     * Annotation for the generated IR.  One of the two can be set.
  71     */
  72    const void *ir;
  73    const char *annotation;
  74    /** @} */
  75 };
  76
  77 enum instruction_scheduler_mode {
  78    SCHEDULE_PRE,
  79    SCHEDULE_PRE_NON_LIFO,
  80    SCHEDULE_PRE_LIFO,
  81    SCHEDULE_POST,
  82 };
  83
  84 class backend_visitor : public ir_visitor {
  85 protected:
  86
  87    backend_visitor(struct brw_context *brw,
  88                    struct gl_shader_program *shader_prog,
  89                    struct gl_program *prog,
  90                    struct brw_stage_prog_data *stage_prog_data,
  91                    gl_shader_stage stage);
  92
  93 public:
  94
  95    struct brw_context * const brw;
  96    struct gl_context * const ctx;
  97    struct brw_shader * const shader;
  98    struct gl_shader_program * const shader_prog;
  99    struct gl_program * const prog;
 100    struct brw_stage_prog_data * const stage_prog_data;
 101
 102    /** ralloc context for temporary data used during compile */
 103    void *mem_ctx;
 104
 105    /**
 106     * List of either fs_inst or vec4_instruction (inheriting from
 107     * backend_instruction)
 108     */
 109    exec_list instructions;
 110
 111    virtual void dump_instruction(backend_instruction *inst) = 0;
 112    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 113    virtual void dump_instructions();
 114    virtual void dump_instructions(const char *name);
 115
 116    void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
 117
 118    virtual void invalidate_live_intervals() = 0;
 119 };
 120
 121 uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
 122
 123 void annotate(struct brw_context *brw,
 124               struct annotation_info *annotation, cfg_t *cfg,
 125               backend_instruction *inst, unsigned offset);
 126 void annotation_finalize(struct annotation_info *annotation, unsigned offset);
 127
 128 #endif /* __cplusplus */
 129
 130 int brw_type_for_base_type(const struct glsl_type *type);
 131 uint32_t brw_conditional_for_comparison(unsigned int op);
 132 uint32_t brw_math_function(enum opcode op);
 133 const char *brw_instruction_name(enum opcode op);