2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_defines.h"
27 #include "main/compiler.h"
29 #include "program/prog_parameter.h"
32 #include "brw_ir_allocator.h"
37 #define MAX_SAMPLER_MESSAGE_SIZE 11
38 #define MAX_VGRF_SIZE 16
41 const struct brw_device_info
*devinfo
;
47 * Array of the ra classes for the unaligned contiguous register
53 * Mapping for register-allocated objects in *regs to the first
54 * GRF for that object.
56 uint8_t *ra_reg_to_grf
;
63 * Array of the ra classes for the unaligned contiguous register
64 * block sizes used, indexed by register size.
69 * Mapping from classes to ra_reg ranges. Each of the per-size
70 * classes corresponds to a range of ra_reg nodes. This array stores
71 * those ranges in the form of first ra_reg in each class and the
72 * total number of ra_reg elements in the last array element. This
73 * way the range of the i'th class is given by:
74 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
76 int class_to_ra_reg_range
[17];
79 * Mapping for register-allocated objects in *regs to the first
80 * GRF for that object.
82 uint8_t *ra_reg_to_grf
;
85 * ra class for the aligned pairs we use for PLN, which doesn't
88 int aligned_pairs_class
;
91 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
92 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
98 enum PACKED register_file
{
103 HW_REG
, /* a struct brw_reg */
105 UNIFORM
, /* prog_data->params[reg] */
111 bool is_zero() const;
113 bool is_negative_one() const;
114 bool is_null() const;
115 bool is_accumulator() const;
116 bool in_range(const backend_reg
&r
, unsigned n
) const;
119 enum register_file file
; /**< Register file: GRF, MRF, IMM. */
120 enum brw_reg_type type
; /**< Register type: BRW_REGISTER_TYPE_* */
125 * For GRF, it's a virtual register number until register allocation.
127 * For MRF, it's the hardware register.
132 * Offset within the virtual register.
134 * In the scalar backend, this is in units of a float per pixel for pre-
135 * register allocation registers (i.e., one register in SIMD8 mode and two
136 * registers in SIMD16 mode).
138 * For uniforms, this is in units of 1 float.
142 struct brw_reg fixed_hw_reg
;
152 struct backend_instruction
: public exec_node
{
153 bool is_3src() const;
155 bool is_math() const;
156 bool is_control_flow() const;
157 bool is_commutative() const;
158 bool can_do_source_mods() const;
159 bool can_do_saturate() const;
160 bool can_do_cmod() const;
161 bool reads_accumulator_implicitly() const;
162 bool writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const;
164 void remove(bblock_t
*block
);
165 void insert_after(bblock_t
*block
, backend_instruction
*inst
);
166 void insert_before(bblock_t
*block
, backend_instruction
*inst
);
167 void insert_before(bblock_t
*block
, exec_list
*list
);
170 * True if the instruction has side effects other than writing to
171 * its destination registers. You are expected not to reorder or
172 * optimize these out unless you know what you are doing.
174 bool has_side_effects() const;
176 struct backend_instruction
{
177 struct exec_node link
;
180 * Annotation for the generated IR. One of the two can be set.
183 const char *annotation
;
186 uint32_t offset
; /**< spill/unspill offset or texture offset bitfield */
187 uint8_t mlen
; /**< SEND message length */
188 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
189 uint8_t target
; /**< MRT target. */
190 uint8_t regs_written
; /**< Number of registers written by the instruction. */
192 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
193 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
194 enum brw_predicate predicate
;
195 bool predicate_inverse
:1;
196 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
197 bool force_writemask_all
:1;
201 bool shadow_compare
:1;
203 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
204 * mod and predication.
206 unsigned flag_subreg
:1;
208 /** The number of hardware registers used for a message header. */
214 enum instruction_scheduler_mode
{
216 SCHEDULE_PRE_NON_LIFO
,
221 class backend_shader
{
224 backend_shader(const struct brw_compiler
*compiler
,
227 struct gl_shader_program
*shader_prog
,
228 struct gl_program
*prog
,
229 struct brw_stage_prog_data
*stage_prog_data
,
230 gl_shader_stage stage
);
234 const struct brw_compiler
*compiler
;
235 void *log_data
; /* Passed to compiler->*_log functions */
237 const struct brw_device_info
* const devinfo
;
238 struct brw_shader
* const shader
;
239 struct gl_shader_program
* const shader_prog
;
240 struct gl_program
* const prog
;
241 struct brw_stage_prog_data
* const stage_prog_data
;
243 /** ralloc context for temporary data used during compile */
247 * List of either fs_inst or vec4_instruction (inheriting from
248 * backend_instruction)
250 exec_list instructions
;
254 gl_shader_stage stage
;
256 const char *stage_name
;
257 const char *stage_abbrev
;
259 brw::simple_allocator alloc
;
261 virtual void dump_instruction(backend_instruction
*inst
) = 0;
262 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
263 virtual void dump_instructions();
264 virtual void dump_instructions(const char *name
);
266 void calculate_cfg();
267 void invalidate_cfg();
269 void assign_common_binding_table_offsets(uint32_t next_binding_table_offset
);
271 virtual void invalidate_live_intervals() = 0;
274 uint32_t brw_texture_offset(int *offsets
, unsigned num_components
);
276 void brw_setup_image_uniform_values(gl_shader_stage stage
,
277 struct brw_stage_prog_data
*stage_prog_data
,
278 unsigned param_start_index
,
279 const gl_uniform_storage
*storage
);
281 #endif /* __cplusplus */
283 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
284 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
285 uint32_t brw_math_function(enum opcode op
);
286 const char *brw_instruction_name(enum opcode op
);
287 bool brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
288 bool brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
289 bool brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
295 struct brw_compiler
*
296 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
298 bool brw_vs_precompile(struct gl_context
*ctx
,
299 struct gl_shader_program
*shader_prog
,
300 struct gl_program
*prog
);
301 bool brw_gs_precompile(struct gl_context
*ctx
,
302 struct gl_shader_program
*shader_prog
,
303 struct gl_program
*prog
);
304 bool brw_fs_precompile(struct gl_context
*ctx
,
305 struct gl_shader_program
*shader_prog
,
306 struct gl_program
*prog
);
307 bool brw_cs_precompile(struct gl_context
*ctx
,
308 struct gl_shader_program
*shader_prog
,
309 struct gl_program
*prog
);
311 int type_size_scalar(const struct glsl_type
*type
);
312 int type_size_vec4(const struct glsl_type
*type
);