2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_defines.h"
27 #include "brw_context.h"
28 #include "main/compiler.h"
30 #include "program/prog_parameter.h"
33 #include "brw_ir_allocator.h"
38 #define MAX_SAMPLER_MESSAGE_SIZE 11
39 #define MAX_VGRF_SIZE 16
42 struct backend_reg
: public brw_reg
45 backend_reg(struct brw_reg reg
) : brw_reg(reg
) {}
49 bool is_negative_one() const;
51 bool is_accumulator() const;
52 bool in_range(const backend_reg
&r
, unsigned n
) const;
55 * Offset within the virtual register.
57 * In the scalar backend, this is in units of a float per pixel for pre-
58 * register allocation registers (i.e., one register in SIMD8 mode and two
59 * registers in SIMD16 mode).
61 * For uniforms, this is in units of 1 float.
71 struct backend_instruction
: public exec_node
{
75 bool is_control_flow() const;
76 bool is_commutative() const;
77 bool can_do_source_mods() const;
78 bool can_do_saturate() const;
79 bool can_do_cmod() const;
80 bool reads_accumulator_implicitly() const;
81 bool writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const;
83 void remove(bblock_t
*block
);
84 void insert_after(bblock_t
*block
, backend_instruction
*inst
);
85 void insert_before(bblock_t
*block
, backend_instruction
*inst
);
86 void insert_before(bblock_t
*block
, exec_list
*list
);
89 * True if the instruction has side effects other than writing to
90 * its destination registers. You are expected not to reorder or
91 * optimize these out unless you know what you are doing.
93 bool has_side_effects() const;
96 * True if the instruction might be affected by side effects of other
99 bool is_volatile() const;
101 struct backend_instruction
{
102 struct exec_node link
;
105 * Annotation for the generated IR. One of the two can be set.
108 const char *annotation
;
111 uint32_t offset
; /**< spill/unspill offset or texture offset bitfield */
112 uint8_t mlen
; /**< SEND message length */
113 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
114 uint8_t target
; /**< MRT target. */
115 uint8_t regs_written
; /**< Number of registers written by the instruction. */
117 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
118 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
119 enum brw_predicate predicate
;
120 bool predicate_inverse
:1;
121 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
122 bool force_writemask_all
:1;
126 bool shadow_compare
:1;
128 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
129 * mod and predication.
131 unsigned flag_subreg
:1;
133 /** The number of hardware registers used for a message header. */
139 enum instruction_scheduler_mode
{
141 SCHEDULE_PRE_NON_LIFO
,
146 struct backend_shader
{
149 backend_shader(const struct brw_compiler
*compiler
,
152 const nir_shader
*shader
,
153 struct brw_stage_prog_data
*stage_prog_data
);
157 const struct brw_compiler
*compiler
;
158 void *log_data
; /* Passed to compiler->*_log functions */
160 const struct brw_device_info
* const devinfo
;
161 const nir_shader
*nir
;
162 struct brw_stage_prog_data
* const stage_prog_data
;
164 /** ralloc context for temporary data used during compile */
168 * List of either fs_inst or vec4_instruction (inheriting from
169 * backend_instruction)
171 exec_list instructions
;
175 gl_shader_stage stage
;
177 const char *stage_name
;
178 const char *stage_abbrev
;
180 brw::simple_allocator alloc
;
182 virtual void dump_instruction(backend_instruction
*inst
) = 0;
183 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
184 virtual void dump_instructions();
185 virtual void dump_instructions(const char *name
);
187 void calculate_cfg();
188 void invalidate_cfg();
190 virtual void invalidate_live_intervals() = 0;
193 uint32_t brw_texture_offset(int *offsets
, unsigned num_components
);
195 void brw_setup_image_uniform_values(gl_shader_stage stage
,
196 struct brw_stage_prog_data
*stage_prog_data
,
197 unsigned param_start_index
,
198 const gl_uniform_storage
*storage
);
201 struct backend_shader
;
202 #endif /* __cplusplus */
204 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
205 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
206 uint32_t brw_math_function(enum opcode op
);
207 const char *brw_instruction_name(enum opcode op
);
208 bool brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
209 bool brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
210 bool brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
212 bool opt_predicated_break(struct backend_shader
*s
);
219 * Scratch data used when compiling a GLSL geometry shader.
221 struct brw_gs_compile
223 struct brw_gs_prog_key key
;
224 struct brw_vue_map input_vue_map
;
226 unsigned control_data_bits_per_vertex
;
227 unsigned control_data_header_size_bits
;
230 struct brw_compiler
*
231 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
234 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
235 const struct brw_device_info
*devinfo
,
236 const struct gl_shader_program
*shader_prog
,
237 const struct gl_program
*prog
,
238 struct brw_stage_prog_data
*stage_prog_data
,
239 uint32_t next_binding_table_offset
);
241 bool brw_vs_precompile(struct gl_context
*ctx
,
242 struct gl_shader_program
*shader_prog
,
243 struct gl_program
*prog
);
244 bool brw_gs_precompile(struct gl_context
*ctx
,
245 struct gl_shader_program
*shader_prog
,
246 struct gl_program
*prog
);
247 bool brw_fs_precompile(struct gl_context
*ctx
,
248 struct gl_shader_program
*shader_prog
,
249 struct gl_program
*prog
);
250 bool brw_cs_precompile(struct gl_context
*ctx
,
251 struct gl_shader_program
*shader_prog
,
252 struct gl_program
*prog
);
254 int type_size_scalar(const struct glsl_type
*type
);
255 int type_size_vec4(const struct glsl_type
*type
);
256 int type_size_vec4_times_4(const struct glsl_type
*type
);